src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28
  29 #include "nv_object.xml.h"
  30 #include "nv_m2mf.xml.h"
  31 #include "nv30/nv30-40_3d.xml.h"
  32 #include "nv30/nv01_2d.xml.h"
  33
  34 #include "nouveau_fence.h"
  35 #include "nv30/nv30_screen.h"
  36 #include "nv30/nv30_context.h"
  37 #include "nv30/nv30_resource.h"
  38 #include "nv30/nv30_format.h"
  39
  40 #define RANKINE_0397_CHIPSET 0x00000003
  41 #define RANKINE_0497_CHIPSET 0x000001e0
  42 #define RANKINE_0697_CHIPSET 0x00000010
  43 #define CURIE_4097_CHIPSET   0x00000baf
  44 #define CURIE_4497_CHIPSET   0x00005450
  45 #define CURIE_4497_CHIPSET6X 0x00000088
  46
  47 static int
  48 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  49 {
  50    struct nv30_screen *screen = nv30_screen(pscreen);
  51    struct nouveau_object *eng3d = screen->eng3d;
  52
  53    switch (param) {
  54    /* non-boolean capabilities */
  55    case PIPE_CAP_MAX_RENDER_TARGETS:
  56       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  57    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58       return 13;
  59    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60       return 10;
  61    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62       return 13;
  63    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  64       return 16;
  65    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  66       return 120;
  67    /* supported capabilities */
  68    case PIPE_CAP_TWO_SIDED_STENCIL:
  69    case PIPE_CAP_ANISOTROPIC_FILTER:
  70    case PIPE_CAP_POINT_SPRITE:
  71    case PIPE_CAP_OCCLUSION_QUERY:
  72    case PIPE_CAP_QUERY_TIME_ELAPSED:
  73    case PIPE_CAP_QUERY_TIMESTAMP:
  74    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  75    case PIPE_CAP_TEXTURE_SWIZZLE:
  76    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  77    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  78    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  79    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  80    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  81    case PIPE_CAP_TGSI_TEXCOORD:
  82    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  83    case PIPE_CAP_USER_INDEX_BUFFERS:
  84       return 1;
  85    case PIPE_CAP_USER_VERTEX_BUFFERS:
  86       return 0;
  87    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  88       return 16;
  89    /* nv4x capabilities */
  90    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  91    case PIPE_CAP_NPOT_TEXTURES:
  92    case PIPE_CAP_CONDITIONAL_RENDER:
  93    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  94    case PIPE_CAP_PRIMITIVE_RESTART:
  95       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  96    /* unsupported */
  97    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  98    case PIPE_CAP_SM3:
  99    case PIPE_CAP_INDEP_BLEND_ENABLE:
 100    case PIPE_CAP_INDEP_BLEND_FUNC:
 101    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 102    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 103    case PIPE_CAP_TGSI_INSTANCEID:
 104    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 105    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 106    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 107    case PIPE_CAP_MIN_TEXEL_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 111    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 112    case PIPE_CAP_TEXTURE_BARRIER:
 113    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 114    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 115    case PIPE_CAP_CUBE_MAP_ARRAY:
 116    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 117    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 118    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 119    case PIPE_CAP_START_INSTANCE:
 120    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 121    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 122    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 123    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 124    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 125    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 126    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 127    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 128    case PIPE_CAP_TGSI_VS_LAYER:
 129       return 0;
 130    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 131    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 132    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 133    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 134       return 1;
 135    case PIPE_CAP_ENDIANNESS:
 136       return PIPE_ENDIAN_LITTLE;
 137    default:
 138       debug_printf("unknown param %d\n", param);
 139       return 0;
 140    }
 141 }
 142
 143 static float
 144 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 145 {
 146    struct nv30_screen *screen = nv30_screen(pscreen);
 147    struct nouveau_object *eng3d = screen->eng3d;
 148
 149    switch (param) {
 150    case PIPE_CAPF_MAX_LINE_WIDTH:
 151    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 152       return 10.0;
 153    case PIPE_CAPF_MAX_POINT_WIDTH:
 154    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 155       return 64.0;
 156    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 157       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 158    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 159       return 15.0;
 160    default:
 161       debug_printf("unknown paramf %d\n", param);
 162       return 0;
 163    }
 164 }
 165
 166 static int
 167 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 168                              enum pipe_shader_cap param)
 169 {
 170    struct nv30_screen *screen = nv30_screen(pscreen);
 171    struct nouveau_object *eng3d = screen->eng3d;
 172
 173    switch (shader) {
 174    case PIPE_SHADER_VERTEX:
 175       switch (param) {
 176       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 177       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 178          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 179       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 180       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 181          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 182       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 183          return 0;
 184       case PIPE_SHADER_CAP_MAX_INPUTS:
 185          return 16;
 186       case PIPE_SHADER_CAP_MAX_CONSTS:
 187          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 188       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 189          return 1;
 190       case PIPE_SHADER_CAP_MAX_TEMPS:
 191          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 192       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 193       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 194          return 0;
 195       case PIPE_SHADER_CAP_MAX_ADDRS:
 196          return 2;
 197       case PIPE_SHADER_CAP_MAX_PREDS:
 198       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 199       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 200       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 201       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 202       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 203       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 204       case PIPE_SHADER_CAP_SUBROUTINES:
 205       case PIPE_SHADER_CAP_INTEGERS:
 206          return 0;
 207       default:
 208          debug_printf("unknown vertex shader param %d\n", param);
 209          return 0;
 210       }
 211       break;
 212    case PIPE_SHADER_FRAGMENT:
 213       switch (param) {
 214       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 215       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 216       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 217       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 218          return 4096;
 219       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 220          return 0;
 221       case PIPE_SHADER_CAP_MAX_INPUTS:
 222          return (eng3d->oclass >= NV40_3D_CLASS) ? 12 : 10;
 223       case PIPE_SHADER_CAP_MAX_CONSTS:
 224          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 225       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 226          return 1;
 227       case PIPE_SHADER_CAP_MAX_TEMPS:
 228          return 32;
 229       case PIPE_SHADER_CAP_MAX_ADDRS:
 230          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 231       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 232       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 233          return 16;
 234       case PIPE_SHADER_CAP_MAX_PREDS:
 235       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 236       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 237       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 238       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 239       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 240       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 241       case PIPE_SHADER_CAP_SUBROUTINES:
 242          return 0;
 243       default:
 244          debug_printf("unknown fragment shader param %d\n", param);
 245          return 0;
 246       }
 247       break;
 248    default:
 249       return 0;
 250    }
 251 }
 252
 253 static boolean
 254 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 255                                 enum pipe_format format,
 256                                 enum pipe_texture_target target,
 257                                 unsigned sample_count,
 258                                 unsigned bindings)
 259 {
 260    if (sample_count > 4)
 261       return FALSE;
 262    if (!(0x00000017 & (1 << sample_count)))
 263       return FALSE;
 264
 265    if (!util_format_is_supported(format, bindings)) {
 266       return FALSE;
 267    }
 268
 269    /* transfers & shared are always supported */
 270    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 271                  PIPE_BIND_TRANSFER_WRITE |
 272                  PIPE_BIND_SHARED);
 273
 274    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 275 }
 276
 277 static void
 278 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 279 {
 280    struct nv30_screen *screen = nv30_screen(pscreen);
 281    struct nouveau_pushbuf *push = screen->base.pushbuf;
 282
 283    *sequence = ++screen->base.fence.sequence;
 284
 285    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 286    PUSH_DATA (push, 0);
 287    PUSH_DATA (push, *sequence);
 288 }
 289
 290 static uint32_t
 291 nv30_screen_fence_update(struct pipe_screen *pscreen)
 292 {
 293    struct nv30_screen *screen = nv30_screen(pscreen);
 294    struct nv04_notify *fence = screen->fence->data;
 295    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 296 }
 297
 298 static void
 299 nv30_screen_destroy(struct pipe_screen *pscreen)
 300 {
 301    struct nv30_screen *screen = nv30_screen(pscreen);
 302
 303    if (screen->base.fence.current &&
 304        screen->base.fence.current->state >= NOUVEAU_FENCE_STATE_EMITTED) {
 305       nouveau_fence_wait(screen->base.fence.current);
 306       nouveau_fence_ref (NULL, &screen->base.fence.current);
 307    }
 308
 309    nouveau_object_del(&screen->query);
 310    nouveau_object_del(&screen->fence);
 311    nouveau_object_del(&screen->ntfy);
 312
 313    nouveau_object_del(&screen->sifm);
 314    nouveau_object_del(&screen->swzsurf);
 315    nouveau_object_del(&screen->surf2d);
 316    nouveau_object_del(&screen->m2mf);
 317    nouveau_object_del(&screen->eng3d);
 318    nouveau_object_del(&screen->null);
 319
 320    nouveau_screen_fini(&screen->base);
 321    FREE(screen);
 322 }
 323
 324 #define FAIL_SCREEN_INIT(str, err)                    \
 325    do {                                               \
 326       NOUVEAU_ERR(str, err);                          \
 327       nv30_screen_destroy(pscreen);                   \
 328       return NULL;                                    \
 329    } while(0)
 330
 331 struct pipe_screen *
 332 nv30_screen_create(struct nouveau_device *dev)
 333 {
 334    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 335    struct pipe_screen *pscreen;
 336    struct nouveau_pushbuf *push;
 337    struct nv04_fifo *fifo;
 338    unsigned oclass = 0;
 339    int ret, i;
 340
 341    if (!screen)
 342       return NULL;
 343
 344    switch (dev->chipset & 0xf0) {
 345    case 0x30:
 346       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 347          oclass = NV30_3D_CLASS;
 348       else
 349       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 350          oclass = NV34_3D_CLASS;
 351       else
 352       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 353          oclass = NV35_3D_CLASS;
 354       break;
 355    case 0x40:
 356       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 357          oclass = NV40_3D_CLASS;
 358       else
 359       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 360          oclass = NV44_3D_CLASS;
 361       break;
 362    case 0x60:
 363       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 364          oclass = NV44_3D_CLASS;
 365       break;
 366    default:
 367       break;
 368    }
 369
 370    if (!oclass) {
 371       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 372       FREE(screen);
 373       return NULL;
 374    }
 375
 376    pscreen = &screen->base.base;
 377    pscreen->destroy = nv30_screen_destroy;
 378    pscreen->get_param = nv30_screen_get_param;
 379    pscreen->get_paramf = nv30_screen_get_paramf;
 380    pscreen->get_shader_param = nv30_screen_get_shader_param;
 381    pscreen->context_create = nv30_context_create;
 382    pscreen->is_format_supported = nv30_screen_is_format_supported;
 383    nv30_resource_screen_init(pscreen);
 384    nouveau_screen_init_vdec(&screen->base);
 385
 386    screen->base.fence.emit = nv30_screen_fence_emit;
 387    screen->base.fence.update = nv30_screen_fence_update;
 388
 389    ret = nouveau_screen_init(&screen->base, dev);
 390    if (ret)
 391       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 392
 393    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 394    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 395    if (oclass == NV40_3D_CLASS) {
 396       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 397       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 398    }
 399
 400    fifo = screen->base.channel->data;
 401    push = screen->base.pushbuf;
 402    push->rsvd_kick = 16;
 403
 404    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 405                             NULL, 0, &screen->null);
 406    if (ret)
 407       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 408
 409    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 410     * this means that the address pointed at by the DMA object must
 411     * be 4KiB aligned, which means this object needs to be the first
 412     * one allocated on the channel.
 413     */
 414    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 415                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 416                             .length = 32 }, sizeof(struct nv04_notify),
 417                             &screen->fence);
 418    if (ret)
 419       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 420
 421    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 422    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 423                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 424                             .length = 32 }, sizeof(struct nv04_notify),
 425                             &screen->ntfy);
 426    if (ret)
 427       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 428
 429    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 430     * the remainder of the "notifier block" assigned by the kernel for
 431     * use as query objects
 432     */
 433    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 434                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 435                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 436                             &screen->query);
 437    if (ret)
 438       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 439
 440    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 441    if (ret)
 442       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 443
 444    LIST_INITHEAD(&screen->queries);
 445
 446    /* Vertex program resources (code/data), currently 6 of the constant
 447     * slots are reserved to implement user clipping planes
 448     */
 449    if (oclass < NV40_3D_CLASS) {
 450       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 451       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 452    } else {
 453       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 454       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 455    }
 456
 457    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 458    if (ret == 0)
 459       nouveau_bo_map(screen->notify, 0, screen->base.client);
 460    if (ret)
 461       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 462
 463    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 464                             NULL, 0, &screen->eng3d);
 465    if (ret)
 466       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 467
 468    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 469    PUSH_DATA (push, screen->eng3d->handle);
 470    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 471    PUSH_DATA (push, screen->ntfy->handle);
 472    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 473    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 474    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 475    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 476    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 477    PUSH_DATA (push, fifo->vram);     /* ZETA */
 478    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 479    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 480    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 481    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 482    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 483    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 484    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 485       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 486       PUSH_DATA (push, 0x00100000);
 487       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 488       PUSH_DATA (push, 3);
 489
 490       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 491       PUSH_DATA (push, 0);
 492       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 493       PUSH_DATA (push, fui(0.0));
 494       PUSH_DATA (push, fui(0.0));
 495       PUSH_DATA (push, fui(1.0));
 496       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 497       for (i = 0; i < 16; i++)
 498          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 499
 500       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 501       PUSH_DATA (push, 0);
 502    } else {
 503       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 504       PUSH_DATA (push, fifo->vram);
 505       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 506
 507       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 508       PUSH_DATA (push, 0x00000004);
 509
 510       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 511       PUSH_DATA (push, 0x00000010);
 512       PUSH_DATA (push, 0x01000100);
 513       PUSH_DATA (push, 0xff800006);
 514
 515       /* vtxprog output routing */
 516       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 517       PUSH_DATA (push, 0x06144321);
 518       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 519       PUSH_DATA (push, 0xedcba987);
 520       PUSH_DATA (push, 0x0000006f);
 521       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 522       PUSH_DATA (push, 0x00171615);
 523       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 524       PUSH_DATA (push, 0x001b1a19);
 525
 526       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 527       PUSH_DATA (push, 0x0020ffff);
 528       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 529       PUSH_DATA (push, 0x01d300d4);
 530
 531       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 532       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 533    }
 534
 535    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 536                             NULL, 0, &screen->m2mf);
 537    if (ret)
 538       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 539
 540    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 541    PUSH_DATA (push, screen->m2mf->handle);
 542    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 543    PUSH_DATA (push, screen->ntfy->handle);
 544
 545    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 546                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 547    if (ret)
 548       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 549
 550    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 551    PUSH_DATA (push, screen->surf2d->handle);
 552    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 553    PUSH_DATA (push, screen->ntfy->handle);
 554
 555    if (dev->chipset < 0x40)
 556       oclass = NV30_SURFACE_SWZ_CLASS;
 557    else
 558       oclass = NV40_SURFACE_SWZ_CLASS;
 559
 560    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 561                             NULL, 0, &screen->swzsurf);
 562    if (ret)
 563       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 564
 565    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 566    PUSH_DATA (push, screen->swzsurf->handle);
 567    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 568    PUSH_DATA (push, screen->ntfy->handle);
 569
 570    if (dev->chipset < 0x40)
 571       oclass = NV30_SIFM_CLASS;
 572    else
 573       oclass = NV40_SIFM_CLASS;
 574
 575    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 576                             NULL, 0, &screen->sifm);
 577    if (ret)
 578       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 579
 580    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 581    PUSH_DATA (push, screen->sifm->handle);
 582    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 583    PUSH_DATA (push, screen->ntfy->handle);
 584    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 585    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 586
 587    nouveau_pushbuf_kick(push, push->channel);
 588
 589    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 590    return pscreen;
 591 }