src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28
  29 #include "nv_object.xml.h"
  30 #include "nv_m2mf.xml.h"
  31 #include "nv30/nv30-40_3d.xml.h"
  32 #include "nv30/nv01_2d.xml.h"
  33
  34 #include "nouveau_fence.h"
  35 #include "nv30/nv30_screen.h"
  36 #include "nv30/nv30_context.h"
  37 #include "nv30/nv30_resource.h"
  38 #include "nv30/nv30_format.h"
  39
  40 #define RANKINE_0397_CHIPSET 0x00000003
  41 #define RANKINE_0497_CHIPSET 0x000001e0
  42 #define RANKINE_0697_CHIPSET 0x00000010
  43 #define CURIE_4097_CHIPSET   0x00000baf
  44 #define CURIE_4497_CHIPSET   0x00005450
  45 #define CURIE_4497_CHIPSET6X 0x00000088
  46
  47 static int
  48 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  49 {
  50    struct nv30_screen *screen = nv30_screen(pscreen);
  51    struct nouveau_object *eng3d = screen->eng3d;
  52
  53    switch (param) {
  54    /* non-boolean capabilities */
  55    case PIPE_CAP_MAX_RENDER_TARGETS:
  56       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  57    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58       return 13;
  59    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60       return 10;
  61    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62       return 13;
  63    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  64       return 120;
  65    /* supported capabilities */
  66    case PIPE_CAP_TWO_SIDED_STENCIL:
  67    case PIPE_CAP_ANISOTROPIC_FILTER:
  68    case PIPE_CAP_POINT_SPRITE:
  69    case PIPE_CAP_OCCLUSION_QUERY:
  70    case PIPE_CAP_QUERY_TIME_ELAPSED:
  71    case PIPE_CAP_QUERY_TIMESTAMP:
  72    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  73    case PIPE_CAP_TEXTURE_SWIZZLE:
  74    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  75    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  76    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  77    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  78    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  79    case PIPE_CAP_TGSI_TEXCOORD:
  80    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  81    case PIPE_CAP_USER_INDEX_BUFFERS:
  82       return 1;
  83    case PIPE_CAP_USER_VERTEX_BUFFERS:
  84       return 0;
  85    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  86       return 16;
  87    case PIPE_CAP_MAX_VIEWPORTS:
  88       return 1;
  89    /* nv4x capabilities */
  90    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  91    case PIPE_CAP_NPOT_TEXTURES:
  92    case PIPE_CAP_CONDITIONAL_RENDER:
  93    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  94    case PIPE_CAP_PRIMITIVE_RESTART:
  95       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  96    /* unsupported */
  97    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  98    case PIPE_CAP_SM3:
  99    case PIPE_CAP_INDEP_BLEND_ENABLE:
 100    case PIPE_CAP_INDEP_BLEND_FUNC:
 101    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 102    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 103    case PIPE_CAP_TGSI_INSTANCEID:
 104    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 105    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 106    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 107    case PIPE_CAP_MIN_TEXEL_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 111    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 112    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 113    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 114    case PIPE_CAP_TEXTURE_BARRIER:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 116    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 117    case PIPE_CAP_CUBE_MAP_ARRAY:
 118    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 119    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 120    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 121    case PIPE_CAP_START_INSTANCE:
 122    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 123    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 124    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 125    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 126    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 127    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 128    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 129    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 130    case PIPE_CAP_TGSI_VS_LAYER:
 131    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 132    case PIPE_CAP_TEXTURE_GATHER_SM5:
 133    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 134       return 0;
 135    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 136    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 137    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 138    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 139       return 1;
 140    case PIPE_CAP_ENDIANNESS:
 141       return PIPE_ENDIAN_LITTLE;
 142    default:
 143       debug_printf("unknown param %d\n", param);
 144       return 0;
 145    }
 146 }
 147
 148 static float
 149 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 150 {
 151    struct nv30_screen *screen = nv30_screen(pscreen);
 152    struct nouveau_object *eng3d = screen->eng3d;
 153
 154    switch (param) {
 155    case PIPE_CAPF_MAX_LINE_WIDTH:
 156    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 157       return 10.0;
 158    case PIPE_CAPF_MAX_POINT_WIDTH:
 159    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 160       return 64.0;
 161    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 162       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 163    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 164       return 15.0;
 165    default:
 166       debug_printf("unknown paramf %d\n", param);
 167       return 0;
 168    }
 169 }
 170
 171 static int
 172 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 173                              enum pipe_shader_cap param)
 174 {
 175    struct nv30_screen *screen = nv30_screen(pscreen);
 176    struct nouveau_object *eng3d = screen->eng3d;
 177
 178    switch (shader) {
 179    case PIPE_SHADER_VERTEX:
 180       switch (param) {
 181       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 182       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 183          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 184       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 185       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 186          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 187       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 188          return 0;
 189       case PIPE_SHADER_CAP_MAX_INPUTS:
 190          return 16;
 191       case PIPE_SHADER_CAP_MAX_CONSTS:
 192          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 193       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 194          return 1;
 195       case PIPE_SHADER_CAP_MAX_TEMPS:
 196          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 197       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 198       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 199          return 0;
 200       case PIPE_SHADER_CAP_MAX_ADDRS:
 201          return 2;
 202       case PIPE_SHADER_CAP_MAX_PREDS:
 203       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 204       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 205       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 206       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 207       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 208       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 209       case PIPE_SHADER_CAP_SUBROUTINES:
 210       case PIPE_SHADER_CAP_INTEGERS:
 211          return 0;
 212       default:
 213          debug_printf("unknown vertex shader param %d\n", param);
 214          return 0;
 215       }
 216       break;
 217    case PIPE_SHADER_FRAGMENT:
 218       switch (param) {
 219       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 220       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 221       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 222       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 223          return 4096;
 224       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 225          return 0;
 226       case PIPE_SHADER_CAP_MAX_INPUTS:
 227          return 8; /* should be possible to do 10 with nv4x */
 228       case PIPE_SHADER_CAP_MAX_CONSTS:
 229          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 230       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 231          return 1;
 232       case PIPE_SHADER_CAP_MAX_TEMPS:
 233          return 32;
 234       case PIPE_SHADER_CAP_MAX_ADDRS:
 235          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 236       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 237       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 238          return 16;
 239       case PIPE_SHADER_CAP_MAX_PREDS:
 240       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 241       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 242       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 243       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 244       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 245       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 246       case PIPE_SHADER_CAP_SUBROUTINES:
 247          return 0;
 248       default:
 249          debug_printf("unknown fragment shader param %d\n", param);
 250          return 0;
 251       }
 252       break;
 253    default:
 254       return 0;
 255    }
 256 }
 257
 258 static boolean
 259 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 260                                 enum pipe_format format,
 261                                 enum pipe_texture_target target,
 262                                 unsigned sample_count,
 263                                 unsigned bindings)
 264 {
 265    if (sample_count > 4)
 266       return FALSE;
 267    if (!(0x00000017 & (1 << sample_count)))
 268       return FALSE;
 269
 270    if (!util_format_is_supported(format, bindings)) {
 271       return FALSE;
 272    }
 273
 274    /* transfers & shared are always supported */
 275    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 276                  PIPE_BIND_TRANSFER_WRITE |
 277                  PIPE_BIND_SHARED);
 278
 279    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 280 }
 281
 282 static void
 283 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 284 {
 285    struct nv30_screen *screen = nv30_screen(pscreen);
 286    struct nouveau_pushbuf *push = screen->base.pushbuf;
 287
 288    *sequence = ++screen->base.fence.sequence;
 289
 290    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 291    PUSH_DATA (push, 0);
 292    PUSH_DATA (push, *sequence);
 293 }
 294
 295 static uint32_t
 296 nv30_screen_fence_update(struct pipe_screen *pscreen)
 297 {
 298    struct nv30_screen *screen = nv30_screen(pscreen);
 299    struct nv04_notify *fence = screen->fence->data;
 300    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 301 }
 302
 303 static void
 304 nv30_screen_destroy(struct pipe_screen *pscreen)
 305 {
 306    struct nv30_screen *screen = nv30_screen(pscreen);
 307
 308    if (!nouveau_drm_screen_unref(&screen->base))
 309       return;
 310
 311    if (screen->base.fence.current &&
 312        screen->base.fence.current->state >= NOUVEAU_FENCE_STATE_EMITTED) {
 313       nouveau_fence_wait(screen->base.fence.current);
 314       nouveau_fence_ref (NULL, &screen->base.fence.current);
 315    }
 316
 317    nouveau_object_del(&screen->query);
 318    nouveau_object_del(&screen->fence);
 319    nouveau_object_del(&screen->ntfy);
 320
 321    nouveau_object_del(&screen->sifm);
 322    nouveau_object_del(&screen->swzsurf);
 323    nouveau_object_del(&screen->surf2d);
 324    nouveau_object_del(&screen->m2mf);
 325    nouveau_object_del(&screen->eng3d);
 326    nouveau_object_del(&screen->null);
 327
 328    nouveau_screen_fini(&screen->base);
 329    FREE(screen);
 330 }
 331
 332 #define FAIL_SCREEN_INIT(str, err)                    \
 333    do {                                               \
 334       NOUVEAU_ERR(str, err);                          \
 335       nv30_screen_destroy(pscreen);                   \
 336       return NULL;                                    \
 337    } while(0)
 338
 339 struct pipe_screen *
 340 nv30_screen_create(struct nouveau_device *dev)
 341 {
 342    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 343    struct pipe_screen *pscreen;
 344    struct nouveau_pushbuf *push;
 345    struct nv04_fifo *fifo;
 346    unsigned oclass = 0;
 347    int ret, i;
 348
 349    if (!screen)
 350       return NULL;
 351
 352    switch (dev->chipset & 0xf0) {
 353    case 0x30:
 354       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 355          oclass = NV30_3D_CLASS;
 356       else
 357       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 358          oclass = NV34_3D_CLASS;
 359       else
 360       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 361          oclass = NV35_3D_CLASS;
 362       break;
 363    case 0x40:
 364       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 365          oclass = NV40_3D_CLASS;
 366       else
 367       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 368          oclass = NV44_3D_CLASS;
 369       break;
 370    case 0x60:
 371       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 372          oclass = NV44_3D_CLASS;
 373       break;
 374    default:
 375       break;
 376    }
 377
 378    if (!oclass) {
 379       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 380       FREE(screen);
 381       return NULL;
 382    }
 383
 384    pscreen = &screen->base.base;
 385    pscreen->destroy = nv30_screen_destroy;
 386    pscreen->get_param = nv30_screen_get_param;
 387    pscreen->get_paramf = nv30_screen_get_paramf;
 388    pscreen->get_shader_param = nv30_screen_get_shader_param;
 389    pscreen->context_create = nv30_context_create;
 390    pscreen->is_format_supported = nv30_screen_is_format_supported;
 391    nv30_resource_screen_init(pscreen);
 392    nouveau_screen_init_vdec(&screen->base);
 393
 394    screen->base.fence.emit = nv30_screen_fence_emit;
 395    screen->base.fence.update = nv30_screen_fence_update;
 396
 397    ret = nouveau_screen_init(&screen->base, dev);
 398    if (ret)
 399       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 400
 401    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 402    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 403    if (oclass == NV40_3D_CLASS) {
 404       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 405       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 406    }
 407
 408    fifo = screen->base.channel->data;
 409    push = screen->base.pushbuf;
 410    push->rsvd_kick = 16;
 411
 412    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 413                             NULL, 0, &screen->null);
 414    if (ret)
 415       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 416
 417    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 418     * this means that the address pointed at by the DMA object must
 419     * be 4KiB aligned, which means this object needs to be the first
 420     * one allocated on the channel.
 421     */
 422    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 423                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 424                             .length = 32 }, sizeof(struct nv04_notify),
 425                             &screen->fence);
 426    if (ret)
 427       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 428
 429    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 430    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 431                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 432                             .length = 32 }, sizeof(struct nv04_notify),
 433                             &screen->ntfy);
 434    if (ret)
 435       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 436
 437    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 438     * the remainder of the "notifier block" assigned by the kernel for
 439     * use as query objects
 440     */
 441    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 442                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 443                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 444                             &screen->query);
 445    if (ret)
 446       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 447
 448    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 449    if (ret)
 450       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 451
 452    LIST_INITHEAD(&screen->queries);
 453
 454    /* Vertex program resources (code/data), currently 6 of the constant
 455     * slots are reserved to implement user clipping planes
 456     */
 457    if (oclass < NV40_3D_CLASS) {
 458       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 459       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 460    } else {
 461       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 462       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 463    }
 464
 465    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 466    if (ret == 0)
 467       nouveau_bo_map(screen->notify, 0, screen->base.client);
 468    if (ret)
 469       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 470
 471    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 472                             NULL, 0, &screen->eng3d);
 473    if (ret)
 474       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 475
 476    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 477    PUSH_DATA (push, screen->eng3d->handle);
 478    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 479    PUSH_DATA (push, screen->ntfy->handle);
 480    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 481    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 482    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 483    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 484    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 485    PUSH_DATA (push, fifo->vram);     /* ZETA */
 486    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 487    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 488    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 489    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 490    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 491    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 492    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 493       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 494       PUSH_DATA (push, 0x00100000);
 495       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 496       PUSH_DATA (push, 3);
 497
 498       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 499       PUSH_DATA (push, 0);
 500       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 501       PUSH_DATA (push, fui(0.0));
 502       PUSH_DATA (push, fui(0.0));
 503       PUSH_DATA (push, fui(1.0));
 504       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 505       for (i = 0; i < 16; i++)
 506          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 507
 508       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 509       PUSH_DATA (push, 0);
 510    } else {
 511       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 512       PUSH_DATA (push, fifo->vram);
 513       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 514
 515       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 516       PUSH_DATA (push, 0x00000004);
 517
 518       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 519       PUSH_DATA (push, 0x00000010);
 520       PUSH_DATA (push, 0x01000100);
 521       PUSH_DATA (push, 0xff800006);
 522
 523       /* vtxprog output routing */
 524       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 525       PUSH_DATA (push, 0x06144321);
 526       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 527       PUSH_DATA (push, 0xedcba987);
 528       PUSH_DATA (push, 0x0000006f);
 529       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 530       PUSH_DATA (push, 0x00171615);
 531       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 532       PUSH_DATA (push, 0x001b1a19);
 533
 534       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 535       PUSH_DATA (push, 0x0020ffff);
 536       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 537       PUSH_DATA (push, 0x01d300d4);
 538
 539       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 540       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 541    }
 542
 543    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 544                             NULL, 0, &screen->m2mf);
 545    if (ret)
 546       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 547
 548    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 549    PUSH_DATA (push, screen->m2mf->handle);
 550    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 551    PUSH_DATA (push, screen->ntfy->handle);
 552
 553    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 554                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 555    if (ret)
 556       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 557
 558    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 559    PUSH_DATA (push, screen->surf2d->handle);
 560    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 561    PUSH_DATA (push, screen->ntfy->handle);
 562
 563    if (dev->chipset < 0x40)
 564       oclass = NV30_SURFACE_SWZ_CLASS;
 565    else
 566       oclass = NV40_SURFACE_SWZ_CLASS;
 567
 568    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 569                             NULL, 0, &screen->swzsurf);
 570    if (ret)
 571       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 572
 573    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 574    PUSH_DATA (push, screen->swzsurf->handle);
 575    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 576    PUSH_DATA (push, screen->ntfy->handle);
 577
 578    if (dev->chipset < 0x40)
 579       oclass = NV30_SIFM_CLASS;
 580    else
 581       oclass = NV40_SIFM_CLASS;
 582
 583    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 584                             NULL, 0, &screen->sifm);
 585    if (ret)
 586       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 587
 588    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 589    PUSH_DATA (push, screen->sifm->handle);
 590    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 591    PUSH_DATA (push, screen->ntfy->handle);
 592    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 593    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 594
 595    nouveau_pushbuf_kick(push, push->channel);
 596
 597    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 598    return pscreen;
 599 }