src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include <xf86drm.h>
  27 #include <nouveau_drm.h>
  28 #include "util/u_format.h"
  29 #include "util/u_format_s3tc.h"
  30
  31 #include "nv_object.xml.h"
  32 #include "nv_m2mf.xml.h"
  33 #include "nv30/nv30-40_3d.xml.h"
  34 #include "nv30/nv01_2d.xml.h"
  35
  36 #include "nouveau_fence.h"
  37 #include "nv30/nv30_screen.h"
  38 #include "nv30/nv30_context.h"
  39 #include "nv30/nv30_resource.h"
  40 #include "nv30/nv30_format.h"
  41
  42 #define RANKINE_0397_CHIPSET 0x00000003
  43 #define RANKINE_0497_CHIPSET 0x000001e0
  44 #define RANKINE_0697_CHIPSET 0x00000010
  45 #define CURIE_4097_CHIPSET   0x00000baf
  46 #define CURIE_4497_CHIPSET   0x00005450
  47 #define CURIE_4497_CHIPSET6X 0x00000088
  48
  49 static int
  50 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52    struct nv30_screen *screen = nv30_screen(pscreen);
  53    struct nouveau_object *eng3d = screen->eng3d;
  54    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  55
  56    switch (param) {
  57    /* non-boolean capabilities */
  58    case PIPE_CAP_MAX_RENDER_TARGETS:
  59       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  60    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  63       return 10;
  64    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  65       return 13;
  66    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  67       return 120;
  68    case PIPE_CAP_ENDIANNESS:
  69       return PIPE_ENDIAN_LITTLE;
  70    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  71       return 16;
  72    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  73       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  74    case PIPE_CAP_MAX_VIEWPORTS:
  75       return 1;
  76    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  77       return 2048;
  78    /* supported capabilities */
  79    case PIPE_CAP_TWO_SIDED_STENCIL:
  80    case PIPE_CAP_ANISOTROPIC_FILTER:
  81    case PIPE_CAP_POINT_SPRITE:
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83    case PIPE_CAP_QUERY_TIME_ELAPSED:
  84    case PIPE_CAP_QUERY_TIMESTAMP:
  85    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  88    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  89    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  90    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  91    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  92    case PIPE_CAP_TGSI_TEXCOORD:
  93    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  94    case PIPE_CAP_USER_INDEX_BUFFERS:
  95    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  96    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  97    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  98    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  99    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 100       return 1;
 101    /* nv35 capabilities */
 102    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 103       return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
 104    /* nv4x capabilities */
 105    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 106    case PIPE_CAP_NPOT_TEXTURES:
 107    case PIPE_CAP_CONDITIONAL_RENDER:
 108    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 109    case PIPE_CAP_PRIMITIVE_RESTART:
 110       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 111    /* unsupported */
 112    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 113    case PIPE_CAP_SM3:
 114    case PIPE_CAP_INDEP_BLEND_ENABLE:
 115    case PIPE_CAP_INDEP_BLEND_FUNC:
 116    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 117    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 118    case PIPE_CAP_TGSI_INSTANCEID:
 119    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 121    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 122    case PIPE_CAP_MIN_TEXEL_OFFSET:
 123    case PIPE_CAP_MAX_TEXEL_OFFSET:
 124    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130    case PIPE_CAP_MAX_VERTEX_STREAMS:
 131    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 132    case PIPE_CAP_TEXTURE_BARRIER:
 133    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 135    case PIPE_CAP_CUBE_MAP_ARRAY:
 136    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 137    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 138    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 139    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 140    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 141    case PIPE_CAP_START_INSTANCE:
 142    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 143    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 146    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 147    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 148    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 149    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 150    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 151    case PIPE_CAP_TEXTURE_GATHER_SM5:
 152    case PIPE_CAP_FAKE_SW_MSAA:
 153    case PIPE_CAP_TEXTURE_QUERY_LOD:
 154    case PIPE_CAP_SAMPLE_SHADING:
 155    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 156    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 157    case PIPE_CAP_USER_VERTEX_BUFFERS:
 158    case PIPE_CAP_COMPUTE:
 159    case PIPE_CAP_DRAW_INDIRECT:
 160    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 161    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 162    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 163    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 164    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 165    case PIPE_CAP_CLIP_HALFZ:
 166    case PIPE_CAP_VERTEXID_NOBASE:
 167    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 168    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 169    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 170    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 171    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 172    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 173    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 174    case PIPE_CAP_TGSI_TXQS:
 175    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 176    case PIPE_CAP_SHAREABLE_SHADERS:
 177    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 178    case PIPE_CAP_CLEAR_TEXTURE:
 179    case PIPE_CAP_DRAW_PARAMETERS:
 180    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 181    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 182    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 183    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 184    case PIPE_CAP_INVALIDATE_BUFFER:
 185    case PIPE_CAP_GENERATE_MIPMAP:
 186    case PIPE_CAP_STRING_MARKER:
 187    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 188    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 189    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 190    case PIPE_CAP_QUERY_MEMORY_INFO:
 191    case PIPE_CAP_PCI_GROUP:
 192    case PIPE_CAP_PCI_BUS:
 193    case PIPE_CAP_PCI_DEVICE:
 194    case PIPE_CAP_PCI_FUNCTION:
 195    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 196       return 0;
 197
 198    case PIPE_CAP_VENDOR_ID:
 199       return 0x10de;
 200    case PIPE_CAP_DEVICE_ID: {
 201       uint64_t device_id;
 202       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 203          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 204          return -1;
 205       }
 206       return device_id;
 207    }
 208    case PIPE_CAP_ACCELERATED:
 209       return 1;
 210    case PIPE_CAP_VIDEO_MEMORY:
 211       return dev->vram_size >> 20;
 212    case PIPE_CAP_UMA:
 213       return 0;
 214    }
 215
 216    debug_printf("unknown param %d\n", param);
 217    return 0;
 218 }
 219
 220 static float
 221 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 222 {
 223    struct nv30_screen *screen = nv30_screen(pscreen);
 224    struct nouveau_object *eng3d = screen->eng3d;
 225
 226    switch (param) {
 227    case PIPE_CAPF_MAX_LINE_WIDTH:
 228    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 229       return 10.0;
 230    case PIPE_CAPF_MAX_POINT_WIDTH:
 231    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 232       return 64.0;
 233    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 234       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 235    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 236       return 15.0;
 237    default:
 238       debug_printf("unknown paramf %d\n", param);
 239       return 0;
 240    }
 241 }
 242
 243 static int
 244 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 245                              enum pipe_shader_cap param)
 246 {
 247    struct nv30_screen *screen = nv30_screen(pscreen);
 248    struct nouveau_object *eng3d = screen->eng3d;
 249
 250    switch (shader) {
 251    case PIPE_SHADER_VERTEX:
 252       switch (param) {
 253       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 254       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 255          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 256       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 257       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 258          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 259       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 260          return 0;
 261       case PIPE_SHADER_CAP_MAX_INPUTS:
 262       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 263          return 16;
 264       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 265          return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
 266       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 267          return 1;
 268       case PIPE_SHADER_CAP_MAX_TEMPS:
 269          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 270       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 271       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 272          return 0;
 273       case PIPE_SHADER_CAP_MAX_PREDS:
 274       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 275       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 276       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 277       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 278       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 279       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 280       case PIPE_SHADER_CAP_SUBROUTINES:
 281       case PIPE_SHADER_CAP_INTEGERS:
 282       case PIPE_SHADER_CAP_DOUBLES:
 283       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 284       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 285       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 286       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 287       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 288       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 289          return 0;
 290       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 291          return 32;
 292       default:
 293          debug_printf("unknown vertex shader param %d\n", param);
 294          return 0;
 295       }
 296       break;
 297    case PIPE_SHADER_FRAGMENT:
 298       switch (param) {
 299       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 300       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 301       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 302       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 303          return 4096;
 304       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 305          return 0;
 306       case PIPE_SHADER_CAP_MAX_INPUTS:
 307          return 8; /* should be possible to do 10 with nv4x */
 308       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 309          return 4;
 310       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 311          return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
 312       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 313          return 1;
 314       case PIPE_SHADER_CAP_MAX_TEMPS:
 315          return 32;
 316       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 317       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 318          return 16;
 319       case PIPE_SHADER_CAP_MAX_PREDS:
 320       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 321       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 322       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 323       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 324       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 325       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 326       case PIPE_SHADER_CAP_SUBROUTINES:
 327       case PIPE_SHADER_CAP_DOUBLES:
 328       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 329       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 330       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 331       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 332       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 333       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 334          return 0;
 335       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 336          return 32;
 337       default:
 338          debug_printf("unknown fragment shader param %d\n", param);
 339          return 0;
 340       }
 341       break;
 342    default:
 343       return 0;
 344    }
 345 }
 346
 347 static boolean
 348 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 349                                 enum pipe_format format,
 350                                 enum pipe_texture_target target,
 351                                 unsigned sample_count,
 352                                 unsigned bindings)
 353 {
 354    if (sample_count > nv30_screen(pscreen)->max_sample_count)
 355       return false;
 356
 357    if (!(0x00000017 & (1 << sample_count)))
 358       return false;
 359
 360    if (!util_format_is_supported(format, bindings)) {
 361       return false;
 362    }
 363
 364    /* transfers & shared are always supported */
 365    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 366                  PIPE_BIND_TRANSFER_WRITE |
 367                  PIPE_BIND_SHARED);
 368
 369    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 370 }
 371
 372 static void
 373 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 374 {
 375    struct nv30_screen *screen = nv30_screen(pscreen);
 376    struct nouveau_pushbuf *push = screen->base.pushbuf;
 377
 378    *sequence = ++screen->base.fence.sequence;
 379
 380    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
 381    PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
 382               (2 /* size */ << 18) | (7 /* subchan */ << 13));
 383    PUSH_DATA (push, 0);
 384    PUSH_DATA (push, *sequence);
 385 }
 386
 387 static uint32_t
 388 nv30_screen_fence_update(struct pipe_screen *pscreen)
 389 {
 390    struct nv30_screen *screen = nv30_screen(pscreen);
 391    struct nv04_notify *fence = screen->fence->data;
 392    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 393 }
 394
 395 static void
 396 nv30_screen_destroy(struct pipe_screen *pscreen)
 397 {
 398    struct nv30_screen *screen = nv30_screen(pscreen);
 399
 400    if (!nouveau_drm_screen_unref(&screen->base))
 401       return;
 402
 403    if (screen->base.fence.current) {
 404       struct nouveau_fence *current = NULL;
 405
 406       /* nouveau_fence_wait will create a new current fence, so wait on the
 407        * _current_ one, and remove both.
 408        */
 409       nouveau_fence_ref(screen->base.fence.current, &current);
 410       nouveau_fence_wait(current, NULL);
 411       nouveau_fence_ref(NULL, &current);
 412       nouveau_fence_ref(NULL, &screen->base.fence.current);
 413    }
 414
 415    nouveau_bo_ref(NULL, &screen->notify);
 416
 417    nouveau_heap_destroy(&screen->query_heap);
 418    nouveau_heap_destroy(&screen->vp_exec_heap);
 419    nouveau_heap_destroy(&screen->vp_data_heap);
 420
 421    nouveau_object_del(&screen->query);
 422    nouveau_object_del(&screen->fence);
 423    nouveau_object_del(&screen->ntfy);
 424
 425    nouveau_object_del(&screen->sifm);
 426    nouveau_object_del(&screen->swzsurf);
 427    nouveau_object_del(&screen->surf2d);
 428    nouveau_object_del(&screen->m2mf);
 429    nouveau_object_del(&screen->eng3d);
 430    nouveau_object_del(&screen->null);
 431
 432    nouveau_screen_fini(&screen->base);
 433    FREE(screen);
 434 }
 435
 436 #define FAIL_SCREEN_INIT(str, err)                    \
 437    do {                                               \
 438       NOUVEAU_ERR(str, err);                          \
 439       screen->base.base.context_create = NULL;        \
 440       return &screen->base;                           \
 441    } while(0)
 442
 443 struct nouveau_screen *
 444 nv30_screen_create(struct nouveau_device *dev)
 445 {
 446    struct nv30_screen *screen;
 447    struct pipe_screen *pscreen;
 448    struct nouveau_pushbuf *push;
 449    struct nv04_fifo *fifo;
 450    unsigned oclass = 0;
 451    int ret, i;
 452
 453    switch (dev->chipset & 0xf0) {
 454    case 0x30:
 455       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 456          oclass = NV30_3D_CLASS;
 457       else
 458       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 459          oclass = NV34_3D_CLASS;
 460       else
 461       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 462          oclass = NV35_3D_CLASS;
 463       break;
 464    case 0x40:
 465       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 466          oclass = NV40_3D_CLASS;
 467       else
 468       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 469          oclass = NV44_3D_CLASS;
 470       break;
 471    case 0x60:
 472       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 473          oclass = NV44_3D_CLASS;
 474       break;
 475    default:
 476       break;
 477    }
 478
 479    if (!oclass) {
 480       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 481       return NULL;
 482    }
 483
 484    screen = CALLOC_STRUCT(nv30_screen);
 485    if (!screen)
 486       return NULL;
 487
 488    pscreen = &screen->base.base;
 489    pscreen->destroy = nv30_screen_destroy;
 490
 491    /*
 492     * Some modern apps try to use msaa without keeping in mind the
 493     * restrictions on videomem of older cards. Resulting in dmesg saying:
 494     * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
 495     * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
 496     * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
 497     *
 498     * Because we are running out of video memory, after which the program
 499     * using the msaa visual freezes, and eventually the entire system freezes.
 500     *
 501     * To work around this we do not allow msaa visauls by default and allow
 502     * the user to override this via NV30_MAX_MSAA.
 503     */
 504    screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
 505    if (screen->max_sample_count > 4)
 506       screen->max_sample_count = 4;
 507
 508    pscreen->get_param = nv30_screen_get_param;
 509    pscreen->get_paramf = nv30_screen_get_paramf;
 510    pscreen->get_shader_param = nv30_screen_get_shader_param;
 511    pscreen->context_create = nv30_context_create;
 512    pscreen->is_format_supported = nv30_screen_is_format_supported;
 513    nv30_resource_screen_init(pscreen);
 514    nouveau_screen_init_vdec(&screen->base);
 515
 516    screen->base.fence.emit = nv30_screen_fence_emit;
 517    screen->base.fence.update = nv30_screen_fence_update;
 518
 519    ret = nouveau_screen_init(&screen->base, dev);
 520    if (ret)
 521       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 522
 523    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 524    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 525    if (oclass == NV40_3D_CLASS) {
 526       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 527       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 528    }
 529
 530    fifo = screen->base.channel->data;
 531    push = screen->base.pushbuf;
 532    push->rsvd_kick = 16;
 533
 534    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 535                             NULL, 0, &screen->null);
 536    if (ret)
 537       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 538
 539    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 540     * this means that the address pointed at by the DMA object must
 541     * be 4KiB aligned, which means this object needs to be the first
 542     * one allocated on the channel.
 543     */
 544    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 545                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 546                             .length = 32 }, sizeof(struct nv04_notify),
 547                             &screen->fence);
 548    if (ret)
 549       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 550
 551    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 552    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 553                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 554                             .length = 32 }, sizeof(struct nv04_notify),
 555                             &screen->ntfy);
 556    if (ret)
 557       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 558
 559    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 560     * the remainder of the "notifier block" assigned by the kernel for
 561     * use as query objects
 562     */
 563    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 564                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 565                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 566                             &screen->query);
 567    if (ret)
 568       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 569
 570    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 571    if (ret)
 572       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 573
 574    LIST_INITHEAD(&screen->queries);
 575
 576    /* Vertex program resources (code/data), currently 6 of the constant
 577     * slots are reserved to implement user clipping planes
 578     */
 579    if (oclass < NV40_3D_CLASS) {
 580       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 581       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 582    } else {
 583       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 584       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 585    }
 586
 587    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 588    if (ret == 0)
 589       ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
 590    if (ret)
 591       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 592
 593    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 594                             NULL, 0, &screen->eng3d);
 595    if (ret)
 596       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 597
 598    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 599    PUSH_DATA (push, screen->eng3d->handle);
 600    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 601    PUSH_DATA (push, screen->ntfy->handle);
 602    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 603    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 604    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 605    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 606    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 607    PUSH_DATA (push, fifo->vram);     /* ZETA */
 608    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 609    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 610    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 611    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 612    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 613    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 614    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 615       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 616       PUSH_DATA (push, 0x00100000);
 617       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 618       PUSH_DATA (push, 3);
 619
 620       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 621       PUSH_DATA (push, 0);
 622       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 623       PUSH_DATA (push, fui(0.0));
 624       PUSH_DATA (push, fui(0.0));
 625       PUSH_DATA (push, fui(1.0));
 626       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 627       for (i = 0; i < 16; i++)
 628          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 629
 630       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 631       PUSH_DATA (push, 0);
 632    } else {
 633       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 634       PUSH_DATA (push, fifo->vram);
 635       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 636
 637       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 638       PUSH_DATA (push, 0x00000004);
 639
 640       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 641       PUSH_DATA (push, 0x00000010);
 642       PUSH_DATA (push, 0x01000100);
 643       PUSH_DATA (push, 0xff800006);
 644
 645       /* vtxprog output routing */
 646       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 647       PUSH_DATA (push, 0x06144321);
 648       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 649       PUSH_DATA (push, 0xedcba987);
 650       PUSH_DATA (push, 0x0000006f);
 651       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 652       PUSH_DATA (push, 0x00171615);
 653       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 654       PUSH_DATA (push, 0x001b1a19);
 655
 656       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 657       PUSH_DATA (push, 0x0020ffff);
 658       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 659       PUSH_DATA (push, 0x01d300d4);
 660
 661       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 662       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 663    }
 664
 665    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 666                             NULL, 0, &screen->m2mf);
 667    if (ret)
 668       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 669
 670    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 671    PUSH_DATA (push, screen->m2mf->handle);
 672    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 673    PUSH_DATA (push, screen->ntfy->handle);
 674
 675    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 676                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 677    if (ret)
 678       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 679
 680    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 681    PUSH_DATA (push, screen->surf2d->handle);
 682    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 683    PUSH_DATA (push, screen->ntfy->handle);
 684
 685    if (dev->chipset < 0x40)
 686       oclass = NV30_SURFACE_SWZ_CLASS;
 687    else
 688       oclass = NV40_SURFACE_SWZ_CLASS;
 689
 690    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 691                             NULL, 0, &screen->swzsurf);
 692    if (ret)
 693       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 694
 695    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 696    PUSH_DATA (push, screen->swzsurf->handle);
 697    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 698    PUSH_DATA (push, screen->ntfy->handle);
 699
 700    if (dev->chipset < 0x40)
 701       oclass = NV30_SIFM_CLASS;
 702    else
 703       oclass = NV40_SIFM_CLASS;
 704
 705    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 706                             NULL, 0, &screen->sifm);
 707    if (ret)
 708       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 709
 710    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 711    PUSH_DATA (push, screen->sifm->handle);
 712    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 713    PUSH_DATA (push, screen->ntfy->handle);
 714    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 715    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 716
 717    nouveau_pushbuf_kick(push, push->channel);
 718
 719    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
 720    return &screen->base;
 721 }