1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_dynarray.h"
5 #include "util/u_linkage.h"
6 #include "util/u_debug.h"
8 #include "pipe/p_shader_tokens.h"
9 #include "tgsi/tgsi_parse.h"
10 #include "tgsi/tgsi_dump.h"
11 #include "tgsi/tgsi_util.h"
12 #include "tgsi/tgsi_ureg.h"
14 #include "draw/draw_context.h"
16 #include "nv_object.xml.h"
17 #include "nouveau_debug.h"
18 #include "nv30/nv30-40_3d.xml.h"
19 #include "nv30/nv30_state.h"
21 /* TODO (at least...):
22 * 1. Indexed consts + ARL
23 * 3. NV_vp11, NV_vp2, NV_vp3 features
24 * - extra arith opcodes
32 #include "nv30/nv30_vertprog.h"
33 #include "nv30/nv40_vertprog.h"
35 struct nvfx_loop_entry
{
41 struct pipe_shader_state pipe
;
42 struct nv30_vertprog
*vp
;
43 struct tgsi_shader_info
* info
;
45 struct nv30_vertprog_exec
*vpi
;
48 unsigned r_temps_discard
;
49 struct nvfx_reg r_result
[PIPE_MAX_SHADER_OUTPUTS
];
50 struct nvfx_reg
*r_address
;
51 struct nvfx_reg
*r_temp
;
52 struct nvfx_reg
*r_const
;
53 struct nvfx_reg r_0_1
;
63 struct util_dynarray label_relocs
;
64 struct util_dynarray loop_stack
;
67 static struct nvfx_reg
68 temp(struct nvfx_vpc
*vpc
)
70 int idx
= ffs(~vpc
->r_temps
) - 1;
73 NOUVEAU_ERR("out of temps!!\n");
75 return nvfx_reg(NVFXSR_TEMP
, 0);
78 vpc
->r_temps
|= (1 << idx
);
79 vpc
->r_temps_discard
|= (1 << idx
);
80 return nvfx_reg(NVFXSR_TEMP
, idx
);
84 release_temps(struct nvfx_vpc
*vpc
)
86 vpc
->r_temps
&= ~vpc
->r_temps_discard
;
87 vpc
->r_temps_discard
= 0;
90 static struct nvfx_reg
91 constant(struct nvfx_vpc
*vpc
, int pipe
, float x
, float y
, float z
, float w
)
93 struct nv30_vertprog
*vp
= vpc
->vp
;
94 struct nv30_vertprog_data
*vpd
;
98 for (idx
= 0; idx
< vp
->nr_consts
; idx
++) {
99 if (vp
->consts
[idx
].index
== pipe
)
100 return nvfx_reg(NVFXSR_CONST
, idx
);
104 idx
= vp
->nr_consts
++;
105 vp
->consts
= realloc(vp
->consts
, sizeof(*vpd
) * vp
->nr_consts
);
106 vpd
= &vp
->consts
[idx
];
113 return nvfx_reg(NVFXSR_CONST
, idx
);
116 #define arith(s,t,o,d,m,s0,s1,s2) \
117 nvfx_insn((s), (NVFX_VP_INST_SLOT_##t << 7) | NVFX_VP_INST_##t##_OP_##o, -1, (d), (m), (s0), (s1), (s2))
120 emit_src(struct nvfx_vpc
*vpc
, uint32_t *hw
,
121 int pos
, struct nvfx_src src
)
123 struct nv30_vertprog
*vp
= vpc
->vp
;
125 struct nvfx_relocation reloc
;
127 switch (src
.reg
.type
) {
129 sr
|= (NVFX_VP(SRC_REG_TYPE_TEMP
) << NVFX_VP(SRC_REG_TYPE_SHIFT
));
130 sr
|= (src
.reg
.index
<< NVFX_VP(SRC_TEMP_SRC_SHIFT
));
133 sr
|= (NVFX_VP(SRC_REG_TYPE_INPUT
) <<
134 NVFX_VP(SRC_REG_TYPE_SHIFT
));
135 vp
->ir
|= (1 << src
.reg
.index
);
136 hw
[1] |= (src
.reg
.index
<< NVFX_VP(INST_INPUT_SRC_SHIFT
));
139 sr
|= (NVFX_VP(SRC_REG_TYPE_CONST
) <<
140 NVFX_VP(SRC_REG_TYPE_SHIFT
));
141 if (src
.reg
.index
< 256 && src
.reg
.index
>= -256) {
142 reloc
.location
= vp
->nr_insns
- 1;
143 reloc
.target
= src
.reg
.index
;
144 util_dynarray_append(&vp
->const_relocs
, struct nvfx_relocation
, reloc
);
146 hw
[1] |= (src
.reg
.index
<< NVFX_VP(INST_CONST_SRC_SHIFT
)) &
147 NVFX_VP(INST_CONST_SRC_MASK
);
151 sr
|= (NVFX_VP(SRC_REG_TYPE_INPUT
) <<
152 NVFX_VP(SRC_REG_TYPE_SHIFT
));
159 sr
|= NVFX_VP(SRC_NEGATE
);
162 hw
[0] |= (1 << (21 + pos
));
164 sr
|= ((src
.swz
[0] << NVFX_VP(SRC_SWZ_X_SHIFT
)) |
165 (src
.swz
[1] << NVFX_VP(SRC_SWZ_Y_SHIFT
)) |
166 (src
.swz
[2] << NVFX_VP(SRC_SWZ_Z_SHIFT
)) |
167 (src
.swz
[3] << NVFX_VP(SRC_SWZ_W_SHIFT
)));
170 if(src
.reg
.type
== NVFXSR_CONST
)
171 hw
[3] |= NVFX_VP(INST_INDEX_CONST
);
172 else if(src
.reg
.type
== NVFXSR_INPUT
)
173 hw
[0] |= NVFX_VP(INST_INDEX_INPUT
);
178 hw
[0] |= NVFX_VP(INST_ADDR_REG_SELECT_1
);
179 hw
[0] |= src
.indirect_swz
<< NVFX_VP(INST_ADDR_SWZ_SHIFT
);
184 hw
[1] |= ((sr
& NVFX_VP(SRC0_HIGH_MASK
)) >>
185 NVFX_VP(SRC0_HIGH_SHIFT
)) << NVFX_VP(INST_SRC0H_SHIFT
);
186 hw
[2] |= (sr
& NVFX_VP(SRC0_LOW_MASK
)) <<
187 NVFX_VP(INST_SRC0L_SHIFT
);
190 hw
[2] |= sr
<< NVFX_VP(INST_SRC1_SHIFT
);
193 hw
[2] |= ((sr
& NVFX_VP(SRC2_HIGH_MASK
)) >>
194 NVFX_VP(SRC2_HIGH_SHIFT
)) << NVFX_VP(INST_SRC2H_SHIFT
);
195 hw
[3] |= (sr
& NVFX_VP(SRC2_LOW_MASK
)) <<
196 NVFX_VP(INST_SRC2L_SHIFT
);
204 emit_dst(struct nvfx_vpc
*vpc
, uint32_t *hw
,
205 int slot
, struct nvfx_reg dst
)
207 struct nv30_vertprog
*vp
= vpc
->vp
;
212 hw
[0] |= NV30_VP_INST_DEST_TEMP_ID_MASK
;
214 hw
[3] |= NV40_VP_INST_DEST_MASK
;
216 hw
[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK
;
218 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
223 hw
[0] |= (dst
.index
<< NV30_VP_INST_DEST_TEMP_ID_SHIFT
);
225 hw
[3] |= NV40_VP_INST_DEST_MASK
;
227 hw
[0] |= (dst
.index
<< NV40_VP_INST_VEC_DEST_TEMP_SHIFT
);
229 hw
[3] |= (dst
.index
<< NV40_VP_INST_SCA_DEST_TEMP_SHIFT
);
233 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
236 case NV30_VP_INST_DEST_CLP(0):
237 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
240 case NV30_VP_INST_DEST_CLP(1):
241 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
244 case NV30_VP_INST_DEST_CLP(2):
245 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
248 case NV30_VP_INST_DEST_CLP(3):
249 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
252 case NV30_VP_INST_DEST_CLP(4):
253 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
256 case NV30_VP_INST_DEST_CLP(5):
257 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
260 case NV40_VP_INST_DEST_COL0
: vp
->or |= (1 << 0); break;
261 case NV40_VP_INST_DEST_COL1
: vp
->or |= (1 << 1); break;
262 case NV40_VP_INST_DEST_BFC0
: vp
->or |= (1 << 2); break;
263 case NV40_VP_INST_DEST_BFC1
: vp
->or |= (1 << 3); break;
264 case NV40_VP_INST_DEST_FOGC
: vp
->or |= (1 << 4); break;
265 case NV40_VP_INST_DEST_PSZ
: vp
->or |= (1 << 5); break;
270 hw
[3] |= (dst
.index
<< NV30_VP_INST_DEST_SHIFT
);
271 hw
[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK
;
273 /*XXX: no way this is entirely correct, someone needs to
274 * figure out what exactly it is.
278 hw
[3] |= (dst
.index
<< NV40_VP_INST_DEST_SHIFT
);
280 hw
[0] |= NV40_VP_INST_VEC_RESULT
;
281 hw
[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK
;
283 hw
[3] |= NV40_VP_INST_SCA_RESULT
;
284 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
294 nvfx_vp_emit(struct nvfx_vpc
*vpc
, struct nvfx_insn insn
)
296 struct nv30_vertprog
*vp
= vpc
->vp
;
297 unsigned slot
= insn
.op
>> 7;
298 unsigned op
= insn
.op
& 0x7f;
301 vp
->insns
= realloc(vp
->insns
, ++vp
->nr_insns
* sizeof(*vpc
->vpi
));
302 vpc
->vpi
= &vp
->insns
[vp
->nr_insns
- 1];
303 memset(vpc
->vpi
, 0, sizeof(*vpc
->vpi
));
307 if (insn
.cc_test
!= NVFX_COND_TR
)
308 hw
[0] |= NVFX_VP(INST_COND_TEST_ENABLE
);
309 hw
[0] |= (insn
.cc_test
<< NVFX_VP(INST_COND_SHIFT
));
310 hw
[0] |= ((insn
.cc_swz
[0] << NVFX_VP(INST_COND_SWZ_X_SHIFT
)) |
311 (insn
.cc_swz
[1] << NVFX_VP(INST_COND_SWZ_Y_SHIFT
)) |
312 (insn
.cc_swz
[2] << NVFX_VP(INST_COND_SWZ_Z_SHIFT
)) |
313 (insn
.cc_swz
[3] << NVFX_VP(INST_COND_SWZ_W_SHIFT
)));
315 hw
[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE
);
318 assert(vpc
->is_nv4x
);
320 hw
[0] |= NV40_VP_INST_SATURATE
;
325 hw
[1] |= (op
<< NV30_VP_INST_VEC_OPCODE_SHIFT
);
327 hw
[0] |= ((op
>> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT
);
328 hw
[1] |= ((op
& 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT
);
330 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
331 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
333 if (insn
.dst
.type
== NVFXSR_OUTPUT
) {
335 hw
[3] |= (insn
.mask
<< NV30_VP_INST_SDEST_WRITEMASK_SHIFT
);
337 hw
[3] |= (insn
.mask
<< NV30_VP_INST_VDEST_WRITEMASK_SHIFT
);
340 hw
[3] |= (insn
.mask
<< NV30_VP_INST_STEMP_WRITEMASK_SHIFT
);
342 hw
[3] |= (insn
.mask
<< NV30_VP_INST_VTEMP_WRITEMASK_SHIFT
);
346 hw
[1] |= (op
<< NV40_VP_INST_VEC_OPCODE_SHIFT
);
347 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
348 hw
[3] |= (insn
.mask
<< NV40_VP_INST_VEC_WRITEMASK_SHIFT
);
350 hw
[1] |= (op
<< NV40_VP_INST_SCA_OPCODE_SHIFT
);
351 hw
[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK
;
352 hw
[3] |= (insn
.mask
<< NV40_VP_INST_SCA_WRITEMASK_SHIFT
);
356 emit_dst(vpc
, hw
, slot
, insn
.dst
);
357 emit_src(vpc
, hw
, 0, insn
.src
[0]);
358 emit_src(vpc
, hw
, 1, insn
.src
[1]);
359 emit_src(vpc
, hw
, 2, insn
.src
[2]);
361 // if(insn.src[0].indirect || op == NVFX_VP_INST_VEC_OP_ARL)
362 // hw[3] |= NV40_VP_INST_SCA_RESULT;
365 static inline struct nvfx_src
366 tgsi_src(struct nvfx_vpc
*vpc
, const struct tgsi_full_src_register
*fsrc
) {
369 switch (fsrc
->Register
.File
) {
370 case TGSI_FILE_INPUT
:
371 src
.reg
= nvfx_reg(NVFXSR_INPUT
, fsrc
->Register
.Index
);
373 case TGSI_FILE_CONSTANT
:
374 if(fsrc
->Register
.Indirect
) {
375 src
.reg
= vpc
->r_const
[0];
376 src
.reg
.index
= fsrc
->Register
.Index
;
378 src
.reg
= vpc
->r_const
[fsrc
->Register
.Index
];
381 case TGSI_FILE_IMMEDIATE
:
382 src
.reg
= vpc
->imm
[fsrc
->Register
.Index
];
384 case TGSI_FILE_TEMPORARY
:
385 src
.reg
= vpc
->r_temp
[fsrc
->Register
.Index
];
388 NOUVEAU_ERR("bad src file\n");
394 src
.abs
= fsrc
->Register
.Absolute
;
395 src
.negate
= fsrc
->Register
.Negate
;
396 src
.swz
[0] = fsrc
->Register
.SwizzleX
;
397 src
.swz
[1] = fsrc
->Register
.SwizzleY
;
398 src
.swz
[2] = fsrc
->Register
.SwizzleZ
;
399 src
.swz
[3] = fsrc
->Register
.SwizzleW
;
401 src
.indirect_reg
= 0;
402 src
.indirect_swz
= 0;
404 if(fsrc
->Register
.Indirect
) {
405 if(fsrc
->Indirect
.File
== TGSI_FILE_ADDRESS
&&
406 (fsrc
->Register
.File
== TGSI_FILE_CONSTANT
||
407 fsrc
->Register
.File
== TGSI_FILE_INPUT
)) {
409 src
.indirect_reg
= fsrc
->Indirect
.Index
;
410 src
.indirect_swz
= fsrc
->Indirect
.Swizzle
;
420 static INLINE
struct nvfx_reg
421 tgsi_dst(struct nvfx_vpc
*vpc
, const struct tgsi_full_dst_register
*fdst
) {
424 switch (fdst
->Register
.File
) {
426 dst
= nvfx_reg(NVFXSR_NONE
, 0);
428 case TGSI_FILE_OUTPUT
:
429 dst
= vpc
->r_result
[fdst
->Register
.Index
];
431 case TGSI_FILE_TEMPORARY
:
432 dst
= vpc
->r_temp
[fdst
->Register
.Index
];
434 case TGSI_FILE_ADDRESS
:
435 dst
= vpc
->r_address
[fdst
->Register
.Index
];
438 NOUVEAU_ERR("bad dst file %i\n", fdst
->Register
.File
);
452 if (tgsi
& TGSI_WRITEMASK_X
) mask
|= NVFX_VP_MASK_X
;
453 if (tgsi
& TGSI_WRITEMASK_Y
) mask
|= NVFX_VP_MASK_Y
;
454 if (tgsi
& TGSI_WRITEMASK_Z
) mask
|= NVFX_VP_MASK_Z
;
455 if (tgsi
& TGSI_WRITEMASK_W
) mask
|= NVFX_VP_MASK_W
;
460 nvfx_vertprog_parse_instruction(struct nvfx_vpc
*vpc
,
461 unsigned idx
, const struct tgsi_full_instruction
*finst
)
463 struct nvfx_src src
[3], tmp
;
465 struct nvfx_reg final_dst
;
466 struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
467 struct nvfx_insn insn
;
468 struct nvfx_relocation reloc
;
469 struct nvfx_loop_entry loop
;
472 int ai
= -1, ci
= -1, ii
= -1;
474 unsigned sub_depth
= 0;
476 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
477 const struct tgsi_full_src_register
*fsrc
;
479 fsrc
= &finst
->Src
[i
];
480 if (fsrc
->Register
.File
== TGSI_FILE_TEMPORARY
) {
481 src
[i
] = tgsi_src(vpc
, fsrc
);
485 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
486 const struct tgsi_full_src_register
*fsrc
;
488 fsrc
= &finst
->Src
[i
];
490 switch (fsrc
->Register
.File
) {
491 case TGSI_FILE_INPUT
:
492 if (ai
== -1 || ai
== fsrc
->Register
.Index
) {
493 ai
= fsrc
->Register
.Index
;
494 src
[i
] = tgsi_src(vpc
, fsrc
);
496 src
[i
] = nvfx_src(temp(vpc
));
497 nvfx_vp_emit(vpc
, arith(0, VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
,
498 tgsi_src(vpc
, fsrc
), none
, none
));
501 case TGSI_FILE_CONSTANT
:
502 if ((ci
== -1 && ii
== -1) ||
503 ci
== fsrc
->Register
.Index
) {
504 ci
= fsrc
->Register
.Index
;
505 src
[i
] = tgsi_src(vpc
, fsrc
);
507 src
[i
] = nvfx_src(temp(vpc
));
508 nvfx_vp_emit(vpc
, arith(0, VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
,
509 tgsi_src(vpc
, fsrc
), none
, none
));
512 case TGSI_FILE_IMMEDIATE
:
513 if ((ci
== -1 && ii
== -1) ||
514 ii
== fsrc
->Register
.Index
) {
515 ii
= fsrc
->Register
.Index
;
516 src
[i
] = tgsi_src(vpc
, fsrc
);
518 src
[i
] = nvfx_src(temp(vpc
));
519 nvfx_vp_emit(vpc
, arith(0, VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
,
520 tgsi_src(vpc
, fsrc
), none
, none
));
523 case TGSI_FILE_TEMPORARY
:
527 NOUVEAU_ERR("bad src file\n");
532 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
533 if(src
[i
].reg
.type
< 0)
537 if(finst
->Dst
[0].Register
.File
== TGSI_FILE_ADDRESS
&&
538 finst
->Instruction
.Opcode
!= TGSI_OPCODE_ARL
)
541 final_dst
= dst
= tgsi_dst(vpc
, &finst
->Dst
[0]);
542 mask
= tgsi_mask(finst
->Dst
[0].Register
.WriteMask
);
543 if(finst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
) {
544 assert(finst
->Instruction
.Opcode
!= TGSI_OPCODE_ARL
);
548 if(dst
.type
!= NVFXSR_TEMP
)
552 switch (finst
->Instruction
.Opcode
) {
553 case TGSI_OPCODE_ABS
:
554 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MOV
, dst
, mask
, abs(src
[0]), none
, none
));
556 case TGSI_OPCODE_ADD
:
557 nvfx_vp_emit(vpc
, arith(sat
, VEC
, ADD
, dst
, mask
, src
[0], none
, src
[1]));
559 case TGSI_OPCODE_ARL
:
560 nvfx_vp_emit(vpc
, arith(0, VEC
, ARL
, dst
, mask
, src
[0], none
, none
));
562 case TGSI_OPCODE_CEIL
:
563 tmp
= nvfx_src(temp(vpc
));
564 nvfx_vp_emit(vpc
, arith(0, VEC
, FLR
, tmp
.reg
, mask
, neg(src
[0]), none
, none
));
565 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MOV
, dst
, mask
, neg(tmp
), none
, none
));
567 case TGSI_OPCODE_CMP
:
568 insn
= arith(0, VEC
, MOV
, none
.reg
, mask
, src
[0], none
, none
);
570 nvfx_vp_emit(vpc
, insn
);
572 insn
= arith(sat
, VEC
, MOV
, dst
, mask
, src
[2], none
, none
);
573 insn
.cc_test
= NVFX_COND_GE
;
574 nvfx_vp_emit(vpc
, insn
);
576 insn
= arith(sat
, VEC
, MOV
, dst
, mask
, src
[1], none
, none
);
577 insn
.cc_test
= NVFX_COND_LT
;
578 nvfx_vp_emit(vpc
, insn
);
580 case TGSI_OPCODE_COS
:
581 nvfx_vp_emit(vpc
, arith(sat
, SCA
, COS
, dst
, mask
, none
, none
, src
[0]));
583 case TGSI_OPCODE_DP2
:
584 tmp
= nvfx_src(temp(vpc
));
585 nvfx_vp_emit(vpc
, arith(0, VEC
, MUL
, tmp
.reg
, NVFX_VP_MASK_X
| NVFX_VP_MASK_Y
, src
[0], src
[1], none
));
586 nvfx_vp_emit(vpc
, arith(sat
, VEC
, ADD
, dst
, mask
, swz(tmp
, X
, X
, X
, X
), none
, swz(tmp
, Y
, Y
, Y
, Y
)));
588 case TGSI_OPCODE_DP3
:
589 nvfx_vp_emit(vpc
, arith(sat
, VEC
, DP3
, dst
, mask
, src
[0], src
[1], none
));
591 case TGSI_OPCODE_DP4
:
592 nvfx_vp_emit(vpc
, arith(sat
, VEC
, DP4
, dst
, mask
, src
[0], src
[1], none
));
594 case TGSI_OPCODE_DPH
:
595 nvfx_vp_emit(vpc
, arith(sat
, VEC
, DPH
, dst
, mask
, src
[0], src
[1], none
));
597 case TGSI_OPCODE_DST
:
598 nvfx_vp_emit(vpc
, arith(sat
, VEC
, DST
, dst
, mask
, src
[0], src
[1], none
));
600 case TGSI_OPCODE_EX2
:
601 nvfx_vp_emit(vpc
, arith(sat
, SCA
, EX2
, dst
, mask
, none
, none
, src
[0]));
603 case TGSI_OPCODE_EXP
:
604 nvfx_vp_emit(vpc
, arith(sat
, SCA
, EXP
, dst
, mask
, none
, none
, src
[0]));
606 case TGSI_OPCODE_FLR
:
607 nvfx_vp_emit(vpc
, arith(sat
, VEC
, FLR
, dst
, mask
, src
[0], none
, none
));
609 case TGSI_OPCODE_FRC
:
610 nvfx_vp_emit(vpc
, arith(sat
, VEC
, FRC
, dst
, mask
, src
[0], none
, none
));
612 case TGSI_OPCODE_LG2
:
613 nvfx_vp_emit(vpc
, arith(sat
, SCA
, LG2
, dst
, mask
, none
, none
, src
[0]));
615 case TGSI_OPCODE_LIT
:
616 nvfx_vp_emit(vpc
, arith(sat
, SCA
, LIT
, dst
, mask
, none
, none
, src
[0]));
618 case TGSI_OPCODE_LOG
:
619 nvfx_vp_emit(vpc
, arith(sat
, SCA
, LOG
, dst
, mask
, none
, none
, src
[0]));
621 case TGSI_OPCODE_LRP
:
622 tmp
= nvfx_src(temp(vpc
));
623 nvfx_vp_emit(vpc
, arith(0, VEC
, MAD
, tmp
.reg
, mask
, neg(src
[0]), src
[2], src
[2]));
624 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MAD
, dst
, mask
, src
[0], src
[1], tmp
));
626 case TGSI_OPCODE_MAD
:
627 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MAD
, dst
, mask
, src
[0], src
[1], src
[2]));
629 case TGSI_OPCODE_MAX
:
630 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MAX
, dst
, mask
, src
[0], src
[1], none
));
632 case TGSI_OPCODE_MIN
:
633 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MIN
, dst
, mask
, src
[0], src
[1], none
));
635 case TGSI_OPCODE_MOV
:
636 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MOV
, dst
, mask
, src
[0], none
, none
));
638 case TGSI_OPCODE_MUL
:
639 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MUL
, dst
, mask
, src
[0], src
[1], none
));
641 case TGSI_OPCODE_NOP
:
643 case TGSI_OPCODE_POW
:
644 tmp
= nvfx_src(temp(vpc
));
645 nvfx_vp_emit(vpc
, arith(0, SCA
, LG2
, tmp
.reg
, NVFX_VP_MASK_X
, none
, none
, swz(src
[0], X
, X
, X
, X
)));
646 nvfx_vp_emit(vpc
, arith(0, VEC
, MUL
, tmp
.reg
, NVFX_VP_MASK_X
, swz(tmp
, X
, X
, X
, X
), swz(src
[1], X
, X
, X
, X
), none
));
647 nvfx_vp_emit(vpc
, arith(sat
, SCA
, EX2
, dst
, mask
, none
, none
, swz(tmp
, X
, X
, X
, X
)));
649 case TGSI_OPCODE_RCP
:
650 nvfx_vp_emit(vpc
, arith(sat
, SCA
, RCP
, dst
, mask
, none
, none
, src
[0]));
652 case TGSI_OPCODE_RSQ
:
653 nvfx_vp_emit(vpc
, arith(sat
, SCA
, RSQ
, dst
, mask
, none
, none
, abs(src
[0])));
655 case TGSI_OPCODE_SEQ
:
656 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SEQ
, dst
, mask
, src
[0], src
[1], none
));
658 case TGSI_OPCODE_SFL
:
659 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SFL
, dst
, mask
, src
[0], src
[1], none
));
661 case TGSI_OPCODE_SGE
:
662 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SGE
, dst
, mask
, src
[0], src
[1], none
));
664 case TGSI_OPCODE_SGT
:
665 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SGT
, dst
, mask
, src
[0], src
[1], none
));
667 case TGSI_OPCODE_SIN
:
668 nvfx_vp_emit(vpc
, arith(sat
, SCA
, SIN
, dst
, mask
, none
, none
, src
[0]));
670 case TGSI_OPCODE_SLE
:
671 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SLE
, dst
, mask
, src
[0], src
[1], none
));
673 case TGSI_OPCODE_SLT
:
674 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SLT
, dst
, mask
, src
[0], src
[1], none
));
676 case TGSI_OPCODE_SNE
:
677 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SNE
, dst
, mask
, src
[0], src
[1], none
));
679 case TGSI_OPCODE_SSG
:
680 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SSG
, dst
, mask
, src
[0], none
, none
));
682 case TGSI_OPCODE_STR
:
683 nvfx_vp_emit(vpc
, arith(sat
, VEC
, STR
, dst
, mask
, src
[0], src
[1], none
));
685 case TGSI_OPCODE_SUB
:
686 nvfx_vp_emit(vpc
, arith(sat
, VEC
, ADD
, dst
, mask
, src
[0], none
, neg(src
[1])));
688 case TGSI_OPCODE_TRUNC
:
689 tmp
= nvfx_src(temp(vpc
));
690 insn
= arith(0, VEC
, MOV
, none
.reg
, mask
, src
[0], none
, none
);
692 nvfx_vp_emit(vpc
, insn
);
694 nvfx_vp_emit(vpc
, arith(0, VEC
, FLR
, tmp
.reg
, mask
, abs(src
[0]), none
, none
));
695 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MOV
, dst
, mask
, tmp
, none
, none
));
697 insn
= arith(sat
, VEC
, MOV
, dst
, mask
, neg(tmp
), none
, none
);
698 insn
.cc_test
= NVFX_COND_LT
;
699 nvfx_vp_emit(vpc
, insn
);
701 case TGSI_OPCODE_XPD
:
702 tmp
= nvfx_src(temp(vpc
));
703 nvfx_vp_emit(vpc
, arith(0, VEC
, MUL
, tmp
.reg
, mask
, swz(src
[0], Z
, X
, Y
, Y
), swz(src
[1], Y
, Z
, X
, X
), none
));
704 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MAD
, dst
, (mask
& ~NVFX_VP_MASK_W
), swz(src
[0], Y
, Z
, X
, X
), swz(src
[1], Z
, X
, Y
, Y
), neg(tmp
)));
707 insn
= arith(0, VEC
, MOV
, none
.reg
, NVFX_VP_MASK_X
, src
[0], none
, none
);
709 nvfx_vp_emit(vpc
, insn
);
711 reloc
.location
= vpc
->vp
->nr_insns
;
712 reloc
.target
= finst
->Label
.Label
+ 1;
713 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
715 insn
= arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
);
716 insn
.cc_test
= NVFX_COND_EQ
;
717 insn
.cc_swz
[0] = insn
.cc_swz
[1] = insn
.cc_swz
[2] = insn
.cc_swz
[3] = 0;
718 nvfx_vp_emit(vpc
, insn
);
720 case TGSI_OPCODE_ELSE
:
721 case TGSI_OPCODE_BRA
:
722 case TGSI_OPCODE_CAL
:
723 reloc
.location
= vpc
->vp
->nr_insns
;
724 reloc
.target
= finst
->Label
.Label
;
725 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
727 if(finst
->Instruction
.Opcode
== TGSI_OPCODE_CAL
)
728 insn
= arith(0, SCA
, CAL
, none
.reg
, 0, none
, none
, none
);
730 insn
= arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
);
731 nvfx_vp_emit(vpc
, insn
);
733 case TGSI_OPCODE_RET
:
734 if(sub_depth
|| !vpc
->vp
->enabled_ucps
) {
736 tmp
.swz
[0] = tmp
.swz
[1] = tmp
.swz
[2] = tmp
.swz
[3] = 0;
737 nvfx_vp_emit(vpc
, arith(0, SCA
, RET
, none
.reg
, 0, none
, none
, tmp
));
739 reloc
.location
= vpc
->vp
->nr_insns
;
740 reloc
.target
= vpc
->info
->num_instructions
;
741 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
742 nvfx_vp_emit(vpc
, arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
745 case TGSI_OPCODE_BGNSUB
:
748 case TGSI_OPCODE_ENDSUB
:
751 case TGSI_OPCODE_ENDIF
:
752 /* nothing to do here */
754 case TGSI_OPCODE_BGNLOOP
:
755 loop
.cont_target
= idx
;
756 loop
.brk_target
= finst
->Label
.Label
+ 1;
757 util_dynarray_append(&vpc
->loop_stack
, struct nvfx_loop_entry
, loop
);
759 case TGSI_OPCODE_ENDLOOP
:
760 loop
= util_dynarray_pop(&vpc
->loop_stack
, struct nvfx_loop_entry
);
762 reloc
.location
= vpc
->vp
->nr_insns
;
763 reloc
.target
= loop
.cont_target
;
764 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
766 nvfx_vp_emit(vpc
, arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
768 case TGSI_OPCODE_CONT
:
769 loop
= util_dynarray_top(&vpc
->loop_stack
, struct nvfx_loop_entry
);
771 reloc
.location
= vpc
->vp
->nr_insns
;
772 reloc
.target
= loop
.cont_target
;
773 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
775 nvfx_vp_emit(vpc
, arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
777 case TGSI_OPCODE_BRK
:
778 loop
= util_dynarray_top(&vpc
->loop_stack
, struct nvfx_loop_entry
);
780 reloc
.location
= vpc
->vp
->nr_insns
;
781 reloc
.target
= loop
.brk_target
;
782 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
784 nvfx_vp_emit(vpc
, arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
786 case TGSI_OPCODE_END
:
788 if(vpc
->vp
->enabled_ucps
) {
789 if(idx
!= (vpc
->info
->num_instructions
- 1)) {
790 reloc
.location
= vpc
->vp
->nr_insns
;
791 reloc
.target
= vpc
->info
->num_instructions
;
792 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
793 nvfx_vp_emit(vpc
, arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
796 if(vpc
->vp
->nr_insns
)
797 vpc
->vp
->insns
[vpc
->vp
->nr_insns
- 1].data
[3] |= NVFX_VP_INST_LAST
;
798 nvfx_vp_emit(vpc
, arith(0, VEC
, NOP
, none
.reg
, 0, none
, none
, none
));
799 vpc
->vp
->insns
[vpc
->vp
->nr_insns
- 1].data
[3] |= NVFX_VP_INST_LAST
;
803 NOUVEAU_ERR("invalid opcode %d\n", finst
->Instruction
.Opcode
);
807 if(finst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
&& !vpc
->is_nv4x
) {
808 if (!vpc
->r_0_1
.type
)
809 vpc
->r_0_1
= constant(vpc
, -1, 0, 1, 0, 0);
810 nvfx_vp_emit(vpc
, arith(0, VEC
, MAX
, dst
, mask
, nvfx_src(dst
), swz(nvfx_src(vpc
->r_0_1
), X
, X
, X
, X
), none
));
811 nvfx_vp_emit(vpc
, arith(0, VEC
, MIN
, final_dst
, mask
, nvfx_src(dst
), swz(nvfx_src(vpc
->r_0_1
), Y
, Y
, Y
, Y
), none
));
819 nvfx_vertprog_parse_decl_output(struct nvfx_vpc
*vpc
,
820 const struct tgsi_full_declaration
*fdec
)
822 unsigned num_texcoords
= vpc
->is_nv4x
? 10 : 8;
823 unsigned idx
= fdec
->Range
.First
;
824 unsigned semantic_index
= fdec
->Semantic
.Index
;
827 switch (fdec
->Semantic
.Name
) {
828 case TGSI_SEMANTIC_POSITION
:
829 hw
= NVFX_VP(INST_DEST_POS
);
832 case TGSI_SEMANTIC_CLIPVERTEX
:
833 vpc
->r_result
[idx
] = temp(vpc
);
834 vpc
->r_temps_discard
= 0;
837 case TGSI_SEMANTIC_COLOR
:
838 if (fdec
->Semantic
.Index
== 0) {
839 hw
= NVFX_VP(INST_DEST_COL0
);
841 if (fdec
->Semantic
.Index
== 1) {
842 hw
= NVFX_VP(INST_DEST_COL1
);
844 NOUVEAU_ERR("bad colour semantic index\n");
848 case TGSI_SEMANTIC_BCOLOR
:
849 if (fdec
->Semantic
.Index
== 0) {
850 hw
= NVFX_VP(INST_DEST_BFC0
);
852 if (fdec
->Semantic
.Index
== 1) {
853 hw
= NVFX_VP(INST_DEST_BFC1
);
855 NOUVEAU_ERR("bad bcolour semantic index\n");
859 case TGSI_SEMANTIC_FOG
:
860 hw
= NVFX_VP(INST_DEST_FOGC
);
862 case TGSI_SEMANTIC_PSIZE
:
863 hw
= NVFX_VP(INST_DEST_PSZ
);
865 case TGSI_SEMANTIC_GENERIC
:
866 /* this is really an identifier for VP/FP linkage */
869 case TGSI_SEMANTIC_TEXCOORD
:
870 for (i
= 0; i
< num_texcoords
; i
++) {
871 if (vpc
->vp
->texcoord
[i
] == semantic_index
) {
872 hw
= NVFX_VP(INST_DEST_TC(i
));
877 if (i
== num_texcoords
) {
878 vpc
->r_result
[idx
] = nvfx_reg(NVFXSR_NONE
, 0);
882 case TGSI_SEMANTIC_EDGEFLAG
:
883 /* not really an error just a fallback */
884 NOUVEAU_ERR("cannot handle edgeflag output\n");
887 NOUVEAU_ERR("bad output semantic\n");
891 vpc
->r_result
[idx
] = nvfx_reg(NVFXSR_OUTPUT
, hw
);
896 nvfx_vertprog_prepare(struct nvfx_vpc
*vpc
)
898 struct tgsi_parse_context p
;
899 int high_const
= -1, high_temp
= -1, high_addr
= -1, nr_imm
= 0, i
;
901 tgsi_parse_init(&p
, vpc
->pipe
.tokens
);
902 while (!tgsi_parse_end_of_tokens(&p
)) {
903 const union tgsi_full_token
*tok
= &p
.FullToken
;
905 tgsi_parse_token(&p
);
906 switch(tok
->Token
.Type
) {
907 case TGSI_TOKEN_TYPE_IMMEDIATE
:
910 case TGSI_TOKEN_TYPE_DECLARATION
:
912 const struct tgsi_full_declaration
*fdec
;
914 fdec
= &p
.FullToken
.FullDeclaration
;
915 switch (fdec
->Declaration
.File
) {
916 case TGSI_FILE_TEMPORARY
:
917 if (fdec
->Range
.Last
> high_temp
) {
922 case TGSI_FILE_ADDRESS
:
923 if (fdec
->Range
.Last
> high_addr
) {
928 case TGSI_FILE_CONSTANT
:
929 if (fdec
->Range
.Last
> high_const
) {
934 case TGSI_FILE_OUTPUT
:
935 if (!nvfx_vertprog_parse_decl_output(vpc
, fdec
))
950 vpc
->imm
= CALLOC(nr_imm
, sizeof(struct nvfx_reg
));
955 vpc
->r_temp
= CALLOC(high_temp
, sizeof(struct nvfx_reg
));
956 for (i
= 0; i
< high_temp
; i
++)
957 vpc
->r_temp
[i
] = temp(vpc
);
961 vpc
->r_address
= CALLOC(high_addr
, sizeof(struct nvfx_reg
));
962 for (i
= 0; i
< high_addr
; i
++)
963 vpc
->r_address
[i
] = nvfx_reg(NVFXSR_TEMP
, i
);
967 vpc
->r_const
= CALLOC(high_const
, sizeof(struct nvfx_reg
));
968 for (i
= 0; i
< high_const
; i
++)
969 vpc
->r_const
[i
] = constant(vpc
, i
, 0, 0, 0, 0);
972 vpc
->r_temps_discard
= 0;
976 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp
, "NVFX_DUMP_VP", FALSE
)
979 _nvfx_vertprog_translate(uint16_t oclass
, struct nv30_vertprog
*vp
)
981 struct tgsi_parse_context parse
;
982 struct nvfx_vpc
*vpc
= NULL
;
983 struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
984 struct util_dynarray insns
;
987 vp
->translated
= FALSE
;
991 vpc
= CALLOC_STRUCT(nvfx_vpc
);
994 vpc
->is_nv4x
= (oclass
>= NV40_3D_CLASS
) ? ~0 : 0;
996 vpc
->pipe
= vp
->pipe
;
997 vpc
->info
= &vp
->info
;
1000 if (!nvfx_vertprog_prepare(vpc
)) {
1005 /* Redirect post-transform vertex position to a temp if user clip
1006 * planes are enabled. We need to append code to the vtxprog
1007 * to handle clip planes later.
1009 if (vp
->enabled_ucps
&& vpc
->cvtx_idx
< 0) {
1010 vpc
->r_result
[vpc
->hpos_idx
] = temp(vpc
);
1011 vpc
->r_temps_discard
= 0;
1012 vpc
->cvtx_idx
= vpc
->hpos_idx
;
1015 util_dynarray_init(&insns
);
1017 tgsi_parse_init(&parse
, vp
->pipe
.tokens
);
1018 while (!tgsi_parse_end_of_tokens(&parse
)) {
1019 tgsi_parse_token(&parse
);
1021 switch (parse
.FullToken
.Token
.Type
) {
1022 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1024 const struct tgsi_full_immediate
*imm
;
1026 imm
= &parse
.FullToken
.FullImmediate
;
1027 assert(imm
->Immediate
.DataType
== TGSI_IMM_FLOAT32
);
1028 assert(imm
->Immediate
.NrTokens
== 4 + 1);
1029 vpc
->imm
[vpc
->nr_imm
++] =
1037 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1039 const struct tgsi_full_instruction
*finst
;
1040 unsigned idx
= insns
.size
>> 2;
1041 util_dynarray_append(&insns
, unsigned, vp
->nr_insns
);
1042 finst
= &parse
.FullToken
.FullInstruction
;
1043 if (!nvfx_vertprog_parse_instruction(vpc
, idx
, finst
))
1052 util_dynarray_append(&insns
, unsigned, vp
->nr_insns
);
1054 for(unsigned i
= 0; i
< vpc
->label_relocs
.size
; i
+= sizeof(struct nvfx_relocation
))
1056 struct nvfx_relocation
* label_reloc
= (struct nvfx_relocation
*)((char*)vpc
->label_relocs
.data
+ i
);
1057 struct nvfx_relocation hw_reloc
;
1059 hw_reloc
.location
= label_reloc
->location
;
1060 hw_reloc
.target
= ((unsigned*)insns
.data
)[label_reloc
->target
];
1062 //debug_printf("hw %u -> tgsi %u = hw %u\n", hw_reloc.location, label_reloc->target, hw_reloc.target);
1064 util_dynarray_append(&vp
->branch_relocs
, struct nvfx_relocation
, hw_reloc
);
1066 util_dynarray_fini(&insns
);
1067 util_dynarray_trim(&vp
->branch_relocs
);
1069 /* XXX: what if we add a RET before?! make sure we jump here...*/
1071 /* Write out HPOS if it was redirected to a temp earlier */
1072 if (vpc
->r_result
[vpc
->hpos_idx
].type
!= NVFXSR_OUTPUT
) {
1073 struct nvfx_reg hpos
= nvfx_reg(NVFXSR_OUTPUT
,
1074 NVFX_VP(INST_DEST_POS
));
1075 struct nvfx_src htmp
= nvfx_src(vpc
->r_result
[vpc
->hpos_idx
]);
1077 nvfx_vp_emit(vpc
, arith(0, VEC
, MOV
, hpos
, NVFX_VP_MASK_ALL
, htmp
, none
, none
));
1080 /* Insert code to handle user clip planes */
1081 ucps
= vp
->enabled_ucps
;
1083 int i
= ffs(ucps
) - 1; ucps
&= ~(1 << i
);
1084 struct nvfx_reg cdst
= nvfx_reg(NVFXSR_OUTPUT
, NV30_VP_INST_DEST_CLP(i
));
1085 struct nvfx_src ceqn
= nvfx_src(nvfx_reg(NVFXSR_CONST
, 512 + i
));
1086 struct nvfx_src htmp
= nvfx_src(vpc
->r_result
[vpc
->cvtx_idx
]);
1092 case 0: case 3: mask
= NVFX_VP_MASK_Y
; break;
1093 case 1: case 4: mask
= NVFX_VP_MASK_Z
; break;
1094 case 2: case 5: mask
= NVFX_VP_MASK_W
; break;
1096 NOUVEAU_ERR("invalid clip dist #%d\n", i
);
1101 mask
= NVFX_VP_MASK_X
;
1103 nvfx_vp_emit(vpc
, arith(0, VEC
, DP4
, cdst
, mask
, htmp
, ceqn
, none
));
1106 if (vpc
->vp
->nr_insns
)
1107 vpc
->vp
->insns
[vpc
->vp
->nr_insns
- 1].data
[3] |= NVFX_VP_INST_LAST
;
1109 if(debug_get_option_nvfx_dump_vp())
1112 tgsi_dump(vpc
->pipe
.tokens
, 0);
1114 debug_printf("\n%s vertex program:\n", vpc
->is_nv4x
? "nv4x" : "nv3x");
1115 for (i
= 0; i
< vp
->nr_insns
; i
++)
1116 debug_printf("%3u: %08x %08x %08x %08x\n", i
, vp
->insns
[i
].data
[0], vp
->insns
[i
].data
[1], vp
->insns
[i
].data
[2], vp
->insns
[i
].data
[3]);
1120 vp
->translated
= TRUE
;
1123 tgsi_parse_free(&parse
);
1125 util_dynarray_fini(&vpc
->label_relocs
);
1126 util_dynarray_fini(&vpc
->loop_stack
);
1128 FREE(vpc
->r_address
);
1134 return vp
->translated
;