1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_dynarray.h"
5 #include "util/u_debug.h"
7 #include "pipe/p_shader_tokens.h"
8 #include "tgsi/tgsi_parse.h"
9 #include "tgsi/tgsi_dump.h"
10 #include "tgsi/tgsi_util.h"
11 #include "tgsi/tgsi_ureg.h"
13 #include "draw/draw_context.h"
15 #include "nv_object.xml.h"
16 #include "nouveau_debug.h"
17 #include "nv30/nv30-40_3d.xml.h"
18 #include "nv30/nv30_state.h"
20 /* TODO (at least...):
21 * 1. Indexed consts + ARL
22 * 3. NV_vp11, NV_vp2, NV_vp3 features
23 * - extra arith opcodes
31 #include "nv30/nv30_vertprog.h"
32 #include "nv30/nv40_vertprog.h"
34 struct nvfx_loop_entry
{
40 struct pipe_shader_state pipe
;
41 struct nv30_vertprog
*vp
;
42 struct tgsi_shader_info
* info
;
44 struct nv30_vertprog_exec
*vpi
;
47 unsigned r_temps_discard
;
48 struct nvfx_reg r_result
[PIPE_MAX_SHADER_OUTPUTS
];
49 struct nvfx_reg
*r_address
;
50 struct nvfx_reg
*r_temp
;
51 struct nvfx_reg
*r_const
;
52 struct nvfx_reg r_0_1
;
62 struct util_dynarray label_relocs
;
63 struct util_dynarray loop_stack
;
66 static struct nvfx_reg
67 temp(struct nvfx_vpc
*vpc
)
69 int idx
= ffs(~vpc
->r_temps
) - 1;
72 NOUVEAU_ERR("out of temps!!\n");
74 return nvfx_reg(NVFXSR_TEMP
, 0);
77 vpc
->r_temps
|= (1 << idx
);
78 vpc
->r_temps_discard
|= (1 << idx
);
79 return nvfx_reg(NVFXSR_TEMP
, idx
);
83 release_temps(struct nvfx_vpc
*vpc
)
85 vpc
->r_temps
&= ~vpc
->r_temps_discard
;
86 vpc
->r_temps_discard
= 0;
89 static struct nvfx_reg
90 constant(struct nvfx_vpc
*vpc
, int pipe
, float x
, float y
, float z
, float w
)
92 struct nv30_vertprog
*vp
= vpc
->vp
;
93 struct nv30_vertprog_data
*vpd
;
97 for (idx
= 0; idx
< vp
->nr_consts
; idx
++) {
98 if (vp
->consts
[idx
].index
== pipe
)
99 return nvfx_reg(NVFXSR_CONST
, idx
);
103 idx
= vp
->nr_consts
++;
104 vp
->consts
= realloc(vp
->consts
, sizeof(*vpd
) * vp
->nr_consts
);
105 vpd
= &vp
->consts
[idx
];
112 return nvfx_reg(NVFXSR_CONST
, idx
);
115 #define arith(s,t,o,d,m,s0,s1,s2) \
116 nvfx_insn((s), (NVFX_VP_INST_SLOT_##t << 7) | NVFX_VP_INST_##t##_OP_##o, -1, (d), (m), (s0), (s1), (s2))
119 emit_src(struct nvfx_vpc
*vpc
, uint32_t *hw
,
120 int pos
, struct nvfx_src src
)
122 struct nv30_vertprog
*vp
= vpc
->vp
;
124 struct nvfx_relocation reloc
;
126 switch (src
.reg
.type
) {
128 sr
|= (NVFX_VP(SRC_REG_TYPE_TEMP
) << NVFX_VP(SRC_REG_TYPE_SHIFT
));
129 sr
|= (src
.reg
.index
<< NVFX_VP(SRC_TEMP_SRC_SHIFT
));
132 sr
|= (NVFX_VP(SRC_REG_TYPE_INPUT
) <<
133 NVFX_VP(SRC_REG_TYPE_SHIFT
));
134 vp
->ir
|= (1 << src
.reg
.index
);
135 hw
[1] |= (src
.reg
.index
<< NVFX_VP(INST_INPUT_SRC_SHIFT
));
138 sr
|= (NVFX_VP(SRC_REG_TYPE_CONST
) <<
139 NVFX_VP(SRC_REG_TYPE_SHIFT
));
140 if (src
.reg
.index
< 256 && src
.reg
.index
>= -256) {
141 reloc
.location
= vp
->nr_insns
- 1;
142 reloc
.target
= src
.reg
.index
;
143 util_dynarray_append(&vp
->const_relocs
, struct nvfx_relocation
, reloc
);
145 hw
[1] |= (src
.reg
.index
<< NVFX_VP(INST_CONST_SRC_SHIFT
)) &
146 NVFX_VP(INST_CONST_SRC_MASK
);
150 sr
|= (NVFX_VP(SRC_REG_TYPE_INPUT
) <<
151 NVFX_VP(SRC_REG_TYPE_SHIFT
));
158 sr
|= NVFX_VP(SRC_NEGATE
);
161 hw
[0] |= (1 << (21 + pos
));
163 sr
|= ((src
.swz
[0] << NVFX_VP(SRC_SWZ_X_SHIFT
)) |
164 (src
.swz
[1] << NVFX_VP(SRC_SWZ_Y_SHIFT
)) |
165 (src
.swz
[2] << NVFX_VP(SRC_SWZ_Z_SHIFT
)) |
166 (src
.swz
[3] << NVFX_VP(SRC_SWZ_W_SHIFT
)));
169 if(src
.reg
.type
== NVFXSR_CONST
)
170 hw
[3] |= NVFX_VP(INST_INDEX_CONST
);
171 else if(src
.reg
.type
== NVFXSR_INPUT
)
172 hw
[0] |= NVFX_VP(INST_INDEX_INPUT
);
177 hw
[0] |= NVFX_VP(INST_ADDR_REG_SELECT_1
);
178 hw
[0] |= src
.indirect_swz
<< NVFX_VP(INST_ADDR_SWZ_SHIFT
);
183 hw
[1] |= ((sr
& NVFX_VP(SRC0_HIGH_MASK
)) >>
184 NVFX_VP(SRC0_HIGH_SHIFT
)) << NVFX_VP(INST_SRC0H_SHIFT
);
185 hw
[2] |= (sr
& NVFX_VP(SRC0_LOW_MASK
)) <<
186 NVFX_VP(INST_SRC0L_SHIFT
);
189 hw
[2] |= sr
<< NVFX_VP(INST_SRC1_SHIFT
);
192 hw
[2] |= ((sr
& NVFX_VP(SRC2_HIGH_MASK
)) >>
193 NVFX_VP(SRC2_HIGH_SHIFT
)) << NVFX_VP(INST_SRC2H_SHIFT
);
194 hw
[3] |= (sr
& NVFX_VP(SRC2_LOW_MASK
)) <<
195 NVFX_VP(INST_SRC2L_SHIFT
);
203 emit_dst(struct nvfx_vpc
*vpc
, uint32_t *hw
,
204 int slot
, struct nvfx_reg dst
)
206 struct nv30_vertprog
*vp
= vpc
->vp
;
211 hw
[0] |= NV30_VP_INST_DEST_TEMP_ID_MASK
;
213 hw
[3] |= NV40_VP_INST_DEST_MASK
;
215 hw
[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK
;
217 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
222 hw
[0] |= (dst
.index
<< NV30_VP_INST_DEST_TEMP_ID_SHIFT
);
224 hw
[3] |= NV40_VP_INST_DEST_MASK
;
226 hw
[0] |= (dst
.index
<< NV40_VP_INST_VEC_DEST_TEMP_SHIFT
);
228 hw
[3] |= (dst
.index
<< NV40_VP_INST_SCA_DEST_TEMP_SHIFT
);
232 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
235 case NV30_VP_INST_DEST_CLP(0):
236 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
239 case NV30_VP_INST_DEST_CLP(1):
240 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
243 case NV30_VP_INST_DEST_CLP(2):
244 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
247 case NV30_VP_INST_DEST_CLP(3):
248 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
251 case NV30_VP_INST_DEST_CLP(4):
252 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
255 case NV30_VP_INST_DEST_CLP(5):
256 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
259 case NV40_VP_INST_DEST_COL0
: vp
->or |= (1 << 0); break;
260 case NV40_VP_INST_DEST_COL1
: vp
->or |= (1 << 1); break;
261 case NV40_VP_INST_DEST_BFC0
: vp
->or |= (1 << 2); break;
262 case NV40_VP_INST_DEST_BFC1
: vp
->or |= (1 << 3); break;
263 case NV40_VP_INST_DEST_FOGC
: vp
->or |= (1 << 4); break;
264 case NV40_VP_INST_DEST_PSZ
: vp
->or |= (1 << 5); break;
269 hw
[3] |= (dst
.index
<< NV30_VP_INST_DEST_SHIFT
);
270 hw
[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK
;
272 /*XXX: no way this is entirely correct, someone needs to
273 * figure out what exactly it is.
277 hw
[3] |= (dst
.index
<< NV40_VP_INST_DEST_SHIFT
);
279 hw
[0] |= NV40_VP_INST_VEC_RESULT
;
280 hw
[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK
;
282 hw
[3] |= NV40_VP_INST_SCA_RESULT
;
283 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
293 nvfx_vp_emit(struct nvfx_vpc
*vpc
, struct nvfx_insn insn
)
295 struct nv30_vertprog
*vp
= vpc
->vp
;
296 unsigned slot
= insn
.op
>> 7;
297 unsigned op
= insn
.op
& 0x7f;
300 vp
->insns
= realloc(vp
->insns
, ++vp
->nr_insns
* sizeof(*vpc
->vpi
));
301 vpc
->vpi
= &vp
->insns
[vp
->nr_insns
- 1];
302 memset(vpc
->vpi
, 0, sizeof(*vpc
->vpi
));
306 if (insn
.cc_test
!= NVFX_COND_TR
)
307 hw
[0] |= NVFX_VP(INST_COND_TEST_ENABLE
);
308 hw
[0] |= (insn
.cc_test
<< NVFX_VP(INST_COND_SHIFT
));
309 hw
[0] |= ((insn
.cc_swz
[0] << NVFX_VP(INST_COND_SWZ_X_SHIFT
)) |
310 (insn
.cc_swz
[1] << NVFX_VP(INST_COND_SWZ_Y_SHIFT
)) |
311 (insn
.cc_swz
[2] << NVFX_VP(INST_COND_SWZ_Z_SHIFT
)) |
312 (insn
.cc_swz
[3] << NVFX_VP(INST_COND_SWZ_W_SHIFT
)));
314 hw
[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE
);
317 assert(vpc
->is_nv4x
);
319 hw
[0] |= NV40_VP_INST_SATURATE
;
324 hw
[1] |= (op
<< NV30_VP_INST_VEC_OPCODE_SHIFT
);
326 hw
[0] |= ((op
>> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT
);
327 hw
[1] |= ((op
& 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT
);
329 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
330 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
332 if (insn
.dst
.type
== NVFXSR_OUTPUT
) {
334 hw
[3] |= (insn
.mask
<< NV30_VP_INST_SDEST_WRITEMASK_SHIFT
);
336 hw
[3] |= (insn
.mask
<< NV30_VP_INST_VDEST_WRITEMASK_SHIFT
);
339 hw
[3] |= (insn
.mask
<< NV30_VP_INST_STEMP_WRITEMASK_SHIFT
);
341 hw
[3] |= (insn
.mask
<< NV30_VP_INST_VTEMP_WRITEMASK_SHIFT
);
345 hw
[1] |= (op
<< NV40_VP_INST_VEC_OPCODE_SHIFT
);
346 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
347 hw
[3] |= (insn
.mask
<< NV40_VP_INST_VEC_WRITEMASK_SHIFT
);
349 hw
[1] |= (op
<< NV40_VP_INST_SCA_OPCODE_SHIFT
);
350 hw
[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK
;
351 hw
[3] |= (insn
.mask
<< NV40_VP_INST_SCA_WRITEMASK_SHIFT
);
355 emit_dst(vpc
, hw
, slot
, insn
.dst
);
356 emit_src(vpc
, hw
, 0, insn
.src
[0]);
357 emit_src(vpc
, hw
, 1, insn
.src
[1]);
358 emit_src(vpc
, hw
, 2, insn
.src
[2]);
360 // if(insn.src[0].indirect || op == NVFX_VP_INST_VEC_OP_ARL)
361 // hw[3] |= NV40_VP_INST_SCA_RESULT;
364 static inline struct nvfx_src
365 tgsi_src(struct nvfx_vpc
*vpc
, const struct tgsi_full_src_register
*fsrc
) {
368 switch (fsrc
->Register
.File
) {
369 case TGSI_FILE_INPUT
:
370 src
.reg
= nvfx_reg(NVFXSR_INPUT
, fsrc
->Register
.Index
);
372 case TGSI_FILE_CONSTANT
:
373 if(fsrc
->Register
.Indirect
) {
374 src
.reg
= vpc
->r_const
[0];
375 src
.reg
.index
= fsrc
->Register
.Index
;
377 src
.reg
= vpc
->r_const
[fsrc
->Register
.Index
];
380 case TGSI_FILE_IMMEDIATE
:
381 src
.reg
= vpc
->imm
[fsrc
->Register
.Index
];
383 case TGSI_FILE_TEMPORARY
:
384 src
.reg
= vpc
->r_temp
[fsrc
->Register
.Index
];
387 NOUVEAU_ERR("bad src file\n");
393 src
.abs
= fsrc
->Register
.Absolute
;
394 src
.negate
= fsrc
->Register
.Negate
;
395 src
.swz
[0] = fsrc
->Register
.SwizzleX
;
396 src
.swz
[1] = fsrc
->Register
.SwizzleY
;
397 src
.swz
[2] = fsrc
->Register
.SwizzleZ
;
398 src
.swz
[3] = fsrc
->Register
.SwizzleW
;
400 src
.indirect_reg
= 0;
401 src
.indirect_swz
= 0;
403 if(fsrc
->Register
.Indirect
) {
404 if(fsrc
->Indirect
.File
== TGSI_FILE_ADDRESS
&&
405 (fsrc
->Register
.File
== TGSI_FILE_CONSTANT
||
406 fsrc
->Register
.File
== TGSI_FILE_INPUT
)) {
408 src
.indirect_reg
= fsrc
->Indirect
.Index
;
409 src
.indirect_swz
= fsrc
->Indirect
.Swizzle
;
419 static INLINE
struct nvfx_reg
420 tgsi_dst(struct nvfx_vpc
*vpc
, const struct tgsi_full_dst_register
*fdst
) {
423 switch (fdst
->Register
.File
) {
425 dst
= nvfx_reg(NVFXSR_NONE
, 0);
427 case TGSI_FILE_OUTPUT
:
428 dst
= vpc
->r_result
[fdst
->Register
.Index
];
430 case TGSI_FILE_TEMPORARY
:
431 dst
= vpc
->r_temp
[fdst
->Register
.Index
];
433 case TGSI_FILE_ADDRESS
:
434 dst
= vpc
->r_address
[fdst
->Register
.Index
];
437 NOUVEAU_ERR("bad dst file %i\n", fdst
->Register
.File
);
451 if (tgsi
& TGSI_WRITEMASK_X
) mask
|= NVFX_VP_MASK_X
;
452 if (tgsi
& TGSI_WRITEMASK_Y
) mask
|= NVFX_VP_MASK_Y
;
453 if (tgsi
& TGSI_WRITEMASK_Z
) mask
|= NVFX_VP_MASK_Z
;
454 if (tgsi
& TGSI_WRITEMASK_W
) mask
|= NVFX_VP_MASK_W
;
459 nvfx_vertprog_parse_instruction(struct nvfx_vpc
*vpc
,
460 unsigned idx
, const struct tgsi_full_instruction
*finst
)
462 struct nvfx_src src
[3], tmp
;
464 struct nvfx_reg final_dst
;
465 struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
466 struct nvfx_insn insn
;
467 struct nvfx_relocation reloc
;
468 struct nvfx_loop_entry loop
;
471 int ai
= -1, ci
= -1, ii
= -1;
473 unsigned sub_depth
= 0;
475 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
476 const struct tgsi_full_src_register
*fsrc
;
478 fsrc
= &finst
->Src
[i
];
479 if (fsrc
->Register
.File
== TGSI_FILE_TEMPORARY
) {
480 src
[i
] = tgsi_src(vpc
, fsrc
);
484 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
485 const struct tgsi_full_src_register
*fsrc
;
487 fsrc
= &finst
->Src
[i
];
489 switch (fsrc
->Register
.File
) {
490 case TGSI_FILE_INPUT
:
491 if (ai
== -1 || ai
== fsrc
->Register
.Index
) {
492 ai
= fsrc
->Register
.Index
;
493 src
[i
] = tgsi_src(vpc
, fsrc
);
495 src
[i
] = nvfx_src(temp(vpc
));
496 nvfx_vp_emit(vpc
, arith(0, VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
,
497 tgsi_src(vpc
, fsrc
), none
, none
));
500 case TGSI_FILE_CONSTANT
:
501 if ((ci
== -1 && ii
== -1) ||
502 ci
== fsrc
->Register
.Index
) {
503 ci
= fsrc
->Register
.Index
;
504 src
[i
] = tgsi_src(vpc
, fsrc
);
506 src
[i
] = nvfx_src(temp(vpc
));
507 nvfx_vp_emit(vpc
, arith(0, VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
,
508 tgsi_src(vpc
, fsrc
), none
, none
));
511 case TGSI_FILE_IMMEDIATE
:
512 if ((ci
== -1 && ii
== -1) ||
513 ii
== fsrc
->Register
.Index
) {
514 ii
= fsrc
->Register
.Index
;
515 src
[i
] = tgsi_src(vpc
, fsrc
);
517 src
[i
] = nvfx_src(temp(vpc
));
518 nvfx_vp_emit(vpc
, arith(0, VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
,
519 tgsi_src(vpc
, fsrc
), none
, none
));
522 case TGSI_FILE_TEMPORARY
:
526 NOUVEAU_ERR("bad src file\n");
531 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
532 if(src
[i
].reg
.type
< 0)
536 if(finst
->Dst
[0].Register
.File
== TGSI_FILE_ADDRESS
&&
537 finst
->Instruction
.Opcode
!= TGSI_OPCODE_ARL
)
540 final_dst
= dst
= tgsi_dst(vpc
, &finst
->Dst
[0]);
541 mask
= tgsi_mask(finst
->Dst
[0].Register
.WriteMask
);
542 if(finst
->Instruction
.Saturate
) {
543 assert(finst
->Instruction
.Opcode
!= TGSI_OPCODE_ARL
);
547 if(dst
.type
!= NVFXSR_TEMP
)
551 switch (finst
->Instruction
.Opcode
) {
552 case TGSI_OPCODE_ABS
:
553 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MOV
, dst
, mask
, abs(src
[0]), none
, none
));
555 case TGSI_OPCODE_ADD
:
556 nvfx_vp_emit(vpc
, arith(sat
, VEC
, ADD
, dst
, mask
, src
[0], none
, src
[1]));
558 case TGSI_OPCODE_ARL
:
559 nvfx_vp_emit(vpc
, arith(0, VEC
, ARL
, dst
, mask
, src
[0], none
, none
));
561 case TGSI_OPCODE_CEIL
:
562 tmp
= nvfx_src(temp(vpc
));
563 nvfx_vp_emit(vpc
, arith(0, VEC
, FLR
, tmp
.reg
, mask
, neg(src
[0]), none
, none
));
564 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MOV
, dst
, mask
, neg(tmp
), none
, none
));
566 case TGSI_OPCODE_CMP
:
567 insn
= arith(0, VEC
, MOV
, none
.reg
, mask
, src
[0], none
, none
);
569 nvfx_vp_emit(vpc
, insn
);
571 insn
= arith(sat
, VEC
, MOV
, dst
, mask
, src
[2], none
, none
);
572 insn
.cc_test
= NVFX_COND_GE
;
573 nvfx_vp_emit(vpc
, insn
);
575 insn
= arith(sat
, VEC
, MOV
, dst
, mask
, src
[1], none
, none
);
576 insn
.cc_test
= NVFX_COND_LT
;
577 nvfx_vp_emit(vpc
, insn
);
579 case TGSI_OPCODE_COS
:
580 nvfx_vp_emit(vpc
, arith(sat
, SCA
, COS
, dst
, mask
, none
, none
, src
[0]));
582 case TGSI_OPCODE_DP2
:
583 tmp
= nvfx_src(temp(vpc
));
584 nvfx_vp_emit(vpc
, arith(0, VEC
, MUL
, tmp
.reg
, NVFX_VP_MASK_X
| NVFX_VP_MASK_Y
, src
[0], src
[1], none
));
585 nvfx_vp_emit(vpc
, arith(sat
, VEC
, ADD
, dst
, mask
, swz(tmp
, X
, X
, X
, X
), none
, swz(tmp
, Y
, Y
, Y
, Y
)));
587 case TGSI_OPCODE_DP3
:
588 nvfx_vp_emit(vpc
, arith(sat
, VEC
, DP3
, dst
, mask
, src
[0], src
[1], none
));
590 case TGSI_OPCODE_DP4
:
591 nvfx_vp_emit(vpc
, arith(sat
, VEC
, DP4
, dst
, mask
, src
[0], src
[1], none
));
593 case TGSI_OPCODE_DPH
:
594 nvfx_vp_emit(vpc
, arith(sat
, VEC
, DPH
, dst
, mask
, src
[0], src
[1], none
));
596 case TGSI_OPCODE_DST
:
597 nvfx_vp_emit(vpc
, arith(sat
, VEC
, DST
, dst
, mask
, src
[0], src
[1], none
));
599 case TGSI_OPCODE_EX2
:
600 nvfx_vp_emit(vpc
, arith(sat
, SCA
, EX2
, dst
, mask
, none
, none
, src
[0]));
602 case TGSI_OPCODE_EXP
:
603 nvfx_vp_emit(vpc
, arith(sat
, SCA
, EXP
, dst
, mask
, none
, none
, src
[0]));
605 case TGSI_OPCODE_FLR
:
606 nvfx_vp_emit(vpc
, arith(sat
, VEC
, FLR
, dst
, mask
, src
[0], none
, none
));
608 case TGSI_OPCODE_FRC
:
609 nvfx_vp_emit(vpc
, arith(sat
, VEC
, FRC
, dst
, mask
, src
[0], none
, none
));
611 case TGSI_OPCODE_LG2
:
612 nvfx_vp_emit(vpc
, arith(sat
, SCA
, LG2
, dst
, mask
, none
, none
, src
[0]));
614 case TGSI_OPCODE_LIT
:
615 nvfx_vp_emit(vpc
, arith(sat
, SCA
, LIT
, dst
, mask
, none
, none
, src
[0]));
617 case TGSI_OPCODE_LOG
:
618 nvfx_vp_emit(vpc
, arith(sat
, SCA
, LOG
, dst
, mask
, none
, none
, src
[0]));
620 case TGSI_OPCODE_LRP
:
621 tmp
= nvfx_src(temp(vpc
));
622 nvfx_vp_emit(vpc
, arith(0, VEC
, MAD
, tmp
.reg
, mask
, neg(src
[0]), src
[2], src
[2]));
623 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MAD
, dst
, mask
, src
[0], src
[1], tmp
));
625 case TGSI_OPCODE_MAD
:
626 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MAD
, dst
, mask
, src
[0], src
[1], src
[2]));
628 case TGSI_OPCODE_MAX
:
629 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MAX
, dst
, mask
, src
[0], src
[1], none
));
631 case TGSI_OPCODE_MIN
:
632 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MIN
, dst
, mask
, src
[0], src
[1], none
));
634 case TGSI_OPCODE_MOV
:
635 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MOV
, dst
, mask
, src
[0], none
, none
));
637 case TGSI_OPCODE_MUL
:
638 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MUL
, dst
, mask
, src
[0], src
[1], none
));
640 case TGSI_OPCODE_NOP
:
642 case TGSI_OPCODE_POW
:
643 tmp
= nvfx_src(temp(vpc
));
644 nvfx_vp_emit(vpc
, arith(0, SCA
, LG2
, tmp
.reg
, NVFX_VP_MASK_X
, none
, none
, swz(src
[0], X
, X
, X
, X
)));
645 nvfx_vp_emit(vpc
, arith(0, VEC
, MUL
, tmp
.reg
, NVFX_VP_MASK_X
, swz(tmp
, X
, X
, X
, X
), swz(src
[1], X
, X
, X
, X
), none
));
646 nvfx_vp_emit(vpc
, arith(sat
, SCA
, EX2
, dst
, mask
, none
, none
, swz(tmp
, X
, X
, X
, X
)));
648 case TGSI_OPCODE_RCP
:
649 nvfx_vp_emit(vpc
, arith(sat
, SCA
, RCP
, dst
, mask
, none
, none
, src
[0]));
651 case TGSI_OPCODE_RSQ
:
652 nvfx_vp_emit(vpc
, arith(sat
, SCA
, RSQ
, dst
, mask
, none
, none
, abs(src
[0])));
654 case TGSI_OPCODE_SEQ
:
655 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SEQ
, dst
, mask
, src
[0], src
[1], none
));
657 case TGSI_OPCODE_SGE
:
658 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SGE
, dst
, mask
, src
[0], src
[1], none
));
660 case TGSI_OPCODE_SGT
:
661 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SGT
, dst
, mask
, src
[0], src
[1], none
));
663 case TGSI_OPCODE_SIN
:
664 nvfx_vp_emit(vpc
, arith(sat
, SCA
, SIN
, dst
, mask
, none
, none
, src
[0]));
666 case TGSI_OPCODE_SLE
:
667 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SLE
, dst
, mask
, src
[0], src
[1], none
));
669 case TGSI_OPCODE_SLT
:
670 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SLT
, dst
, mask
, src
[0], src
[1], none
));
672 case TGSI_OPCODE_SNE
:
673 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SNE
, dst
, mask
, src
[0], src
[1], none
));
675 case TGSI_OPCODE_SSG
:
676 nvfx_vp_emit(vpc
, arith(sat
, VEC
, SSG
, dst
, mask
, src
[0], none
, none
));
678 case TGSI_OPCODE_SUB
:
679 nvfx_vp_emit(vpc
, arith(sat
, VEC
, ADD
, dst
, mask
, src
[0], none
, neg(src
[1])));
681 case TGSI_OPCODE_TRUNC
:
682 tmp
= nvfx_src(temp(vpc
));
683 insn
= arith(0, VEC
, MOV
, none
.reg
, mask
, src
[0], none
, none
);
685 nvfx_vp_emit(vpc
, insn
);
687 nvfx_vp_emit(vpc
, arith(0, VEC
, FLR
, tmp
.reg
, mask
, abs(src
[0]), none
, none
));
688 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MOV
, dst
, mask
, tmp
, none
, none
));
690 insn
= arith(sat
, VEC
, MOV
, dst
, mask
, neg(tmp
), none
, none
);
691 insn
.cc_test
= NVFX_COND_LT
;
692 nvfx_vp_emit(vpc
, insn
);
694 case TGSI_OPCODE_XPD
:
695 tmp
= nvfx_src(temp(vpc
));
696 nvfx_vp_emit(vpc
, arith(0, VEC
, MUL
, tmp
.reg
, mask
, swz(src
[0], Z
, X
, Y
, Y
), swz(src
[1], Y
, Z
, X
, X
), none
));
697 nvfx_vp_emit(vpc
, arith(sat
, VEC
, MAD
, dst
, (mask
& ~NVFX_VP_MASK_W
), swz(src
[0], Y
, Z
, X
, X
), swz(src
[1], Z
, X
, Y
, Y
), neg(tmp
)));
700 insn
= arith(0, VEC
, MOV
, none
.reg
, NVFX_VP_MASK_X
, src
[0], none
, none
);
702 nvfx_vp_emit(vpc
, insn
);
704 reloc
.location
= vpc
->vp
->nr_insns
;
705 reloc
.target
= finst
->Label
.Label
+ 1;
706 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
708 insn
= arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
);
709 insn
.cc_test
= NVFX_COND_EQ
;
710 insn
.cc_swz
[0] = insn
.cc_swz
[1] = insn
.cc_swz
[2] = insn
.cc_swz
[3] = 0;
711 nvfx_vp_emit(vpc
, insn
);
713 case TGSI_OPCODE_ELSE
:
714 case TGSI_OPCODE_CAL
:
715 reloc
.location
= vpc
->vp
->nr_insns
;
716 reloc
.target
= finst
->Label
.Label
;
717 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
719 if(finst
->Instruction
.Opcode
== TGSI_OPCODE_CAL
)
720 insn
= arith(0, SCA
, CAL
, none
.reg
, 0, none
, none
, none
);
722 insn
= arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
);
723 nvfx_vp_emit(vpc
, insn
);
725 case TGSI_OPCODE_RET
:
726 if(sub_depth
|| !vpc
->vp
->enabled_ucps
) {
728 tmp
.swz
[0] = tmp
.swz
[1] = tmp
.swz
[2] = tmp
.swz
[3] = 0;
729 nvfx_vp_emit(vpc
, arith(0, SCA
, RET
, none
.reg
, 0, none
, none
, tmp
));
731 reloc
.location
= vpc
->vp
->nr_insns
;
732 reloc
.target
= vpc
->info
->num_instructions
;
733 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
734 nvfx_vp_emit(vpc
, arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
737 case TGSI_OPCODE_BGNSUB
:
740 case TGSI_OPCODE_ENDSUB
:
743 case TGSI_OPCODE_ENDIF
:
744 /* nothing to do here */
746 case TGSI_OPCODE_BGNLOOP
:
747 loop
.cont_target
= idx
;
748 loop
.brk_target
= finst
->Label
.Label
+ 1;
749 util_dynarray_append(&vpc
->loop_stack
, struct nvfx_loop_entry
, loop
);
751 case TGSI_OPCODE_ENDLOOP
:
752 loop
= util_dynarray_pop(&vpc
->loop_stack
, struct nvfx_loop_entry
);
754 reloc
.location
= vpc
->vp
->nr_insns
;
755 reloc
.target
= loop
.cont_target
;
756 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
758 nvfx_vp_emit(vpc
, arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
760 case TGSI_OPCODE_CONT
:
761 loop
= util_dynarray_top(&vpc
->loop_stack
, struct nvfx_loop_entry
);
763 reloc
.location
= vpc
->vp
->nr_insns
;
764 reloc
.target
= loop
.cont_target
;
765 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
767 nvfx_vp_emit(vpc
, arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
769 case TGSI_OPCODE_BRK
:
770 loop
= util_dynarray_top(&vpc
->loop_stack
, struct nvfx_loop_entry
);
772 reloc
.location
= vpc
->vp
->nr_insns
;
773 reloc
.target
= loop
.brk_target
;
774 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
776 nvfx_vp_emit(vpc
, arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
778 case TGSI_OPCODE_END
:
780 if(vpc
->vp
->enabled_ucps
) {
781 if(idx
!= (vpc
->info
->num_instructions
- 1)) {
782 reloc
.location
= vpc
->vp
->nr_insns
;
783 reloc
.target
= vpc
->info
->num_instructions
;
784 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_relocation
, reloc
);
785 nvfx_vp_emit(vpc
, arith(0, SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
788 if(vpc
->vp
->nr_insns
)
789 vpc
->vp
->insns
[vpc
->vp
->nr_insns
- 1].data
[3] |= NVFX_VP_INST_LAST
;
790 nvfx_vp_emit(vpc
, arith(0, VEC
, NOP
, none
.reg
, 0, none
, none
, none
));
791 vpc
->vp
->insns
[vpc
->vp
->nr_insns
- 1].data
[3] |= NVFX_VP_INST_LAST
;
795 NOUVEAU_ERR("invalid opcode %d\n", finst
->Instruction
.Opcode
);
799 if(finst
->Instruction
.Saturate
&& !vpc
->is_nv4x
) {
800 if (!vpc
->r_0_1
.type
)
801 vpc
->r_0_1
= constant(vpc
, -1, 0, 1, 0, 0);
802 nvfx_vp_emit(vpc
, arith(0, VEC
, MAX
, dst
, mask
, nvfx_src(dst
), swz(nvfx_src(vpc
->r_0_1
), X
, X
, X
, X
), none
));
803 nvfx_vp_emit(vpc
, arith(0, VEC
, MIN
, final_dst
, mask
, nvfx_src(dst
), swz(nvfx_src(vpc
->r_0_1
), Y
, Y
, Y
, Y
), none
));
811 nvfx_vertprog_parse_decl_output(struct nvfx_vpc
*vpc
,
812 const struct tgsi_full_declaration
*fdec
)
814 unsigned num_texcoords
= vpc
->is_nv4x
? 10 : 8;
815 unsigned idx
= fdec
->Range
.First
;
816 unsigned semantic_index
= fdec
->Semantic
.Index
;
819 switch (fdec
->Semantic
.Name
) {
820 case TGSI_SEMANTIC_POSITION
:
821 hw
= NVFX_VP(INST_DEST_POS
);
824 case TGSI_SEMANTIC_CLIPVERTEX
:
825 vpc
->r_result
[idx
] = temp(vpc
);
826 vpc
->r_temps_discard
= 0;
829 case TGSI_SEMANTIC_COLOR
:
830 if (fdec
->Semantic
.Index
== 0) {
831 hw
= NVFX_VP(INST_DEST_COL0
);
833 if (fdec
->Semantic
.Index
== 1) {
834 hw
= NVFX_VP(INST_DEST_COL1
);
836 NOUVEAU_ERR("bad colour semantic index\n");
840 case TGSI_SEMANTIC_BCOLOR
:
841 if (fdec
->Semantic
.Index
== 0) {
842 hw
= NVFX_VP(INST_DEST_BFC0
);
844 if (fdec
->Semantic
.Index
== 1) {
845 hw
= NVFX_VP(INST_DEST_BFC1
);
847 NOUVEAU_ERR("bad bcolour semantic index\n");
851 case TGSI_SEMANTIC_FOG
:
852 hw
= NVFX_VP(INST_DEST_FOGC
);
854 case TGSI_SEMANTIC_PSIZE
:
855 hw
= NVFX_VP(INST_DEST_PSZ
);
857 case TGSI_SEMANTIC_GENERIC
:
858 /* this is really an identifier for VP/FP linkage */
861 case TGSI_SEMANTIC_TEXCOORD
:
862 for (i
= 0; i
< num_texcoords
; i
++) {
863 if (vpc
->vp
->texcoord
[i
] == semantic_index
) {
864 hw
= NVFX_VP(INST_DEST_TC(i
));
869 if (i
== num_texcoords
) {
870 vpc
->r_result
[idx
] = nvfx_reg(NVFXSR_NONE
, 0);
874 case TGSI_SEMANTIC_EDGEFLAG
:
875 vpc
->r_result
[idx
] = nvfx_reg(NVFXSR_NONE
, 0);
878 NOUVEAU_ERR("bad output semantic\n");
882 vpc
->r_result
[idx
] = nvfx_reg(NVFXSR_OUTPUT
, hw
);
887 nvfx_vertprog_prepare(struct nvfx_vpc
*vpc
)
889 struct tgsi_parse_context p
;
890 int high_const
= -1, high_temp
= -1, high_addr
= -1, nr_imm
= 0, i
;
892 tgsi_parse_init(&p
, vpc
->pipe
.tokens
);
893 while (!tgsi_parse_end_of_tokens(&p
)) {
894 const union tgsi_full_token
*tok
= &p
.FullToken
;
896 tgsi_parse_token(&p
);
897 switch(tok
->Token
.Type
) {
898 case TGSI_TOKEN_TYPE_IMMEDIATE
:
901 case TGSI_TOKEN_TYPE_DECLARATION
:
903 const struct tgsi_full_declaration
*fdec
;
905 fdec
= &p
.FullToken
.FullDeclaration
;
906 switch (fdec
->Declaration
.File
) {
907 case TGSI_FILE_TEMPORARY
:
908 if (fdec
->Range
.Last
> high_temp
) {
913 case TGSI_FILE_ADDRESS
:
914 if (fdec
->Range
.Last
> high_addr
) {
919 case TGSI_FILE_CONSTANT
:
920 if (fdec
->Range
.Last
> high_const
) {
925 case TGSI_FILE_OUTPUT
:
926 if (!nvfx_vertprog_parse_decl_output(vpc
, fdec
))
941 vpc
->imm
= CALLOC(nr_imm
, sizeof(struct nvfx_reg
));
946 vpc
->r_temp
= CALLOC(high_temp
, sizeof(struct nvfx_reg
));
947 for (i
= 0; i
< high_temp
; i
++)
948 vpc
->r_temp
[i
] = temp(vpc
);
952 vpc
->r_address
= CALLOC(high_addr
, sizeof(struct nvfx_reg
));
953 for (i
= 0; i
< high_addr
; i
++)
954 vpc
->r_address
[i
] = nvfx_reg(NVFXSR_TEMP
, i
);
958 vpc
->r_const
= CALLOC(high_const
, sizeof(struct nvfx_reg
));
959 for (i
= 0; i
< high_const
; i
++)
960 vpc
->r_const
[i
] = constant(vpc
, i
, 0, 0, 0, 0);
963 vpc
->r_temps_discard
= 0;
967 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp
, "NVFX_DUMP_VP", FALSE
)
970 _nvfx_vertprog_translate(uint16_t oclass
, struct nv30_vertprog
*vp
)
972 struct tgsi_parse_context parse
;
973 struct nvfx_vpc
*vpc
= NULL
;
974 struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
975 struct util_dynarray insns
;
978 vp
->translated
= FALSE
;
982 vpc
= CALLOC_STRUCT(nvfx_vpc
);
985 vpc
->is_nv4x
= (oclass
>= NV40_3D_CLASS
) ? ~0 : 0;
987 vpc
->pipe
= vp
->pipe
;
988 vpc
->info
= &vp
->info
;
991 if (!nvfx_vertprog_prepare(vpc
)) {
996 /* Redirect post-transform vertex position to a temp if user clip
997 * planes are enabled. We need to append code to the vtxprog
998 * to handle clip planes later.
1000 if (vp
->enabled_ucps
&& vpc
->cvtx_idx
< 0) {
1001 vpc
->r_result
[vpc
->hpos_idx
] = temp(vpc
);
1002 vpc
->r_temps_discard
= 0;
1003 vpc
->cvtx_idx
= vpc
->hpos_idx
;
1006 util_dynarray_init(&insns
);
1008 tgsi_parse_init(&parse
, vp
->pipe
.tokens
);
1009 while (!tgsi_parse_end_of_tokens(&parse
)) {
1010 tgsi_parse_token(&parse
);
1012 switch (parse
.FullToken
.Token
.Type
) {
1013 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1015 const struct tgsi_full_immediate
*imm
;
1017 imm
= &parse
.FullToken
.FullImmediate
;
1018 assert(imm
->Immediate
.DataType
== TGSI_IMM_FLOAT32
);
1019 assert(imm
->Immediate
.NrTokens
== 4 + 1);
1020 vpc
->imm
[vpc
->nr_imm
++] =
1028 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1030 const struct tgsi_full_instruction
*finst
;
1031 unsigned idx
= insns
.size
>> 2;
1032 util_dynarray_append(&insns
, unsigned, vp
->nr_insns
);
1033 finst
= &parse
.FullToken
.FullInstruction
;
1034 if (!nvfx_vertprog_parse_instruction(vpc
, idx
, finst
))
1043 util_dynarray_append(&insns
, unsigned, vp
->nr_insns
);
1045 for(unsigned i
= 0; i
< vpc
->label_relocs
.size
; i
+= sizeof(struct nvfx_relocation
))
1047 struct nvfx_relocation
* label_reloc
= (struct nvfx_relocation
*)((char*)vpc
->label_relocs
.data
+ i
);
1048 struct nvfx_relocation hw_reloc
;
1050 hw_reloc
.location
= label_reloc
->location
;
1051 hw_reloc
.target
= ((unsigned*)insns
.data
)[label_reloc
->target
];
1053 //debug_printf("hw %u -> tgsi %u = hw %u\n", hw_reloc.location, label_reloc->target, hw_reloc.target);
1055 util_dynarray_append(&vp
->branch_relocs
, struct nvfx_relocation
, hw_reloc
);
1057 util_dynarray_fini(&insns
);
1058 util_dynarray_trim(&vp
->branch_relocs
);
1060 /* XXX: what if we add a RET before?! make sure we jump here...*/
1062 /* Write out HPOS if it was redirected to a temp earlier */
1063 if (vpc
->r_result
[vpc
->hpos_idx
].type
!= NVFXSR_OUTPUT
) {
1064 struct nvfx_reg hpos
= nvfx_reg(NVFXSR_OUTPUT
,
1065 NVFX_VP(INST_DEST_POS
));
1066 struct nvfx_src htmp
= nvfx_src(vpc
->r_result
[vpc
->hpos_idx
]);
1068 nvfx_vp_emit(vpc
, arith(0, VEC
, MOV
, hpos
, NVFX_VP_MASK_ALL
, htmp
, none
, none
));
1071 /* Insert code to handle user clip planes */
1072 ucps
= vp
->enabled_ucps
;
1074 int i
= ffs(ucps
) - 1; ucps
&= ~(1 << i
);
1075 struct nvfx_reg cdst
= nvfx_reg(NVFXSR_OUTPUT
, NV30_VP_INST_DEST_CLP(i
));
1076 struct nvfx_src ceqn
= nvfx_src(nvfx_reg(NVFXSR_CONST
, 512 + i
));
1077 struct nvfx_src htmp
= nvfx_src(vpc
->r_result
[vpc
->cvtx_idx
]);
1083 case 0: case 3: mask
= NVFX_VP_MASK_Y
; break;
1084 case 1: case 4: mask
= NVFX_VP_MASK_Z
; break;
1085 case 2: case 5: mask
= NVFX_VP_MASK_W
; break;
1087 NOUVEAU_ERR("invalid clip dist #%d\n", i
);
1092 mask
= NVFX_VP_MASK_X
;
1094 nvfx_vp_emit(vpc
, arith(0, VEC
, DP4
, cdst
, mask
, htmp
, ceqn
, none
));
1097 if (vpc
->vp
->nr_insns
)
1098 vpc
->vp
->insns
[vpc
->vp
->nr_insns
- 1].data
[3] |= NVFX_VP_INST_LAST
;
1100 if(debug_get_option_nvfx_dump_vp())
1103 tgsi_dump(vpc
->pipe
.tokens
, 0);
1105 debug_printf("\n%s vertex program:\n", vpc
->is_nv4x
? "nv4x" : "nv3x");
1106 for (i
= 0; i
< vp
->nr_insns
; i
++)
1107 debug_printf("%3u: %08x %08x %08x %08x\n", i
, vp
->insns
[i
].data
[0], vp
->insns
[i
].data
[1], vp
->insns
[i
].data
[2], vp
->insns
[i
].data
[3]);
1111 vp
->translated
= TRUE
;
1114 tgsi_parse_free(&parse
);
1116 util_dynarray_fini(&vpc
->label_relocs
);
1117 util_dynarray_fini(&vpc
->loop_stack
);
1119 FREE(vpc
->r_address
);
1125 return vp
->translated
;