iris: propagate error from gen_perf_begin_query to glBeginPerfQueryINTEL
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_compute.xml.h
1 #ifndef NV50_COMPUTE_XML
2 #define NV50_COMPUTE_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/envytools/envytools/
8 git clone https://github.com/envytools/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - rnndb/graph/g80_compute.xml ( 14027 bytes, from 2015-02-14 02:01:36)
12 - rnndb/copyright.xml ( 6456 bytes, from 2015-02-14 02:01:36)
13 - rnndb/nvchipsets.xml ( 2833 bytes, from 2015-04-28 16:28:33)
14 - rnndb/fifo/nv_object.xml ( 15390 bytes, from 2015-04-22 20:36:09)
15 - rnndb/g80_defs.xml ( 18210 bytes, from 2015-10-19 20:49:59)
16
17 Copyright (C) 2006-2015 by the following authors:
18 - Artur Huillet <arthur.huillet@free.fr> (ahuillet)
19 - Ben Skeggs (darktama, darktama_)
20 - B. R. <koala_br@users.sourceforge.net> (koala_br)
21 - Carlos Martin <carlosmn@users.sf.net> (carlosmn)
22 - Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
23 - Dawid Gajownik <gajownik@users.sf.net> (gajownik)
24 - Dmitry Baryshkov
25 - Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
26 - EdB <edb_@users.sf.net> (edb_)
27 - Erik Waling <erikwailing@users.sf.net> (erikwaling)
28 - Francisco Jerez <currojerez@riseup.net> (curro)
29 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
30 - jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
31 - Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
32 - Laurent Carlier <lordheavym@gmail.com> (lordheavy)
33 - Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
34 - Maarten Maathuis <madman2003@gmail.com> (stillunknown)
35 - Marcin Koƛcielnicki <koriakin@0x04.net> (mwk, koriakin)
36 - Mark Carey <mark.carey@gmail.com> (careym)
37 - Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
38 - nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
39 - Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
40 - Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
41 - Peter Popov <ironpeter@users.sf.net> (ironpeter)
42 - Richard Hughes <hughsient@users.sf.net> (hughsient)
43 - Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
44 - Serge Martin
45 - Simon Raffeiner
46 - Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
47 - Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
48 - sturmflut <sturmflut@users.sf.net> (sturmflut)
49 - Sylvain Munaut <tnt@246tNt.com>
50 - Victor Stinner <victor.stinner@haypocalc.com> (haypo)
51 - Wladmir van der Laan <laanwj@gmail.com> (miathan6)
52 - Younes Manton <younes.m@gmail.com> (ymanton)
53
54 Permission is hereby granted, free of charge, to any person obtaining
55 a copy of this software and associated documentation files (the
56 "Software"), to deal in the Software without restriction, including
57 without limitation the rights to use, copy, modify, merge, publish,
58 distribute, sublicense, and/or sell copies of the Software, and to
59 permit persons to whom the Software is furnished to do so, subject to
60 the following conditions:
61
62 The above copyright notice and this permission notice (including the
63 next paragraph) shall be included in all copies or substantial
64 portions of the Software.
65
66 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
67 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
68 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
69 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
70 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
71 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
72 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
73 */
74
75
76
77 #define NV50_COMPUTE_DMA_NOTIFY 0x00000180
78
79 #define NV50_COMPUTE_DMA_GLOBAL 0x000001a0
80
81 #define NV50_COMPUTE_DMA_QUERY 0x000001a4
82
83 #define NV50_COMPUTE_DMA_LOCAL 0x000001b8
84
85 #define NV50_COMPUTE_DMA_STACK 0x000001bc
86
87 #define NV50_COMPUTE_DMA_CODE_CB 0x000001c0
88
89 #define NV50_COMPUTE_DMA_TSC 0x000001c4
90
91 #define NV50_COMPUTE_DMA_TIC 0x000001c8
92
93 #define NV50_COMPUTE_DMA_TEXTURE 0x000001cc
94
95 #define NV50_COMPUTE_UNK0200 0x00000200
96 #define NV50_COMPUTE_UNK0200_UNK1__MASK 0x0000ffff
97 #define NV50_COMPUTE_UNK0200_UNK1__SHIFT 0
98 #define NV50_COMPUTE_UNK0200_UNK2__MASK 0x00ff0000
99 #define NV50_COMPUTE_UNK0200_UNK2__SHIFT 16
100
101 #define NV50_COMPUTE_UNK0204 0x00000204
102
103 #define NV50_COMPUTE_UNK0208 0x00000208
104
105 #define NV50_COMPUTE_UNK020C 0x0000020c
106
107 #define NV50_COMPUTE_CP_ADDRESS_HIGH 0x00000210
108
109 #define NV50_COMPUTE_CP_ADDRESS_LOW 0x00000214
110
111 #define NV50_COMPUTE_STACK_ADDRESS_HIGH 0x00000218
112
113 #define NV50_COMPUTE_STACK_ADDRESS_LOW 0x0000021c
114
115 #define NV50_COMPUTE_STACK_SIZE_LOG 0x00000220
116
117 #define NV50_COMPUTE_CALL_LIMIT_LOG 0x00000224
118
119 #define NV50_COMPUTE_UNK0228 0x00000228
120 #define NV50_COMPUTE_UNK0228_UNK0 0x00000001
121 #define NV50_COMPUTE_UNK0228_UNK4__MASK 0x00000ff0
122 #define NV50_COMPUTE_UNK0228_UNK4__SHIFT 4
123 #define NV50_COMPUTE_UNK0228_UNK12__MASK 0x000ff000
124 #define NV50_COMPUTE_UNK0228_UNK12__SHIFT 12
125
126 #define NV50_COMPUTE_TSC_ADDRESS_HIGH 0x0000022c
127
128 #define NV50_COMPUTE_TSC_ADDRESS_LOW 0x00000230
129 #define NV50_COMPUTE_TSC_ADDRESS_LOW__ALIGN 0x00000020
130
131 #define NV50_COMPUTE_TSC_LIMIT 0x00000234
132 #define NV50_COMPUTE_TSC_LIMIT__MAX 0x00001fff
133
134 #define NV50_COMPUTE_CB_ADDR 0x00000238
135 #define NV50_COMPUTE_CB_ADDR_ID__MASK 0x003fff00
136 #define NV50_COMPUTE_CB_ADDR_ID__SHIFT 8
137 #define NV50_COMPUTE_CB_ADDR_BUFFER__MASK 0x0000007f
138 #define NV50_COMPUTE_CB_ADDR_BUFFER__SHIFT 0
139
140 #define NV50_COMPUTE_CB_DATA(i0) (0x0000023c + 0x4*(i0))
141 #define NV50_COMPUTE_CB_DATA__ESIZE 0x00000004
142 #define NV50_COMPUTE_CB_DATA__LEN 0x00000010
143
144 #define NV50_COMPUTE_TSC_FLUSH 0x0000027c
145 #define NV50_COMPUTE_TSC_FLUSH_SPECIFIC 0x00000001
146 #define NV50_COMPUTE_TSC_FLUSH_ENTRY__MASK 0x03fffff0
147 #define NV50_COMPUTE_TSC_FLUSH_ENTRY__SHIFT 4
148
149 #define NV50_COMPUTE_TIC_FLUSH 0x00000280
150 #define NV50_COMPUTE_TIC_FLUSH_SPECIFIC 0x00000001
151 #define NV50_COMPUTE_TIC_FLUSH_ENTRY__MASK 0x03fffff0
152 #define NV50_COMPUTE_TIC_FLUSH_ENTRY__SHIFT 4
153
154 #define NV50_COMPUTE_DELAY1 0x00000284
155
156 #define NV50_COMPUTE_WATCHDOG_TIMER 0x00000288
157
158 #define NV50_COMPUTE_DELAY2 0x0000028c
159
160 #define NV50_COMPUTE_UNK0290 0x00000290
161
162 #define NV50_COMPUTE_LOCAL_ADDRESS_HIGH 0x00000294
163
164 #define NV50_COMPUTE_LOCAL_ADDRESS_LOW 0x00000298
165 #define NV50_COMPUTE_LOCAL_ADDRESS_LOW__ALIGN 0x00000100
166
167 #define NV50_COMPUTE_LOCAL_SIZE_LOG 0x0000029c
168
169 #define NV50_COMPUTE_UNK02A0 0x000002a0
170
171 #define NV50_COMPUTE_CB_DEF_ADDRESS_HIGH 0x000002a4
172
173 #define NV50_COMPUTE_CB_DEF_ADDRESS_LOW 0x000002a8
174
175 #define NV50_COMPUTE_CB_DEF_SET 0x000002ac
176 #define NV50_COMPUTE_CB_DEF_SET_SIZE__MASK 0x0000ffff
177 #define NV50_COMPUTE_CB_DEF_SET_SIZE__SHIFT 0
178 #define NV50_COMPUTE_CB_DEF_SET_BUFFER__MASK 0x007f0000
179 #define NV50_COMPUTE_CB_DEF_SET_BUFFER__SHIFT 16
180
181 #define NV50_COMPUTE_UNK02B0 0x000002b0
182
183 #define NV50_COMPUTE_BLOCK_ALLOC 0x000002b4
184 #define NV50_COMPUTE_BLOCK_ALLOC_THREADS__MASK 0x0000ffff
185 #define NV50_COMPUTE_BLOCK_ALLOC_THREADS__SHIFT 0
186 #define NV50_COMPUTE_BLOCK_ALLOC_BARRIERS__MASK 0x00ff0000
187 #define NV50_COMPUTE_BLOCK_ALLOC_BARRIERS__SHIFT 16
188
189 #define NV50_COMPUTE_LANES32_ENABLE 0x000002b8
190
191 #define NV50_COMPUTE_UNK02BC 0x000002bc
192 #define NV50_COMPUTE_UNK02BC_UNK1__MASK 0x00000007
193 #define NV50_COMPUTE_UNK02BC_UNK1__SHIFT 0
194 #define NV50_COMPUTE_UNK02BC_UNK2__MASK 0x00000070
195 #define NV50_COMPUTE_UNK02BC_UNK2__SHIFT 4
196
197 #define NV50_COMPUTE_CP_REG_ALLOC_TEMP 0x000002c0
198
199 #define NV50_COMPUTE_TIC_ADDRESS_HIGH 0x000002c4
200
201 #define NV50_COMPUTE_TIC_ADDRESS_LOW 0x000002c8
202
203 #define NV50_COMPUTE_TIC_LIMIT 0x000002cc
204
205 #define NV50_COMPUTE_MP_PM_SET(i0) (0x000002d0 + 0x4*(i0))
206 #define NV50_COMPUTE_MP_PM_SET__ESIZE 0x00000004
207 #define NV50_COMPUTE_MP_PM_SET__LEN 0x00000004
208
209 #define NV50_COMPUTE_MP_PM_CONTROL(i0) (0x000002e0 + 0x4*(i0))
210 #define NV50_COMPUTE_MP_PM_CONTROL__ESIZE 0x00000004
211 #define NV50_COMPUTE_MP_PM_CONTROL__LEN 0x00000004
212 #define NV50_COMPUTE_MP_PM_CONTROL_MODE__MASK 0x00000001
213 #define NV50_COMPUTE_MP_PM_CONTROL_MODE__SHIFT 0
214 #define NV50_COMPUTE_MP_PM_CONTROL_MODE_LOGOP 0x00000000
215 #define NV50_COMPUTE_MP_PM_CONTROL_MODE_LOGOP_PULSE 0x00000001
216 #define NV50_COMPUTE_MP_PM_CONTROL_UNIT__MASK 0x00000070
217 #define NV50_COMPUTE_MP_PM_CONTROL_UNIT__SHIFT 4
218 #define NV50_COMPUTE_MP_PM_CONTROL_UNIT_UNK0 0x00000000
219 #define NV50_COMPUTE_MP_PM_CONTROL_UNIT_UNK1 0x00000010
220 #define NV50_COMPUTE_MP_PM_CONTROL_UNIT_UNK2 0x00000020
221 #define NV50_COMPUTE_MP_PM_CONTROL_UNIT_UNK3 0x00000030
222 #define NV50_COMPUTE_MP_PM_CONTROL_UNIT_UNK4 0x00000040
223 #define NV50_COMPUTE_MP_PM_CONTROL_UNIT_UNK5 0x00000050
224 #define NV50_COMPUTE_MP_PM_CONTROL_FUNC__MASK 0x00ffff00
225 #define NV50_COMPUTE_MP_PM_CONTROL_FUNC__SHIFT 8
226 #define NV50_COMPUTE_MP_PM_CONTROL_SIG__MASK 0xff000000
227 #define NV50_COMPUTE_MP_PM_CONTROL_SIG__SHIFT 24
228
229 #define NV50_COMPUTE_MP_PM_OVERFLOW_TRAP_ENABLE 0x000002f0
230 #define NV50_COMPUTE_MP_PM_OVERFLOW_TRAP_ENABLE_0 0x00000001
231 #define NV50_COMPUTE_MP_PM_OVERFLOW_TRAP_ENABLE_1 0x00000002
232 #define NV50_COMPUTE_MP_PM_OVERFLOW_TRAP_ENABLE_2 0x00000004
233 #define NV50_COMPUTE_MP_PM_OVERFLOW_TRAP_ENABLE_3 0x00000008
234
235 #define NV50_COMPUTE_UNK02F4 0x000002f4
236
237 #define NV50_COMPUTE_BLOCKDIM_LATCH 0x000002f8
238
239 #define NV50_COMPUTE_LOCAL_WARPS_LOG_ALLOC 0x000002fc
240
241 #define NV50_COMPUTE_LOCAL_WARPS_NO_CLAMP 0x00000300
242
243 #define NV50_COMPUTE_STACK_WARPS_LOG_ALLOC 0x00000304
244
245 #define NV50_COMPUTE_STACK_WARPS_NO_CLAMP 0x00000308
246
247 #define NV50_COMPUTE_UNK030C 0x0000030c
248
249 #define NV50_COMPUTE_QUERY_ADDRESS_HIGH 0x00000310
250
251 #define NV50_COMPUTE_QUERY_ADDRESS_LOW 0x00000314
252
253 #define NV50_COMPUTE_QUERY_SEQUENCE 0x00000318
254
255 #define NV50_COMPUTE_QUERY_GET 0x0000031c
256 #define NV50_COMPUTE_QUERY_GET_INTR 0x00000200
257 #define NV50_COMPUTE_QUERY_GET_SHORT 0x00008000
258
259 #define NV50_COMPUTE_COND_ADDRESS_HIGH 0x00000320
260
261 #define NV50_COMPUTE_COND_ADDRESS_LOW 0x00000324
262
263 #define NV50_COMPUTE_COND_MODE 0x00000328
264 #define NV50_COMPUTE_COND_MODE_NEVER 0x00000000
265 #define NV50_COMPUTE_COND_MODE_ALWAYS 0x00000001
266 #define NV50_COMPUTE_COND_MODE_RES_NON_ZERO 0x00000002
267 #define NV50_COMPUTE_COND_MODE_EQUAL 0x00000003
268 #define NV50_COMPUTE_COND_MODE_NOT_EQUAL 0x00000004
269
270 #define NV50_COMPUTE_UNK032C 0x0000032c
271
272 #define NV50_COMPUTE_UNK0330 0x00000330
273
274 #define NV50_COMPUTE_UNK0334(i0) (0x00000334 + 0x4*(i0))
275 #define NV50_COMPUTE_UNK0334__ESIZE 0x00000004
276 #define NV50_COMPUTE_UNK0334__LEN 0x00000003
277
278 #define NV50_COMPUTE_UNK0340(i0) (0x00000340 + 0x4*(i0))
279 #define NV50_COMPUTE_UNK0340__ESIZE 0x00000004
280 #define NV50_COMPUTE_UNK0340__LEN 0x00000002
281
282 #define NV50_COMPUTE_UNK0348(i0) (0x00000348 + 0x4*(i0))
283 #define NV50_COMPUTE_UNK0348__ESIZE 0x00000004
284 #define NV50_COMPUTE_UNK0348__LEN 0x00000002
285
286 #define NV50_COMPUTE_UNK0350(i0) (0x00000350 + 0x4*(i0))
287 #define NV50_COMPUTE_UNK0350__ESIZE 0x00000004
288 #define NV50_COMPUTE_UNK0350__LEN 0x00000002
289
290 #define NV50_COMPUTE_UNK0358 0x00000358
291
292 #define NV50_COMPUTE_UNK035C 0x0000035c
293
294 #define NV50_COMPUTE_UNK0360 0x00000360
295 #define NV50_COMPUTE_UNK0360_UNK0__MASK 0x000000f0
296 #define NV50_COMPUTE_UNK0360_UNK0__SHIFT 4
297 #define NV50_COMPUTE_UNK0360_UNK1__MASK 0x00000f00
298 #define NV50_COMPUTE_UNK0360_UNK1__SHIFT 8
299
300 #define NV50_COMPUTE_UNK0364 0x00000364
301
302 #define NV50_COMPUTE_LAUNCH 0x00000368
303
304 #define NV50_COMPUTE_UNK036C 0x0000036c
305
306 #define NV50_COMPUTE_UNK0370 0x00000370
307
308 #define NV50_COMPUTE_USER_PARAM_COUNT 0x00000374
309 #define NV50_COMPUTE_USER_PARAM_COUNT_UNK0__MASK 0x000000ff
310 #define NV50_COMPUTE_USER_PARAM_COUNT_UNK0__SHIFT 0
311 #define NV50_COMPUTE_USER_PARAM_COUNT_COUNT__MASK 0x0000ff00
312 #define NV50_COMPUTE_USER_PARAM_COUNT_COUNT__SHIFT 8
313 #define NV50_COMPUTE_USER_PARAM_COUNT_COUNT__MAX 0x00000040
314
315 #define NV50_COMPUTE_LINKED_TSC 0x00000378
316
317 #define NV50_COMPUTE_UNK037C 0x0000037c
318 #define NV50_COMPUTE_UNK037C_ALWAYS_DERIV 0x00000001
319 #define NV50_COMPUTE_UNK037C_UNK16 0x00010000
320
321 #define NV50_COMPUTE_CODE_CB_FLUSH 0x00000380
322
323 #define NV50_COMPUTE_UNK0384 0x00000384
324
325 #define NV50_COMPUTE_GRIDID 0x00000388
326
327 #define NV50_COMPUTE_UNK038C(i0) (0x0000038c + 0x4*(i0))
328 #define NV50_COMPUTE_UNK038C__ESIZE 0x00000004
329 #define NV50_COMPUTE_UNK038C__LEN 0x00000003
330
331 #define NV50_COMPUTE_WRCACHE_FLUSH 0x00000398
332
333 #define NV50_COMPUTE_UNK039C(i0) (0x0000039c + 0x4*(i0))
334 #define NV50_COMPUTE_UNK039C__ESIZE 0x00000004
335 #define NV50_COMPUTE_UNK039C__LEN 0x00000002
336
337 #define NV50_COMPUTE_GRIDDIM 0x000003a4
338 #define NV50_COMPUTE_GRIDDIM_X__MASK 0x0000ffff
339 #define NV50_COMPUTE_GRIDDIM_X__SHIFT 0
340 #define NV50_COMPUTE_GRIDDIM_Y__MASK 0xffff0000
341 #define NV50_COMPUTE_GRIDDIM_Y__SHIFT 16
342
343 #define NV50_COMPUTE_SHARED_SIZE 0x000003a8
344 #define NV50_COMPUTE_SHARED_SIZE__MAX 0x00004000
345 #define NV50_COMPUTE_SHARED_SIZE__ALIGN 0x00000040
346
347 #define NV50_COMPUTE_BLOCKDIM_XY 0x000003ac
348 #define NV50_COMPUTE_BLOCKDIM_XY_X__MASK 0x0000ffff
349 #define NV50_COMPUTE_BLOCKDIM_XY_X__SHIFT 0
350 #define NV50_COMPUTE_BLOCKDIM_XY_Y__MASK 0xffff0000
351 #define NV50_COMPUTE_BLOCKDIM_XY_Y__SHIFT 16
352
353 #define NV50_COMPUTE_BLOCKDIM_Z 0x000003b0
354 #define NV50_COMPUTE_BLOCKDIM_Z__MIN 0x00000001
355 #define NV50_COMPUTE_BLOCKDIM_Z__MAX 0x00000040
356
357 #define NV50_COMPUTE_CP_START_ID 0x000003b4
358
359 #define NV50_COMPUTE_REG_MODE 0x000003b8
360 #define NV50_COMPUTE_REG_MODE_PACKED 0x00000001
361 #define NV50_COMPUTE_REG_MODE_STRIPED 0x00000002
362
363 #define NV50_COMPUTE_TEX_LIMITS 0x000003bc
364 #define NV50_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__MASK 0x0000000f
365 #define NV50_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__SHIFT 0
366 #define NV50_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__MIN 0x00000000
367 #define NV50_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__MAX 0x00000004
368 #define NV50_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__MASK 0x000000f0
369 #define NV50_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__SHIFT 4
370 #define NV50_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__MIN 0x00000000
371 #define NV50_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__MAX 0x00000007
372
373 #define NV50_COMPUTE_BIND_TSC 0x000003c0
374 #define NV50_COMPUTE_BIND_TSC_VALID 0x00000001
375 #define NV50_COMPUTE_BIND_TSC_SAMPLER__MASK 0x000000f0
376 #define NV50_COMPUTE_BIND_TSC_SAMPLER__SHIFT 4
377 #define NV50_COMPUTE_BIND_TSC_TSC__MASK 0x001ff000
378 #define NV50_COMPUTE_BIND_TSC_TSC__SHIFT 12
379
380 #define NV50_COMPUTE_BIND_TIC 0x000003c4
381 #define NV50_COMPUTE_BIND_TIC_VALID 0x00000001
382 #define NV50_COMPUTE_BIND_TIC_TEXTURE__MASK 0x000001fe
383 #define NV50_COMPUTE_BIND_TIC_TEXTURE__SHIFT 1
384 #define NV50_COMPUTE_BIND_TIC_TIC__MASK 0x7ffffe00
385 #define NV50_COMPUTE_BIND_TIC_TIC__SHIFT 9
386
387 #define NV50_COMPUTE_SET_PROGRAM_CB 0x000003c8
388 #define NV50_COMPUTE_SET_PROGRAM_CB_INDEX__MASK 0x00000f00
389 #define NV50_COMPUTE_SET_PROGRAM_CB_INDEX__SHIFT 8
390 #define NV50_COMPUTE_SET_PROGRAM_CB_BUFFER__MASK 0x0007f000
391 #define NV50_COMPUTE_SET_PROGRAM_CB_BUFFER__SHIFT 12
392 #define NV50_COMPUTE_SET_PROGRAM_CB_VALID 0x000000ff
393
394 #define NV50_COMPUTE_UNK03CC 0x000003cc
395
396 #define NV50_COMPUTE_TEX_CACHE_CTL 0x000003d0
397 #define NV50_COMPUTE_TEX_CACHE_CTL_UNK1__MASK 0x00000030
398 #define NV50_COMPUTE_TEX_CACHE_CTL_UNK1__SHIFT 4
399
400 #define NV50_COMPUTE_UNK03D4 0x000003d4
401
402 #define NV50_COMPUTE_UNK03D8 0x000003d8
403
404 #define NV50_COMPUTE_UNK03DC 0x000003dc
405
406 #define NV50_COMPUTE_UNK03E0 0x000003e0
407
408 #define NV50_COMPUTE_UNK03E4 0x000003e4
409
410 #define NVA3_COMPUTE_TEX_MISC 0x000003e8
411 #define NVA3_COMPUTE_TEX_MISC_UNK1 0x00000001
412 #define NVA3_COMPUTE_TEX_MISC_SEAMLESS_CUBE_MAP 0x00000002
413
414 #define NV50_COMPUTE_GLOBAL(i0) (0x00000400 + 0x20*(i0))
415 #define NV50_COMPUTE_GLOBAL__ESIZE 0x00000020
416 #define NV50_COMPUTE_GLOBAL__LEN 0x00000010
417
418 #define NV50_COMPUTE_GLOBAL_ADDRESS_HIGH(i0) (0x00000400 + 0x20*(i0))
419
420 #define NV50_COMPUTE_GLOBAL_ADDRESS_LOW(i0) (0x00000404 + 0x20*(i0))
421
422 #define NV50_COMPUTE_GLOBAL_PITCH(i0) (0x00000408 + 0x20*(i0))
423 #define NV50_COMPUTE_GLOBAL_PITCH__MAX 0x00800000
424 #define NV50_COMPUTE_GLOBAL_PITCH__ALIGN 0x00000100
425
426 #define NV50_COMPUTE_GLOBAL_LIMIT(i0) (0x0000040c + 0x20*(i0))
427
428 #define NV50_COMPUTE_GLOBAL_MODE(i0) (0x00000410 + 0x20*(i0))
429 #define NV50_COMPUTE_GLOBAL_MODE_LINEAR 0x00000001
430 #define NV50_COMPUTE_GLOBAL_MODE_UNK1__MASK 0x000000f0
431 #define NV50_COMPUTE_GLOBAL_MODE_UNK1__SHIFT 4
432 #define NV50_COMPUTE_GLOBAL_MODE_TILE_MODE__MASK 0x00000f00
433 #define NV50_COMPUTE_GLOBAL_MODE_TILE_MODE__SHIFT 8
434
435 #define NV50_COMPUTE_USER_PARAM(i0) (0x00000600 + 0x4*(i0))
436 #define NV50_COMPUTE_USER_PARAM__ESIZE 0x00000004
437 #define NV50_COMPUTE_USER_PARAM__LEN 0x00000040
438
439 #define NV50_COMPUTE_UNK0700(i0) (0x00000700 + 0x4*(i0))
440 #define NV50_COMPUTE_UNK0700__ESIZE 0x00000004
441 #define NV50_COMPUTE_UNK0700__LEN 0x00000010
442
443
444 #endif /* NV50_COMPUTE_XML */