src/gallium/drivers/nouveau/nv50/nv50_program.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "nv50/nv50_program.h"
  24 #include "nv50/nv50_context.h"
  25
  26 #include "codegen/nv50_ir_driver.h"
  27
  28 static INLINE unsigned
  29 bitcount4(const uint32_t val)
  30 {
  31    static const uint8_t cnt[16]
  32    = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
  33    return cnt[val & 0xf];
  34 }
  35
  36 static int
  37 nv50_vertprog_assign_slots(struct nv50_ir_prog_info *info)
  38 {
  39    struct nv50_program *prog = (struct nv50_program *)info->driverPriv;
  40    unsigned i, n, c;
  41
  42    n = 0;
  43    for (i = 0; i < info->numInputs; ++i) {
  44       prog->in[i].id = i;
  45       prog->in[i].sn = info->in[i].sn;
  46       prog->in[i].si = info->in[i].si;
  47       prog->in[i].hw = n;
  48       prog->in[i].mask = info->in[i].mask;
  49
  50       prog->vp.attrs[(4 * i) / 32] |= info->in[i].mask << ((4 * i) % 32);
  51
  52       for (c = 0; c < 4; ++c)
  53          if (info->in[i].mask & (1 << c))
  54             info->in[i].slot[c] = n++;
  55
  56       if (info->in[i].sn == TGSI_SEMANTIC_PRIMID)
  57          prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_PRIMITIVE_ID;
  58    }
  59    prog->in_nr = info->numInputs;
  60
  61    for (i = 0; i < info->numSysVals; ++i) {
  62       switch (info->sv[i].sn) {
  63       case TGSI_SEMANTIC_INSTANCEID:
  64          prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_INSTANCE_ID;
  65          continue;
  66       case TGSI_SEMANTIC_VERTEXID:
  67          prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID;
  68          prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_UNK12;
  69          continue;
  70       default:
  71          break;
  72       }
  73    }
  74
  75    /*
  76     * Corner case: VP has no inputs, but we will still need to submit data to
  77     * draw it. HW will shout at us and won't draw anything if we don't enable
  78     * any input, so let's just pretend it's the first one.
  79     */
  80    if (prog->vp.attrs[0] == 0 &&
  81        prog->vp.attrs[1] == 0 &&
  82        prog->vp.attrs[2] == 0)
  83       prog->vp.attrs[0] |= 0xf;
  84
  85    /* VertexID before InstanceID */
  86    if (info->io.vertexId < info->numSysVals)
  87       info->sv[info->io.vertexId].slot[0] = n++;
  88    if (info->io.instanceId < info->numSysVals)
  89       info->sv[info->io.instanceId].slot[0] = n++;
  90
  91    n = 0;
  92    for (i = 0; i < info->numOutputs; ++i) {
  93       switch (info->out[i].sn) {
  94       case TGSI_SEMANTIC_PSIZE:
  95          prog->vp.psiz = i;
  96          break;
  97       case TGSI_SEMANTIC_CLIPDIST:
  98          prog->vp.clpd[info->out[i].si] = n;
  99          break;
 100       case TGSI_SEMANTIC_EDGEFLAG:
 101          prog->vp.edgeflag = i;
 102          break;
 103       case TGSI_SEMANTIC_BCOLOR:
 104          prog->vp.bfc[info->out[i].si] = i;
 105          break;
 106       case TGSI_SEMANTIC_LAYER:
 107          prog->gp.has_layer = true;
 108          prog->gp.layerid = n;
 109          break;
 110       default:
 111          break;
 112       }
 113       prog->out[i].id = i;
 114       prog->out[i].sn = info->out[i].sn;
 115       prog->out[i].si = info->out[i].si;
 116       prog->out[i].hw = n;
 117       prog->out[i].mask = info->out[i].mask;
 118
 119       for (c = 0; c < 4; ++c)
 120          if (info->out[i].mask & (1 << c))
 121             info->out[i].slot[c] = n++;
 122    }
 123    prog->out_nr = info->numOutputs;
 124    prog->max_out = n;
 125    if (!prog->max_out)
 126       prog->max_out = 1;
 127
 128    if (prog->vp.psiz < info->numOutputs)
 129       prog->vp.psiz = prog->out[prog->vp.psiz].hw;
 130
 131    return 0;
 132 }
 133
 134 static int
 135 nv50_fragprog_assign_slots(struct nv50_ir_prog_info *info)
 136 {
 137    struct nv50_program *prog = (struct nv50_program *)info->driverPriv;
 138    unsigned i, n, m, c;
 139    unsigned nvary;
 140    unsigned nflat;
 141    unsigned nintp = 0;
 142
 143    /* count recorded non-flat inputs */
 144    for (m = 0, i = 0; i < info->numInputs; ++i) {
 145       switch (info->in[i].sn) {
 146       case TGSI_SEMANTIC_POSITION:
 147       case TGSI_SEMANTIC_FACE:
 148          continue;
 149       default:
 150          m += info->in[i].flat ? 0 : 1;
 151          break;
 152       }
 153    }
 154    /* careful: id may be != i in info->in[prog->in[i].id] */
 155
 156    /* Fill prog->in[] so that non-flat inputs are first and
 157     * kick out special inputs that don't use the RESULT_MAP.
 158     */
 159    for (n = 0, i = 0; i < info->numInputs; ++i) {
 160       if (info->in[i].sn == TGSI_SEMANTIC_POSITION) {
 161          prog->fp.interp |= info->in[i].mask << 24;
 162          for (c = 0; c < 4; ++c)
 163             if (info->in[i].mask & (1 << c))
 164                info->in[i].slot[c] = nintp++;
 165       } else
 166       if (info->in[i].sn == TGSI_SEMANTIC_FACE) {
 167          info->in[i].slot[0] = 255;
 168       } else {
 169          unsigned j = info->in[i].flat ? m++ : n++;
 170
 171          if (info->in[i].sn == TGSI_SEMANTIC_COLOR)
 172             prog->vp.bfc[info->in[i].si] = j;
 173          else if (info->in[i].sn == TGSI_SEMANTIC_PRIMID) {
 174             prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_PRIMITIVE_ID;
 175             prog->gp.primid = j;
 176          }
 177
 178          prog->in[j].id = i;
 179          prog->in[j].mask = info->in[i].mask;
 180          prog->in[j].sn = info->in[i].sn;
 181          prog->in[j].si = info->in[i].si;
 182          prog->in[j].linear = info->in[i].linear;
 183
 184          prog->in_nr++;
 185       }
 186    }
 187    if (!(prog->fp.interp & (8 << 24))) {
 188       ++nintp;
 189       prog->fp.interp |= 8 << 24;
 190    }
 191
 192    for (i = 0; i < prog->in_nr; ++i) {
 193       int j = prog->in[i].id;
 194
 195       prog->in[i].hw = nintp;
 196       for (c = 0; c < 4; ++c)
 197          if (prog->in[i].mask & (1 << c))
 198             info->in[j].slot[c] = nintp++;
 199    }
 200    /* (n == m) if m never increased, i.e. no flat inputs */
 201    nflat = (n < m) ? (nintp - prog->in[n].hw) : 0;
 202    nintp -= bitcount4(prog->fp.interp >> 24); /* subtract position inputs */
 203    nvary = nintp - nflat;
 204
 205    prog->fp.interp |= nvary << NV50_3D_FP_INTERPOLANT_CTRL_COUNT_NONFLAT__SHIFT;
 206    prog->fp.interp |= nintp << NV50_3D_FP_INTERPOLANT_CTRL_COUNT__SHIFT;
 207
 208    /* put front/back colors right after HPOS */
 209    prog->fp.colors = 4 << NV50_3D_SEMANTIC_COLOR_FFC0_ID__SHIFT;
 210    for (i = 0; i < 2; ++i)
 211       if (prog->vp.bfc[i] < 0xff)
 212          prog->fp.colors += bitcount4(prog->in[prog->vp.bfc[i]].mask) << 16;
 213
 214    /* FP outputs */
 215
 216    if (info->prop.fp.numColourResults > 1)
 217       prog->fp.flags[0] |= NV50_3D_FP_CONTROL_MULTIPLE_RESULTS;
 218
 219    for (i = 0; i < info->numOutputs; ++i) {
 220       prog->out[i].id = i;
 221       prog->out[i].sn = info->out[i].sn;
 222       prog->out[i].si = info->out[i].si;
 223       prog->out[i].mask = info->out[i].mask;
 224
 225       if (i == info->io.fragDepth || i == info->io.sampleMask)
 226          continue;
 227       prog->out[i].hw = info->out[i].si * 4;
 228
 229       for (c = 0; c < 4; ++c)
 230          info->out[i].slot[c] = prog->out[i].hw + c;
 231
 232       prog->max_out = MAX2(prog->max_out, prog->out[i].hw + 4);
 233    }
 234
 235    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
 236       info->out[info->io.sampleMask].slot[0] = prog->max_out++;
 237
 238    if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
 239       info->out[info->io.fragDepth].slot[2] = prog->max_out++;
 240
 241    if (!prog->max_out)
 242       prog->max_out = 4;
 243
 244    return 0;
 245 }
 246
 247 static int
 248 nv50_program_assign_varying_slots(struct nv50_ir_prog_info *info)
 249 {
 250    switch (info->type) {
 251    case PIPE_SHADER_VERTEX:
 252       return nv50_vertprog_assign_slots(info);
 253    case PIPE_SHADER_GEOMETRY:
 254       return nv50_vertprog_assign_slots(info);
 255    case PIPE_SHADER_FRAGMENT:
 256       return nv50_fragprog_assign_slots(info);
 257    default:
 258       return -1;
 259    }
 260 }
 261
 262 static struct nv50_stream_output_state *
 263 nv50_program_create_strmout_state(const struct nv50_ir_prog_info *info,
 264                                   const struct pipe_stream_output_info *pso)
 265 {
 266    struct nv50_stream_output_state *so;
 267    unsigned b, i, c;
 268    unsigned base[4];
 269
 270    so = MALLOC_STRUCT(nv50_stream_output_state);
 271    if (!so)
 272       return NULL;
 273    memset(so->map, 0xff, sizeof(so->map));
 274
 275    for (b = 0; b < 4; ++b)
 276       so->num_attribs[b] = 0;
 277    for (i = 0; i < pso->num_outputs; ++i) {
 278       unsigned end =  pso->output[i].dst_offset + pso->output[i].num_components;
 279       b = pso->output[i].output_buffer;
 280       assert(b < 4);
 281       so->num_attribs[b] = MAX2(so->num_attribs[b], end);
 282    }
 283
 284    so->ctrl = NV50_3D_STRMOUT_BUFFERS_CTRL_INTERLEAVED;
 285
 286    so->stride[0] = pso->stride[0] * 4;
 287    base[0] = 0;
 288    for (b = 1; b < 4; ++b) {
 289       assert(!so->num_attribs[b] || so->num_attribs[b] == pso->stride[b]);
 290       so->stride[b] = so->num_attribs[b] * 4;
 291       if (so->num_attribs[b])
 292          so->ctrl = (b + 1) << NV50_3D_STRMOUT_BUFFERS_CTRL_SEPARATE__SHIFT;
 293       base[b] = align(base[b - 1] + so->num_attribs[b - 1], 4);
 294    }
 295    if (so->ctrl & NV50_3D_STRMOUT_BUFFERS_CTRL_INTERLEAVED) {
 296       assert(so->stride[0] < NV50_3D_STRMOUT_BUFFERS_CTRL_STRIDE__MAX);
 297       so->ctrl |= so->stride[0] << NV50_3D_STRMOUT_BUFFERS_CTRL_STRIDE__SHIFT;
 298    }
 299
 300    so->map_size = base[3] + so->num_attribs[3];
 301
 302    for (i = 0; i < pso->num_outputs; ++i) {
 303       const unsigned s = pso->output[i].start_component;
 304       const unsigned p = pso->output[i].dst_offset;
 305       const unsigned r = pso->output[i].register_index;
 306       b = pso->output[i].output_buffer;
 307
 308       for (c = 0; c < pso->output[i].num_components; ++c)
 309          so->map[base[b] + p + c] = info->out[r].slot[s + c];
 310    }
 311
 312    return so;
 313 }
 314
 315 boolean
 316 nv50_program_translate(struct nv50_program *prog, uint16_t chipset)
 317 {
 318    struct nv50_ir_prog_info *info;
 319    int ret;
 320    const uint8_t map_undef = (prog->type == PIPE_SHADER_VERTEX) ? 0x40 : 0x80;
 321
 322    info = CALLOC_STRUCT(nv50_ir_prog_info);
 323    if (!info)
 324       return FALSE;
 325
 326    info->type = prog->type;
 327    info->target = chipset;
 328    info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
 329    info->bin.source = (void *)prog->pipe.tokens;
 330
 331    info->io.ucpCBSlot = 15;
 332    info->io.ucpBase = 0;
 333    info->io.genUserClip = prog->vp.clpd_nr;
 334
 335    info->assignSlots = nv50_program_assign_varying_slots;
 336
 337    prog->vp.bfc[0] = 0xff;
 338    prog->vp.bfc[1] = 0xff;
 339    prog->vp.edgeflag = 0xff;
 340    prog->vp.clpd[0] = map_undef;
 341    prog->vp.clpd[1] = map_undef;
 342    prog->vp.psiz = map_undef;
 343    prog->gp.primid = 0x80;
 344    prog->gp.has_layer = 0;
 345
 346    info->driverPriv = prog;
 347
 348 #ifdef DEBUG
 349    info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
 350    info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
 351 #else
 352    info->optLevel = 3;
 353 #endif
 354
 355    ret = nv50_ir_generate_code(info);
 356    if (ret) {
 357       NOUVEAU_ERR("shader translation failed: %i\n", ret);
 358       goto out;
 359    }
 360    FREE(info->bin.syms);
 361
 362    prog->code = info->bin.code;
 363    prog->code_size = info->bin.codeSize;
 364    prog->fixups = info->bin.relocData;
 365    prog->max_gpr = MAX2(4, (info->bin.maxGPR >> 1) + 1);
 366    prog->tls_space = info->bin.tlsSpace;
 367
 368    if (prog->type == PIPE_SHADER_FRAGMENT) {
 369       if (info->prop.fp.writesDepth) {
 370          prog->fp.flags[0] |= NV50_3D_FP_CONTROL_EXPORTS_Z;
 371          prog->fp.flags[1] = 0x11;
 372       }
 373       if (info->prop.fp.usesDiscard)
 374          prog->fp.flags[0] |= NV50_3D_FP_CONTROL_USES_KIL;
 375    } else
 376    if (prog->type == PIPE_SHADER_GEOMETRY) {
 377       switch (info->prop.gp.outputPrim) {
 378       case PIPE_PRIM_LINE_STRIP:
 379          prog->gp.prim_type = NV50_3D_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP;
 380          break;
 381       case PIPE_PRIM_TRIANGLE_STRIP:
 382          prog->gp.prim_type = NV50_3D_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP;
 383          break;
 384       case PIPE_PRIM_POINTS:
 385       default:
 386          assert(info->prop.gp.outputPrim == PIPE_PRIM_POINTS);
 387          prog->gp.prim_type = NV50_3D_GP_OUTPUT_PRIMITIVE_TYPE_POINTS;
 388          break;
 389       }
 390       prog->gp.vert_count = info->prop.gp.maxVertices;
 391    }
 392
 393    if (prog->pipe.stream_output.num_outputs)
 394       prog->so = nv50_program_create_strmout_state(info,
 395                                                    &prog->pipe.stream_output);
 396
 397 out:
 398    FREE(info);
 399    return !ret;
 400 }
 401
 402 boolean
 403 nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog)
 404 {
 405    struct nouveau_heap *heap;
 406    int ret;
 407    uint32_t size = align(prog->code_size, 0x40);
 408
 409    switch (prog->type) {
 410    case PIPE_SHADER_VERTEX:   heap = nv50->screen->vp_code_heap; break;
 411    case PIPE_SHADER_GEOMETRY: heap = nv50->screen->fp_code_heap; break;
 412    case PIPE_SHADER_FRAGMENT: heap = nv50->screen->gp_code_heap; break;
 413    default:
 414       assert(!"invalid program type");
 415       return FALSE;
 416    }
 417
 418    ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
 419    if (ret) {
 420       /* Out of space: evict everything to compactify the code segment, hoping
 421        * the working set is much smaller and drifts slowly. Improve me !
 422        */
 423       while (heap->next) {
 424          struct nv50_program *evict = heap->next->priv;
 425          if (evict)
 426             nouveau_heap_free(&evict->mem);
 427       }
 428       debug_printf("WARNING: out of code space, evicting all shaders.\n");
 429       ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
 430       if (ret) {
 431          NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
 432          return FALSE;
 433       }
 434    }
 435    prog->code_base = prog->mem->start;
 436
 437    ret = nv50_tls_realloc(nv50->screen, prog->tls_space);
 438    if (ret < 0) {
 439       nouveau_heap_free(&prog->mem);
 440       return FALSE;
 441    }
 442    if (ret > 0)
 443       nv50->state.new_tls_space = TRUE;
 444
 445    if (prog->fixups)
 446       nv50_ir_relocate_code(prog->fixups, prog->code, prog->code_base, 0, 0);
 447
 448    nv50_sifc_linear_u8(&nv50->base, nv50->screen->code,
 449                        (prog->type << NV50_CODE_BO_SIZE_LOG2) + prog->code_base,
 450                        NOUVEAU_BO_VRAM, prog->code_size, prog->code);
 451
 452    BEGIN_NV04(nv50->base.pushbuf, NV50_3D(CODE_CB_FLUSH), 1);
 453    PUSH_DATA (nv50->base.pushbuf, 0);
 454
 455    return TRUE;
 456 }
 457
 458 void
 459 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
 460 {
 461    const struct pipe_shader_state pipe = p->pipe;
 462    const ubyte type = p->type;
 463
 464    if (p->mem)
 465       nouveau_heap_free(&p->mem);
 466
 467    FREE(p->code);
 468
 469    FREE(p->fixups);
 470
 471    FREE(p->so);
 472
 473    memset(p, 0, sizeof(*p));
 474
 475    p->pipe = pipe;
 476    p->type = type;
 477 }