src/gallium/drivers/nouveau/nv50/nv50_program.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "nv50/nv50_program.h"
  24 #include "nv50/nv50_context.h"
  25
  26 #include "codegen/nv50_ir_driver.h"
  27
  28 static inline unsigned
  29 bitcount4(const uint32_t val)
  30 {
  31    static const uint8_t cnt[16]
  32    = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
  33    return cnt[val & 0xf];
  34 }
  35
  36 static int
  37 nv50_vertprog_assign_slots(struct nv50_ir_prog_info *info)
  38 {
  39    struct nv50_program *prog = (struct nv50_program *)info->driverPriv;
  40    unsigned i, n, c;
  41
  42    n = 0;
  43    for (i = 0; i < info->numInputs; ++i) {
  44       prog->in[i].id = i;
  45       prog->in[i].sn = info->in[i].sn;
  46       prog->in[i].si = info->in[i].si;
  47       prog->in[i].hw = n;
  48       prog->in[i].mask = info->in[i].mask;
  49
  50       prog->vp.attrs[(4 * i) / 32] |= info->in[i].mask << ((4 * i) % 32);
  51
  52       for (c = 0; c < 4; ++c)
  53          if (info->in[i].mask & (1 << c))
  54             info->in[i].slot[c] = n++;
  55
  56       if (info->in[i].sn == TGSI_SEMANTIC_PRIMID)
  57          prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_PRIMITIVE_ID;
  58    }
  59    prog->in_nr = info->numInputs;
  60
  61    for (i = 0; i < info->numSysVals; ++i) {
  62       switch (info->sv[i].sn) {
  63       case TGSI_SEMANTIC_INSTANCEID:
  64          prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_INSTANCE_ID;
  65          continue;
  66       case TGSI_SEMANTIC_VERTEXID:
  67          prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID;
  68          prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID_DRAW_ARRAYS_ADD_START;
  69          continue;
  70       default:
  71          break;
  72       }
  73    }
  74
  75    /*
  76     * Corner case: VP has no inputs, but we will still need to submit data to
  77     * draw it. HW will shout at us and won't draw anything if we don't enable
  78     * any input, so let's just pretend it's the first one.
  79     */
  80    if (prog->vp.attrs[0] == 0 &&
  81        prog->vp.attrs[1] == 0 &&
  82        prog->vp.attrs[2] == 0)
  83       prog->vp.attrs[0] |= 0xf;
  84
  85    /* VertexID before InstanceID */
  86    if (info->io.vertexId < info->numSysVals)
  87       info->sv[info->io.vertexId].slot[0] = n++;
  88    if (info->io.instanceId < info->numSysVals)
  89       info->sv[info->io.instanceId].slot[0] = n++;
  90
  91    n = 0;
  92    for (i = 0; i < info->numOutputs; ++i) {
  93       switch (info->out[i].sn) {
  94       case TGSI_SEMANTIC_PSIZE:
  95          prog->vp.psiz = i;
  96          break;
  97       case TGSI_SEMANTIC_CLIPDIST:
  98          prog->vp.clpd[info->out[i].si] = n;
  99          break;
 100       case TGSI_SEMANTIC_EDGEFLAG:
 101          prog->vp.edgeflag = i;
 102          break;
 103       case TGSI_SEMANTIC_BCOLOR:
 104          prog->vp.bfc[info->out[i].si] = i;
 105          break;
 106       case TGSI_SEMANTIC_LAYER:
 107          prog->gp.has_layer = true;
 108          prog->gp.layerid = n;
 109          break;
 110       case TGSI_SEMANTIC_VIEWPORT_INDEX:
 111          prog->gp.has_viewport = true;
 112          prog->gp.viewportid = n;
 113          break;
 114       default:
 115          break;
 116       }
 117       prog->out[i].id = i;
 118       prog->out[i].sn = info->out[i].sn;
 119       prog->out[i].si = info->out[i].si;
 120       prog->out[i].hw = n;
 121       prog->out[i].mask = info->out[i].mask;
 122
 123       for (c = 0; c < 4; ++c)
 124          if (info->out[i].mask & (1 << c))
 125             info->out[i].slot[c] = n++;
 126    }
 127    prog->out_nr = info->numOutputs;
 128    prog->max_out = n;
 129    if (!prog->max_out)
 130       prog->max_out = 1;
 131
 132    if (prog->vp.psiz < info->numOutputs)
 133       prog->vp.psiz = prog->out[prog->vp.psiz].hw;
 134
 135    return 0;
 136 }
 137
 138 static int
 139 nv50_fragprog_assign_slots(struct nv50_ir_prog_info *info)
 140 {
 141    struct nv50_program *prog = (struct nv50_program *)info->driverPriv;
 142    unsigned i, n, m, c;
 143    unsigned nvary;
 144    unsigned nflat;
 145    unsigned nintp = 0;
 146
 147    /* count recorded non-flat inputs */
 148    for (m = 0, i = 0; i < info->numInputs; ++i) {
 149       switch (info->in[i].sn) {
 150       case TGSI_SEMANTIC_POSITION:
 151       case TGSI_SEMANTIC_FACE:
 152          continue;
 153       default:
 154          m += info->in[i].flat ? 0 : 1;
 155          break;
 156       }
 157    }
 158    /* careful: id may be != i in info->in[prog->in[i].id] */
 159
 160    /* Fill prog->in[] so that non-flat inputs are first and
 161     * kick out special inputs that don't use the RESULT_MAP.
 162     */
 163    for (n = 0, i = 0; i < info->numInputs; ++i) {
 164       if (info->in[i].sn == TGSI_SEMANTIC_POSITION) {
 165          prog->fp.interp |= info->in[i].mask << 24;
 166          for (c = 0; c < 4; ++c)
 167             if (info->in[i].mask & (1 << c))
 168                info->in[i].slot[c] = nintp++;
 169       } else
 170       if (info->in[i].sn == TGSI_SEMANTIC_FACE) {
 171          info->in[i].slot[0] = 255;
 172       } else {
 173          unsigned j = info->in[i].flat ? m++ : n++;
 174
 175          if (info->in[i].sn == TGSI_SEMANTIC_COLOR)
 176             prog->vp.bfc[info->in[i].si] = j;
 177          else if (info->in[i].sn == TGSI_SEMANTIC_PRIMID)
 178             prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_PRIMITIVE_ID;
 179
 180          prog->in[j].id = i;
 181          prog->in[j].mask = info->in[i].mask;
 182          prog->in[j].sn = info->in[i].sn;
 183          prog->in[j].si = info->in[i].si;
 184          prog->in[j].linear = info->in[i].linear;
 185
 186          prog->in_nr++;
 187       }
 188    }
 189    if (!(prog->fp.interp & (8 << 24))) {
 190       ++nintp;
 191       prog->fp.interp |= 8 << 24;
 192    }
 193
 194    for (i = 0; i < prog->in_nr; ++i) {
 195       int j = prog->in[i].id;
 196
 197       prog->in[i].hw = nintp;
 198       for (c = 0; c < 4; ++c)
 199          if (prog->in[i].mask & (1 << c))
 200             info->in[j].slot[c] = nintp++;
 201    }
 202    /* (n == m) if m never increased, i.e. no flat inputs */
 203    nflat = (n < m) ? (nintp - prog->in[n].hw) : 0;
 204    nintp -= bitcount4(prog->fp.interp >> 24); /* subtract position inputs */
 205    nvary = nintp - nflat;
 206
 207    prog->fp.interp |= nvary << NV50_3D_FP_INTERPOLANT_CTRL_COUNT_NONFLAT__SHIFT;
 208    prog->fp.interp |= nintp << NV50_3D_FP_INTERPOLANT_CTRL_COUNT__SHIFT;
 209
 210    /* put front/back colors right after HPOS */
 211    prog->fp.colors = 4 << NV50_3D_SEMANTIC_COLOR_FFC0_ID__SHIFT;
 212    for (i = 0; i < 2; ++i)
 213       if (prog->vp.bfc[i] < 0xff)
 214          prog->fp.colors += bitcount4(prog->in[prog->vp.bfc[i]].mask) << 16;
 215
 216    /* FP outputs */
 217
 218    if (info->prop.fp.numColourResults > 1)
 219       prog->fp.flags[0] |= NV50_3D_FP_CONTROL_MULTIPLE_RESULTS;
 220
 221    for (i = 0; i < info->numOutputs; ++i) {
 222       prog->out[i].id = i;
 223       prog->out[i].sn = info->out[i].sn;
 224       prog->out[i].si = info->out[i].si;
 225       prog->out[i].mask = info->out[i].mask;
 226
 227       if (i == info->io.fragDepth || i == info->io.sampleMask)
 228          continue;
 229       prog->out[i].hw = info->out[i].si * 4;
 230
 231       for (c = 0; c < 4; ++c)
 232          info->out[i].slot[c] = prog->out[i].hw + c;
 233
 234       prog->max_out = MAX2(prog->max_out, prog->out[i].hw + 4);
 235    }
 236
 237    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS) {
 238       info->out[info->io.sampleMask].slot[0] = prog->max_out++;
 239       prog->fp.has_samplemask = 1;
 240    }
 241
 242    if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
 243       info->out[info->io.fragDepth].slot[2] = prog->max_out++;
 244
 245    if (!prog->max_out)
 246       prog->max_out = 4;
 247
 248    return 0;
 249 }
 250
 251 static int
 252 nv50_program_assign_varying_slots(struct nv50_ir_prog_info *info)
 253 {
 254    switch (info->type) {
 255    case PIPE_SHADER_VERTEX:
 256       return nv50_vertprog_assign_slots(info);
 257    case PIPE_SHADER_GEOMETRY:
 258       return nv50_vertprog_assign_slots(info);
 259    case PIPE_SHADER_FRAGMENT:
 260       return nv50_fragprog_assign_slots(info);
 261    case PIPE_SHADER_COMPUTE:
 262       return 0;
 263    default:
 264       return -1;
 265    }
 266 }
 267
 268 static struct nv50_stream_output_state *
 269 nv50_program_create_strmout_state(const struct nv50_ir_prog_info *info,
 270                                   const struct pipe_stream_output_info *pso)
 271 {
 272    struct nv50_stream_output_state *so;
 273    unsigned b, i, c;
 274    unsigned base[4];
 275
 276    so = MALLOC_STRUCT(nv50_stream_output_state);
 277    if (!so)
 278       return NULL;
 279    memset(so->map, 0xff, sizeof(so->map));
 280
 281    for (b = 0; b < 4; ++b)
 282       so->num_attribs[b] = 0;
 283    for (i = 0; i < pso->num_outputs; ++i) {
 284       unsigned end =  pso->output[i].dst_offset + pso->output[i].num_components;
 285       b = pso->output[i].output_buffer;
 286       assert(b < 4);
 287       so->num_attribs[b] = MAX2(so->num_attribs[b], end);
 288    }
 289
 290    so->ctrl = NV50_3D_STRMOUT_BUFFERS_CTRL_INTERLEAVED;
 291
 292    so->stride[0] = pso->stride[0] * 4;
 293    base[0] = 0;
 294    for (b = 1; b < 4; ++b) {
 295       assert(!so->num_attribs[b] || so->num_attribs[b] == pso->stride[b]);
 296       so->stride[b] = so->num_attribs[b] * 4;
 297       if (so->num_attribs[b])
 298          so->ctrl = (b + 1) << NV50_3D_STRMOUT_BUFFERS_CTRL_SEPARATE__SHIFT;
 299       base[b] = align(base[b - 1] + so->num_attribs[b - 1], 4);
 300    }
 301    if (so->ctrl & NV50_3D_STRMOUT_BUFFERS_CTRL_INTERLEAVED) {
 302       assert(so->stride[0] < NV50_3D_STRMOUT_BUFFERS_CTRL_STRIDE__MAX);
 303       so->ctrl |= so->stride[0] << NV50_3D_STRMOUT_BUFFERS_CTRL_STRIDE__SHIFT;
 304    }
 305
 306    so->map_size = base[3] + so->num_attribs[3];
 307
 308    for (i = 0; i < pso->num_outputs; ++i) {
 309       const unsigned s = pso->output[i].start_component;
 310       const unsigned p = pso->output[i].dst_offset;
 311       const unsigned r = pso->output[i].register_index;
 312       b = pso->output[i].output_buffer;
 313
 314       for (c = 0; c < pso->output[i].num_components; ++c)
 315          so->map[base[b] + p + c] = info->out[r].slot[s + c];
 316    }
 317
 318    return so;
 319 }
 320
 321 bool
 322 nv50_program_translate(struct nv50_program *prog, uint16_t chipset,
 323                        struct pipe_debug_callback *debug)
 324 {
 325    struct nv50_ir_prog_info *info;
 326    int ret;
 327    const uint8_t map_undef = (prog->type == PIPE_SHADER_VERTEX) ? 0x40 : 0x80;
 328
 329    info = CALLOC_STRUCT(nv50_ir_prog_info);
 330    if (!info)
 331       return false;
 332
 333    info->type = prog->type;
 334    info->target = chipset;
 335    info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
 336    info->bin.source = (void *)prog->pipe.tokens;
 337
 338    info->io.ucpCBSlot = 15;
 339    info->io.ucpBase = NV50_CB_AUX_UCP_OFFSET;
 340    info->io.genUserClip = prog->vp.clpd_nr;
 341
 342    info->io.resInfoCBSlot = 15;
 343    info->io.suInfoBase = NV50_CB_AUX_TEX_MS_OFFSET;
 344    info->io.sampleInfoBase = NV50_CB_AUX_SAMPLE_OFFSET;
 345    info->io.msInfoCBSlot = 15;
 346    info->io.msInfoBase = NV50_CB_AUX_MS_OFFSET;
 347
 348    info->assignSlots = nv50_program_assign_varying_slots;
 349
 350    prog->vp.bfc[0] = 0xff;
 351    prog->vp.bfc[1] = 0xff;
 352    prog->vp.edgeflag = 0xff;
 353    prog->vp.clpd[0] = map_undef;
 354    prog->vp.clpd[1] = map_undef;
 355    prog->vp.psiz = map_undef;
 356    prog->gp.has_layer = 0;
 357    prog->gp.has_viewport = 0;
 358
 359    if (prog->type == PIPE_SHADER_COMPUTE)
 360       info->prop.cp.inputOffset = 0x10;
 361
 362    info->driverPriv = prog;
 363
 364 #ifdef DEBUG
 365    info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
 366    info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
 367 #else
 368    info->optLevel = 3;
 369 #endif
 370
 371    ret = nv50_ir_generate_code(info);
 372    if (ret) {
 373       NOUVEAU_ERR("shader translation failed: %i\n", ret);
 374       goto out;
 375    }
 376    FREE(info->bin.syms);
 377
 378    prog->code = info->bin.code;
 379    prog->code_size = info->bin.codeSize;
 380    prog->fixups = info->bin.relocData;
 381    prog->interps = info->bin.interpData;
 382    prog->max_gpr = MAX2(4, (info->bin.maxGPR >> 1) + 1);
 383    prog->tls_space = info->bin.tlsSpace;
 384
 385    prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
 386
 387    if (prog->type == PIPE_SHADER_FRAGMENT) {
 388       if (info->prop.fp.writesDepth) {
 389          prog->fp.flags[0] |= NV50_3D_FP_CONTROL_EXPORTS_Z;
 390          prog->fp.flags[1] = 0x11;
 391       }
 392       if (info->prop.fp.usesDiscard)
 393          prog->fp.flags[0] |= NV50_3D_FP_CONTROL_USES_KIL;
 394    } else
 395    if (prog->type == PIPE_SHADER_GEOMETRY) {
 396       switch (info->prop.gp.outputPrim) {
 397       case PIPE_PRIM_LINE_STRIP:
 398          prog->gp.prim_type = NV50_3D_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP;
 399          break;
 400       case PIPE_PRIM_TRIANGLE_STRIP:
 401          prog->gp.prim_type = NV50_3D_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP;
 402          break;
 403       case PIPE_PRIM_POINTS:
 404       default:
 405          assert(info->prop.gp.outputPrim == PIPE_PRIM_POINTS);
 406          prog->gp.prim_type = NV50_3D_GP_OUTPUT_PRIMITIVE_TYPE_POINTS;
 407          break;
 408       }
 409       prog->gp.vert_count = info->prop.gp.maxVertices;
 410    } else
 411    if (prog->type == PIPE_SHADER_COMPUTE) {
 412       prog->cp.syms = info->bin.syms;
 413       prog->cp.num_syms = info->bin.numSyms;
 414    }
 415
 416    if (prog->pipe.stream_output.num_outputs)
 417       prog->so = nv50_program_create_strmout_state(info,
 418                                                    &prog->pipe.stream_output);
 419
 420    pipe_debug_message(debug, SHADER_INFO,
 421                       "type: %d, local: %d, gpr: %d, inst: %d, bytes: %d",
 422                       prog->type, info->bin.tlsSpace, prog->max_gpr,
 423                       info->bin.instructions, info->bin.codeSize);
 424
 425 out:
 426    FREE(info);
 427    return !ret;
 428 }
 429
 430 bool
 431 nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog)
 432 {
 433    struct nouveau_heap *heap;
 434    int ret;
 435    uint32_t size = align(prog->code_size, 0x40);
 436    uint8_t prog_type;
 437
 438    switch (prog->type) {
 439    case PIPE_SHADER_VERTEX:   heap = nv50->screen->vp_code_heap; break;
 440    case PIPE_SHADER_GEOMETRY: heap = nv50->screen->gp_code_heap; break;
 441    case PIPE_SHADER_FRAGMENT: heap = nv50->screen->fp_code_heap; break;
 442    case PIPE_SHADER_COMPUTE:  heap = nv50->screen->fp_code_heap; break;
 443    default:
 444       assert(!"invalid program type");
 445       return false;
 446    }
 447
 448    ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
 449    if (ret) {
 450       /* Out of space: evict everything to compactify the code segment, hoping
 451        * the working set is much smaller and drifts slowly. Improve me !
 452        */
 453       while (heap->next) {
 454          struct nv50_program *evict = heap->next->priv;
 455          if (evict)
 456             nouveau_heap_free(&evict->mem);
 457       }
 458       debug_printf("WARNING: out of code space, evicting all shaders.\n");
 459       ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
 460       if (ret) {
 461          NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
 462          return false;
 463       }
 464    }
 465
 466    if (prog->type == PIPE_SHADER_COMPUTE) {
 467       /* CP code must be uploaded in FP code segment. */
 468       prog_type = 1;
 469    } else {
 470       prog->code_base = prog->mem->start;
 471       prog_type = prog->type;
 472    }
 473
 474    ret = nv50_tls_realloc(nv50->screen, prog->tls_space);
 475    if (ret < 0) {
 476       nouveau_heap_free(&prog->mem);
 477       return false;
 478    }
 479    if (ret > 0)
 480       nv50->state.new_tls_space = true;
 481
 482    if (prog->fixups)
 483       nv50_ir_relocate_code(prog->fixups, prog->code, prog->code_base, 0, 0);
 484    if (prog->interps)
 485       nv50_ir_change_interp(prog->interps, prog->code,
 486                             prog->fp.force_persample_interp,
 487                             false /* flatshade */);
 488
 489    nv50_sifc_linear_u8(&nv50->base, nv50->screen->code,
 490                        (prog_type << NV50_CODE_BO_SIZE_LOG2) + prog->code_base,
 491                        NOUVEAU_BO_VRAM, prog->code_size, prog->code);
 492
 493    BEGIN_NV04(nv50->base.pushbuf, NV50_3D(CODE_CB_FLUSH), 1);
 494    PUSH_DATA (nv50->base.pushbuf, 0);
 495
 496    return true;
 497 }
 498
 499 void
 500 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
 501 {
 502    const struct pipe_shader_state pipe = p->pipe;
 503    const ubyte type = p->type;
 504
 505    if (p->mem)
 506       nouveau_heap_free(&p->mem);
 507
 508    FREE(p->code);
 509
 510    FREE(p->fixups);
 511    FREE(p->interps);
 512    FREE(p->so);
 513
 514    memset(p, 0, sizeof(*p));
 515
 516    p->pipe = pipe;
 517    p->type = type;
 518 }