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0bd5de91d1fe9504522d27a3a0b63135e4bf9b55
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <errno.h>
24 #include <xf86drm.h>
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nv_object.xml.h"
36
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
41
42 #define THREADS_IN_WARP 32
43
44 static boolean
45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
46 enum pipe_format format,
47 enum pipe_texture_target target,
48 unsigned sample_count,
49 unsigned bindings)
50 {
51 if (sample_count > 8)
52 return false;
53 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
54 return false;
55 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
56 return false;
57
58 if (!util_format_is_supported(format, bindings))
59 return false;
60
61 switch (format) {
62 case PIPE_FORMAT_Z16_UNORM:
63 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
64 return false;
65 break;
66 default:
67 break;
68 }
69
70 /* transfers & shared are always supported */
71 bindings &= ~(PIPE_BIND_TRANSFER_READ |
72 PIPE_BIND_TRANSFER_WRITE |
73 PIPE_BIND_SHARED);
74
75 return (( nv50_format_table[format].usage |
76 nv50_vertex_format[format].usage) & bindings) == bindings;
77 }
78
79 static int
80 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
81 {
82 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
83 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
84
85 switch (param) {
86 /* non-boolean caps */
87 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
88 return 14;
89 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
90 return 12;
91 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
92 return 14;
93 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
94 return 512;
95 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
96 case PIPE_CAP_MIN_TEXEL_OFFSET:
97 return -8;
98 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
99 case PIPE_CAP_MAX_TEXEL_OFFSET:
100 return 7;
101 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
102 return 128 * 1024 * 1024;
103 case PIPE_CAP_GLSL_FEATURE_LEVEL:
104 return 330;
105 case PIPE_CAP_MAX_RENDER_TARGETS:
106 return 8;
107 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
108 return 1;
109 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
110 return 4;
111 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
112 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
113 return 64;
114 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
115 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
116 return 1024;
117 case PIPE_CAP_MAX_VERTEX_STREAMS:
118 return 1;
119 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
120 return 2048;
121 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
122 return 256;
123 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
124 return 16; /* 256 for binding as RT, but that's not possible in GL */
125 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
126 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
127 case PIPE_CAP_MAX_VIEWPORTS:
128 return NV50_MAX_VIEWPORTS;
129 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
130 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
131 case PIPE_CAP_ENDIANNESS:
132 return PIPE_ENDIAN_LITTLE;
133 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
134 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
135
136 /* supported caps */
137 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
138 case PIPE_CAP_TEXTURE_SWIZZLE:
139 case PIPE_CAP_TEXTURE_SHADOW_MAP:
140 case PIPE_CAP_NPOT_TEXTURES:
141 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
142 case PIPE_CAP_ANISOTROPIC_FILTER:
143 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
144 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
145 case PIPE_CAP_TWO_SIDED_STENCIL:
146 case PIPE_CAP_DEPTH_CLIP_DISABLE:
147 case PIPE_CAP_POINT_SPRITE:
148 case PIPE_CAP_SM3:
149 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
150 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
151 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
152 case PIPE_CAP_QUERY_TIMESTAMP:
153 case PIPE_CAP_QUERY_TIME_ELAPSED:
154 case PIPE_CAP_OCCLUSION_QUERY:
155 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
156 case PIPE_CAP_INDEP_BLEND_ENABLE:
157 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
158 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
159 case PIPE_CAP_PRIMITIVE_RESTART:
160 case PIPE_CAP_TGSI_INSTANCEID:
161 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
162 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
163 case PIPE_CAP_CONDITIONAL_RENDER:
164 case PIPE_CAP_TEXTURE_BARRIER:
165 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
166 case PIPE_CAP_START_INSTANCE:
167 case PIPE_CAP_USER_CONSTANT_BUFFERS:
168 case PIPE_CAP_USER_INDEX_BUFFERS:
169 case PIPE_CAP_USER_VERTEX_BUFFERS:
170 case PIPE_CAP_TEXTURE_MULTISAMPLE:
171 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
172 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
173 case PIPE_CAP_SAMPLER_VIEW_TARGET:
174 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
175 case PIPE_CAP_CLIP_HALFZ:
176 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
177 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
178 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
179 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
180 case PIPE_CAP_DEPTH_BOUNDS_TEST:
181 case PIPE_CAP_TGSI_TXQS:
182 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
183 case PIPE_CAP_SHAREABLE_SHADERS:
184 case PIPE_CAP_CLEAR_TEXTURE:
185 case PIPE_CAP_COMPUTE:
186 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
187 return 1;
188 case PIPE_CAP_SEAMLESS_CUBE_MAP:
189 return 1; /* class_3d >= NVA0_3D_CLASS; */
190 /* supported on nva0+ */
191 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
192 return class_3d >= NVA0_3D_CLASS;
193 /* supported on nva3+ */
194 case PIPE_CAP_CUBE_MAP_ARRAY:
195 case PIPE_CAP_INDEP_BLEND_FUNC:
196 case PIPE_CAP_TEXTURE_QUERY_LOD:
197 case PIPE_CAP_SAMPLE_SHADING:
198 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
199 return class_3d >= NVA3_3D_CLASS;
200
201 /* unsupported caps */
202 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
203 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
204 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
205 case PIPE_CAP_SHADER_STENCIL_EXPORT:
206 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
207 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
208 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
209 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
210 case PIPE_CAP_TGSI_TEXCOORD:
211 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
212 case PIPE_CAP_TEXTURE_GATHER_SM5:
213 case PIPE_CAP_FAKE_SW_MSAA:
214 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
215 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
216 case PIPE_CAP_DRAW_INDIRECT:
217 case PIPE_CAP_MULTI_DRAW_INDIRECT:
218 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
219 case PIPE_CAP_VERTEXID_NOBASE:
220 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
221 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
222 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
223 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
224 case PIPE_CAP_DRAW_PARAMETERS:
225 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
226 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
227 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
228 case PIPE_CAP_INVALIDATE_BUFFER:
229 case PIPE_CAP_GENERATE_MIPMAP:
230 case PIPE_CAP_STRING_MARKER:
231 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
232 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
233 case PIPE_CAP_QUERY_BUFFER_OBJECT:
234 case PIPE_CAP_QUERY_MEMORY_INFO:
235 return 0;
236
237 case PIPE_CAP_VENDOR_ID:
238 return 0x10de;
239 case PIPE_CAP_DEVICE_ID: {
240 uint64_t device_id;
241 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
242 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
243 return -1;
244 }
245 return device_id;
246 }
247 case PIPE_CAP_ACCELERATED:
248 return 1;
249 case PIPE_CAP_VIDEO_MEMORY:
250 return dev->vram_size >> 20;
251 case PIPE_CAP_UMA:
252 return 0;
253 }
254
255 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
256 return 0;
257 }
258
259 static int
260 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
261 enum pipe_shader_cap param)
262 {
263 switch (shader) {
264 case PIPE_SHADER_VERTEX:
265 case PIPE_SHADER_GEOMETRY:
266 case PIPE_SHADER_FRAGMENT:
267 break;
268 case PIPE_SHADER_COMPUTE:
269 default:
270 return 0;
271 }
272
273 switch (param) {
274 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
275 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
276 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
277 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
278 return 16384;
279 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
280 return 4;
281 case PIPE_SHADER_CAP_MAX_INPUTS:
282 if (shader == PIPE_SHADER_VERTEX)
283 return 32;
284 return 15;
285 case PIPE_SHADER_CAP_MAX_OUTPUTS:
286 return 16;
287 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
288 return 65536;
289 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
290 return NV50_MAX_PIPE_CONSTBUFS;
291 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
292 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
293 return shader != PIPE_SHADER_FRAGMENT;
294 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
295 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
296 return 1;
297 case PIPE_SHADER_CAP_MAX_PREDS:
298 return 0;
299 case PIPE_SHADER_CAP_MAX_TEMPS:
300 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
301 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
302 return 1;
303 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
304 return 0;
305 case PIPE_SHADER_CAP_SUBROUTINES:
306 return 0; /* please inline, or provide function declarations */
307 case PIPE_SHADER_CAP_INTEGERS:
308 return 1;
309 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
310 /* The chip could handle more sampler views than samplers */
311 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
312 return MIN2(16, PIPE_MAX_SAMPLERS);
313 case PIPE_SHADER_CAP_DOUBLES:
314 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
315 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
316 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
317 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
318 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
319 case PIPE_SHADER_CAP_SUPPORTED_IRS:
320 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
321 return 0;
322 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
323 return 32;
324 default:
325 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
326 return 0;
327 }
328 }
329
330 static float
331 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
332 {
333 switch (param) {
334 case PIPE_CAPF_MAX_LINE_WIDTH:
335 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
336 return 10.0f;
337 case PIPE_CAPF_MAX_POINT_WIDTH:
338 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
339 return 64.0f;
340 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
341 return 16.0f;
342 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
343 return 4.0f;
344 case PIPE_CAPF_GUARD_BAND_LEFT:
345 case PIPE_CAPF_GUARD_BAND_TOP:
346 return 0.0f;
347 case PIPE_CAPF_GUARD_BAND_RIGHT:
348 case PIPE_CAPF_GUARD_BAND_BOTTOM:
349 return 0.0f; /* that or infinity */
350 }
351
352 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
353 return 0.0f;
354 }
355
356 static int
357 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
358 enum pipe_compute_cap param, void *data)
359 {
360 struct nv50_screen *screen = nv50_screen(pscreen);
361
362 #define RET(x) do { \
363 if (data) \
364 memcpy(data, x, sizeof(x)); \
365 return sizeof(x); \
366 } while (0)
367
368 switch (param) {
369 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
370 RET((uint64_t []) { 2 });
371 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
372 RET(((uint64_t []) { 65535, 65535 }));
373 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
374 RET(((uint64_t []) { 512, 512, 64 }));
375 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
376 RET((uint64_t []) { 512 });
377 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
378 RET((uint64_t []) { 1ULL << 32 });
379 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
380 RET((uint64_t []) { 16 << 10 });
381 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
382 RET((uint64_t []) { 16 << 10 });
383 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
384 RET((uint64_t []) { 4096 });
385 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
386 RET((uint32_t []) { 32 });
387 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
388 RET((uint64_t []) { 1ULL << 40 });
389 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
390 RET((uint32_t []) { 0 });
391 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
392 RET((uint32_t []) { screen->mp_count });
393 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
394 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
395 default:
396 return 0;
397 }
398
399 #undef RET
400 }
401
402 static void
403 nv50_screen_destroy(struct pipe_screen *pscreen)
404 {
405 struct nv50_screen *screen = nv50_screen(pscreen);
406
407 if (!nouveau_drm_screen_unref(&screen->base))
408 return;
409
410 if (screen->base.fence.current) {
411 struct nouveau_fence *current = NULL;
412
413 /* nouveau_fence_wait will create a new current fence, so wait on the
414 * _current_ one, and remove both.
415 */
416 nouveau_fence_ref(screen->base.fence.current, &current);
417 nouveau_fence_wait(current, NULL);
418 nouveau_fence_ref(NULL, &current);
419 nouveau_fence_ref(NULL, &screen->base.fence.current);
420 }
421 if (screen->base.pushbuf)
422 screen->base.pushbuf->user_priv = NULL;
423
424 if (screen->blitter)
425 nv50_blitter_destroy(screen);
426 if (screen->pm.prog) {
427 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
428 nv50_program_destroy(NULL, screen->pm.prog);
429 FREE(screen->pm.prog);
430 }
431
432 nouveau_bo_ref(NULL, &screen->code);
433 nouveau_bo_ref(NULL, &screen->tls_bo);
434 nouveau_bo_ref(NULL, &screen->stack_bo);
435 nouveau_bo_ref(NULL, &screen->txc);
436 nouveau_bo_ref(NULL, &screen->uniforms);
437 nouveau_bo_ref(NULL, &screen->fence.bo);
438
439 nouveau_heap_destroy(&screen->vp_code_heap);
440 nouveau_heap_destroy(&screen->gp_code_heap);
441 nouveau_heap_destroy(&screen->fp_code_heap);
442
443 FREE(screen->tic.entries);
444
445 nouveau_object_del(&screen->tesla);
446 nouveau_object_del(&screen->eng2d);
447 nouveau_object_del(&screen->m2mf);
448 nouveau_object_del(&screen->compute);
449 nouveau_object_del(&screen->sync);
450
451 nouveau_screen_fini(&screen->base);
452
453 FREE(screen);
454 }
455
456 static void
457 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
458 {
459 struct nv50_screen *screen = nv50_screen(pscreen);
460 struct nouveau_pushbuf *push = screen->base.pushbuf;
461
462 /* we need to do it after possible flush in MARK_RING */
463 *sequence = ++screen->base.fence.sequence;
464
465 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
466 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
467 PUSH_DATAh(push, screen->fence.bo->offset);
468 PUSH_DATA (push, screen->fence.bo->offset);
469 PUSH_DATA (push, *sequence);
470 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
471 NV50_3D_QUERY_GET_UNK4 |
472 NV50_3D_QUERY_GET_UNIT_CROP |
473 NV50_3D_QUERY_GET_TYPE_QUERY |
474 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
475 NV50_3D_QUERY_GET_SHORT);
476 }
477
478 static u32
479 nv50_screen_fence_update(struct pipe_screen *pscreen)
480 {
481 return nv50_screen(pscreen)->fence.map[0];
482 }
483
484 static void
485 nv50_screen_init_hwctx(struct nv50_screen *screen)
486 {
487 struct nouveau_pushbuf *push = screen->base.pushbuf;
488 struct nv04_fifo *fifo;
489 unsigned i;
490
491 fifo = (struct nv04_fifo *)screen->base.channel->data;
492
493 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
494 PUSH_DATA (push, screen->m2mf->handle);
495 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
496 PUSH_DATA (push, screen->sync->handle);
497 PUSH_DATA (push, fifo->vram);
498 PUSH_DATA (push, fifo->vram);
499
500 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
501 PUSH_DATA (push, screen->eng2d->handle);
502 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
503 PUSH_DATA (push, screen->sync->handle);
504 PUSH_DATA (push, fifo->vram);
505 PUSH_DATA (push, fifo->vram);
506 PUSH_DATA (push, fifo->vram);
507 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
508 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
509 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
510 PUSH_DATA (push, 0);
511 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
512 PUSH_DATA (push, 0);
513 BEGIN_NV04(push, SUBC_2D(0x0888), 1);
514 PUSH_DATA (push, 1);
515 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
516 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
517
518 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
519 PUSH_DATA (push, screen->tesla->handle);
520
521 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
522 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
523
524 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
525 PUSH_DATA (push, screen->sync->handle);
526 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
527 for (i = 0; i < 11; ++i)
528 PUSH_DATA(push, fifo->vram);
529 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
530 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
531 PUSH_DATA(push, fifo->vram);
532
533 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
534 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
535 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
536 PUSH_DATA (push, 0xf);
537
538 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
539 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
540 PUSH_DATA (push, 0x18);
541 }
542
543 BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
544 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
545
546 BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
547 for (i = 0; i < 8; ++i)
548 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
549
550 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
551 PUSH_DATA (push, 1);
552
553 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
554 PUSH_DATA (push, 0);
555 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
556 PUSH_DATA (push, 0);
557 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
558 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
559 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
560 PUSH_DATA (push, 0);
561 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
562 PUSH_DATA (push, 1);
563 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
564 PUSH_DATA (push, 1);
565
566 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
567 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
568 PUSH_DATA (push, 0);
569 }
570
571 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
572 PUSH_DATA (push, 0);
573 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
574 PUSH_DATA (push, 0);
575 PUSH_DATA (push, 0);
576 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
577 PUSH_DATA (push, 0x3f);
578
579 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
580 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
581 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
582
583 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
584 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
585 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
586
587 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
588 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
589 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
590
591 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
592 PUSH_DATAh(push, screen->tls_bo->offset);
593 PUSH_DATA (push, screen->tls_bo->offset);
594 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
595
596 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
597 PUSH_DATAh(push, screen->stack_bo->offset);
598 PUSH_DATA (push, screen->stack_bo->offset);
599 PUSH_DATA (push, 4);
600
601 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
602 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
603 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
604 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
605
606 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
607 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
608 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
609 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
610
611 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
612 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
613 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
614 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
615
616 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
617 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
618 PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
619 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
620
621 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
622 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
623 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
624 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
625
626 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
627 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
628 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
629 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
630 PUSH_DATAf(push, 0.0f);
631 PUSH_DATAf(push, 0.0f);
632 PUSH_DATAf(push, 0.0f);
633 PUSH_DATAf(push, 0.0f);
634 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
635 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
636 PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
637
638 nv50_upload_ms_info(push);
639
640 /* max TIC (bits 4:8) & TSC bindings, per program type */
641 for (i = 0; i < 3; ++i) {
642 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
643 PUSH_DATA (push, 0x54);
644 }
645
646 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
647 PUSH_DATAh(push, screen->txc->offset);
648 PUSH_DATA (push, screen->txc->offset);
649 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
650
651 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
652 PUSH_DATAh(push, screen->txc->offset + 65536);
653 PUSH_DATA (push, screen->txc->offset + 65536);
654 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
655
656 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
657 PUSH_DATA (push, 0);
658
659 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
660 PUSH_DATA (push, 0);
661 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
662 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
663 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
664 for (i = 0; i < 8 * 2; ++i)
665 PUSH_DATA(push, 0);
666 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
667 PUSH_DATA (push, 0);
668
669 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
670 PUSH_DATA (push, 1);
671 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
672 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
673 PUSH_DATAf(push, 0.0f);
674 PUSH_DATAf(push, 1.0f);
675 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
676 PUSH_DATA (push, 8192 << 16);
677 PUSH_DATA (push, 8192 << 16);
678 }
679
680 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
681 #ifdef NV50_SCISSORS_CLIPPING
682 PUSH_DATA (push, 0x0000);
683 #else
684 PUSH_DATA (push, 0x1080);
685 #endif
686
687 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
688 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
689
690 /* We use scissors instead of exact view volume clipping,
691 * so they're always enabled.
692 */
693 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
694 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
695 PUSH_DATA (push, 1);
696 PUSH_DATA (push, 8192 << 16);
697 PUSH_DATA (push, 8192 << 16);
698 }
699
700 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
701 PUSH_DATA (push, 1);
702 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
703 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
704 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
705 PUSH_DATA (push, 0x11111111);
706 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
707 PUSH_DATA (push, 1);
708
709 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
710 PUSH_DATA (push, 0);
711 if (screen->base.class_3d >= NV84_3D_CLASS) {
712 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
713 PUSH_DATA (push, 0);
714 }
715
716 PUSH_KICK (push);
717 }
718
719 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
720 uint64_t *tls_size)
721 {
722 struct nouveau_device *dev = screen->base.device;
723 int ret;
724
725 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
726 ONE_TEMP_SIZE;
727 if (nouveau_mesa_debug)
728 debug_printf("allocating space for %u temps\n",
729 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
730 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
731 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
732
733 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
734 *tls_size, NULL, &screen->tls_bo);
735 if (ret) {
736 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
737 return ret;
738 }
739
740 return 0;
741 }
742
743 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
744 {
745 struct nouveau_pushbuf *push = screen->base.pushbuf;
746 int ret;
747 uint64_t tls_size;
748
749 if (tls_space < screen->cur_tls_space)
750 return 0;
751 if (tls_space > screen->max_tls_space) {
752 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
753 * LOCAL_WARPS_NO_CLAMP) */
754 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
755 (unsigned)(tls_space / ONE_TEMP_SIZE),
756 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
757 return -ENOMEM;
758 }
759
760 nouveau_bo_ref(NULL, &screen->tls_bo);
761 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
762 if (ret)
763 return ret;
764
765 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
766 PUSH_DATAh(push, screen->tls_bo->offset);
767 PUSH_DATA (push, screen->tls_bo->offset);
768 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
769
770 return 1;
771 }
772
773 struct nouveau_screen *
774 nv50_screen_create(struct nouveau_device *dev)
775 {
776 struct nv50_screen *screen;
777 struct pipe_screen *pscreen;
778 struct nouveau_object *chan;
779 uint64_t value;
780 uint32_t tesla_class;
781 unsigned stack_size;
782 int ret;
783
784 screen = CALLOC_STRUCT(nv50_screen);
785 if (!screen)
786 return NULL;
787 pscreen = &screen->base.base;
788 pscreen->destroy = nv50_screen_destroy;
789
790 ret = nouveau_screen_init(&screen->base, dev);
791 if (ret) {
792 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
793 goto fail;
794 }
795
796 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
797 * admit them to VRAM.
798 */
799 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
800 PIPE_BIND_VERTEX_BUFFER;
801 screen->base.sysmem_bindings |=
802 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
803
804 screen->base.pushbuf->user_priv = screen;
805 screen->base.pushbuf->rsvd_kick = 5;
806
807 chan = screen->base.channel;
808
809 pscreen->context_create = nv50_create;
810 pscreen->is_format_supported = nv50_screen_is_format_supported;
811 pscreen->get_param = nv50_screen_get_param;
812 pscreen->get_shader_param = nv50_screen_get_shader_param;
813 pscreen->get_paramf = nv50_screen_get_paramf;
814 pscreen->get_compute_param = nv50_screen_get_compute_param;
815 pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
816 pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
817
818 nv50_screen_init_resource_functions(pscreen);
819
820 if (screen->base.device->chipset < 0x84 ||
821 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
822 /* PMPEG */
823 nouveau_screen_init_vdec(&screen->base);
824 } else if (screen->base.device->chipset < 0x98 ||
825 screen->base.device->chipset == 0xa0) {
826 /* VP2 */
827 screen->base.base.get_video_param = nv84_screen_get_video_param;
828 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
829 } else {
830 /* VP3/4 */
831 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
832 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
833 }
834
835 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
836 NULL, &screen->fence.bo);
837 if (ret) {
838 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
839 goto fail;
840 }
841
842 nouveau_bo_map(screen->fence.bo, 0, NULL);
843 screen->fence.map = screen->fence.bo->map;
844 screen->base.fence.emit = nv50_screen_fence_emit;
845 screen->base.fence.update = nv50_screen_fence_update;
846
847 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
848 &(struct nv04_notify){ .length = 32 },
849 sizeof(struct nv04_notify), &screen->sync);
850 if (ret) {
851 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
852 goto fail;
853 }
854
855 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
856 NULL, 0, &screen->m2mf);
857 if (ret) {
858 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
859 goto fail;
860 }
861
862 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
863 NULL, 0, &screen->eng2d);
864 if (ret) {
865 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
866 goto fail;
867 }
868
869 switch (dev->chipset & 0xf0) {
870 case 0x50:
871 tesla_class = NV50_3D_CLASS;
872 break;
873 case 0x80:
874 case 0x90:
875 tesla_class = NV84_3D_CLASS;
876 break;
877 case 0xa0:
878 switch (dev->chipset) {
879 case 0xa0:
880 case 0xaa:
881 case 0xac:
882 tesla_class = NVA0_3D_CLASS;
883 break;
884 case 0xaf:
885 tesla_class = NVAF_3D_CLASS;
886 break;
887 default:
888 tesla_class = NVA3_3D_CLASS;
889 break;
890 }
891 break;
892 default:
893 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
894 goto fail;
895 }
896 screen->base.class_3d = tesla_class;
897
898 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
899 NULL, 0, &screen->tesla);
900 if (ret) {
901 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
902 goto fail;
903 }
904
905 /* This over-allocates by a page. The GP, which would execute at the end of
906 * the last page, would trigger faults. The going theory is that it
907 * prefetches up to a certain amount.
908 */
909 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
910 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
911 NULL, &screen->code);
912 if (ret) {
913 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
914 goto fail;
915 }
916
917 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
918 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
919 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
920
921 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
922
923 screen->TPs = util_bitcount(value & 0xffff);
924 screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
925
926 screen->mp_count = screen->TPs * screen->MPsInTP;
927
928 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
929 STACK_WARPS_ALLOC * 64 * 8;
930
931 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
932 &screen->stack_bo);
933 if (ret) {
934 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
935 goto fail;
936 }
937
938 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
939 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
940 ONE_TEMP_SIZE;
941 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
942 screen->max_tls_space /= 2; /* half of vram */
943
944 /* hw can address max 64 KiB */
945 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
946
947 uint64_t tls_size;
948 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
949 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
950 if (ret)
951 goto fail;
952
953 if (nouveau_mesa_debug)
954 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
955 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
956
957 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
958 &screen->uniforms);
959 if (ret) {
960 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
961 goto fail;
962 }
963
964 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
965 &screen->txc);
966 if (ret) {
967 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
968 goto fail;
969 }
970
971 screen->tic.entries = CALLOC(4096, sizeof(void *));
972 screen->tsc.entries = screen->tic.entries + 2048;
973
974 if (!nv50_blitter_create(screen))
975 goto fail;
976
977 nv50_screen_init_hwctx(screen);
978
979 ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
980 if (ret) {
981 NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
982 goto fail;
983 }
984
985 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
986
987 return &screen->base;
988
989 fail:
990 screen->base.base.context_create = NULL;
991 return &screen->base;
992 }
993
994 int
995 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
996 {
997 int i = screen->tic.next;
998
999 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1000 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1001
1002 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1003
1004 if (screen->tic.entries[i])
1005 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1006
1007 screen->tic.entries[i] = entry;
1008 return i;
1009 }
1010
1011 int
1012 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1013 {
1014 int i = screen->tsc.next;
1015
1016 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1017 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1018
1019 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1020
1021 if (screen->tsc.entries[i])
1022 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1023
1024 screen->tsc.entries[i] = entry;
1025 return i;
1026 }