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[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "nv50/nv50_context.h"
28 #include "nv50/nv50_screen.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nv_object.xml.h"
33 #include <errno.h>
34
35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
37 #endif
38
39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
40 #define LOCAL_WARPS_ALLOC 32
41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
42 #define STACK_WARPS_ALLOC 32
43
44 #define THREADS_IN_WARP 32
45
46 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
47
48 static boolean
49 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
50 enum pipe_format format,
51 enum pipe_texture_target target,
52 unsigned sample_count,
53 unsigned bindings)
54 {
55 if (sample_count > 8)
56 return FALSE;
57 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
58 return FALSE;
59 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
60 return FALSE;
61
62 if (!util_format_is_supported(format, bindings))
63 return FALSE;
64
65 switch (format) {
66 case PIPE_FORMAT_Z16_UNORM:
67 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
68 return FALSE;
69 break;
70 default:
71 break;
72 }
73
74 /* transfers & shared are always supported */
75 bindings &= ~(PIPE_BIND_TRANSFER_READ |
76 PIPE_BIND_TRANSFER_WRITE |
77 PIPE_BIND_SHARED);
78
79 return (nv50_format_table[format].usage & bindings) == bindings;
80 }
81
82 static int
83 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
84 {
85 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
86
87 switch (param) {
88 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
89 return 14;
90 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
91 return 12;
92 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
93 return 14;
94 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
95 return 512;
96 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
97 case PIPE_CAP_MIN_TEXEL_OFFSET:
98 return -8;
99 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
100 case PIPE_CAP_MAX_TEXEL_OFFSET:
101 return 7;
102 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
103 case PIPE_CAP_TEXTURE_SWIZZLE:
104 case PIPE_CAP_TEXTURE_SHADOW_MAP:
105 case PIPE_CAP_NPOT_TEXTURES:
106 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
107 case PIPE_CAP_ANISOTROPIC_FILTER:
108 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
109 return 1;
110 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
111 return 65536;
112 case PIPE_CAP_SEAMLESS_CUBE_MAP:
113 return 1; /* nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS; */
114 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
115 return 0;
116 case PIPE_CAP_CUBE_MAP_ARRAY:
117 return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
118 case PIPE_CAP_TWO_SIDED_STENCIL:
119 case PIPE_CAP_DEPTH_CLIP_DISABLE:
120 case PIPE_CAP_POINT_SPRITE:
121 return 1;
122 case PIPE_CAP_SM3:
123 return 1;
124 case PIPE_CAP_GLSL_FEATURE_LEVEL:
125 return 330;
126 case PIPE_CAP_MAX_RENDER_TARGETS:
127 return 8;
128 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
129 return 1;
130 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
131 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
132 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
133 return 1;
134 case PIPE_CAP_QUERY_TIMESTAMP:
135 case PIPE_CAP_QUERY_TIME_ELAPSED:
136 case PIPE_CAP_OCCLUSION_QUERY:
137 return 1;
138 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
139 return 4;
140 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
141 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
142 return 64;
143 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
144 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
145 return 1024;
146 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
147 return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
148 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
149 case PIPE_CAP_INDEP_BLEND_ENABLE:
150 return 1;
151 case PIPE_CAP_INDEP_BLEND_FUNC:
152 return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
153 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
154 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
155 return 1;
156 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
157 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
158 return 0;
159 case PIPE_CAP_SHADER_STENCIL_EXPORT:
160 return 0;
161 case PIPE_CAP_PRIMITIVE_RESTART:
162 case PIPE_CAP_TGSI_INSTANCEID:
163 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
164 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
165 case PIPE_CAP_CONDITIONAL_RENDER:
166 case PIPE_CAP_TEXTURE_BARRIER:
167 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
168 case PIPE_CAP_START_INSTANCE:
169 return 1;
170 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
171 return 0; /* state trackers will know better */
172 case PIPE_CAP_USER_CONSTANT_BUFFERS:
173 case PIPE_CAP_USER_INDEX_BUFFERS:
174 case PIPE_CAP_USER_VERTEX_BUFFERS:
175 return 1;
176 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
177 return 256;
178 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
179 return 1; /* 256 for binding as RT, but that's not possible in GL */
180 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
181 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
182 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
183 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
184 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
185 case PIPE_CAP_TGSI_TEXCOORD:
186 return 0;
187 case PIPE_CAP_TEXTURE_MULTISAMPLE:
188 return 1;
189 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
190 return 1;
191 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
192 return 0;
193 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
194 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
195 case PIPE_CAP_ENDIANNESS:
196 return PIPE_ENDIAN_LITTLE;
197 case PIPE_CAP_TGSI_VS_LAYER:
198 case PIPE_CAP_TEXTURE_GATHER_SM5:
199 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
200 case PIPE_CAP_FAKE_SW_MSAA:
201 case PIPE_CAP_SAMPLE_SHADING:
202 return 0;
203 case PIPE_CAP_MAX_VIEWPORTS:
204 return NV50_MAX_VIEWPORTS;
205 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
206 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
207 case PIPE_CAP_TEXTURE_QUERY_LOD:
208 return class_3d >= NVA3_3D_CLASS;
209 default:
210 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
211 return 0;
212 }
213 }
214
215 static int
216 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
217 enum pipe_shader_cap param)
218 {
219 switch (shader) {
220 case PIPE_SHADER_VERTEX:
221 case PIPE_SHADER_GEOMETRY:
222 case PIPE_SHADER_FRAGMENT:
223 break;
224 default:
225 return 0;
226 }
227
228 switch (param) {
229 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
230 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
231 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
232 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
233 return 16384;
234 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
235 return 4;
236 case PIPE_SHADER_CAP_MAX_INPUTS:
237 if (shader == PIPE_SHADER_VERTEX)
238 return 32;
239 return 15;
240 case PIPE_SHADER_CAP_MAX_CONSTS:
241 return 65536 / 16;
242 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
243 return NV50_MAX_PIPE_CONSTBUFS;
244 case PIPE_SHADER_CAP_MAX_ADDRS:
245 return 1;
246 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
247 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
248 return shader != PIPE_SHADER_FRAGMENT;
249 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
250 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
251 return 1;
252 case PIPE_SHADER_CAP_MAX_PREDS:
253 return 0;
254 case PIPE_SHADER_CAP_MAX_TEMPS:
255 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
256 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
257 return 1;
258 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
259 return 0;
260 case PIPE_SHADER_CAP_SUBROUTINES:
261 return 0; /* please inline, or provide function declarations */
262 case PIPE_SHADER_CAP_INTEGERS:
263 return 1;
264 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
265 /* The chip could handle more sampler views than samplers */
266 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
267 return MIN2(32, PIPE_MAX_SAMPLERS);
268 default:
269 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
270 return 0;
271 }
272 }
273
274 static float
275 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
276 {
277 switch (param) {
278 case PIPE_CAPF_MAX_LINE_WIDTH:
279 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
280 return 10.0f;
281 case PIPE_CAPF_MAX_POINT_WIDTH:
282 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
283 return 64.0f;
284 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
285 return 16.0f;
286 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
287 return 4.0f;
288 default:
289 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
290 return 0.0f;
291 }
292 }
293
294 static void
295 nv50_screen_destroy(struct pipe_screen *pscreen)
296 {
297 struct nv50_screen *screen = nv50_screen(pscreen);
298
299 if (!nouveau_drm_screen_unref(&screen->base))
300 return;
301
302 if (screen->base.fence.current) {
303 struct nouveau_fence *current = NULL;
304
305 /* nouveau_fence_wait will create a new current fence, so wait on the
306 * _current_ one, and remove both.
307 */
308 nouveau_fence_ref(screen->base.fence.current, &current);
309 nouveau_fence_wait(current);
310 nouveau_fence_ref(NULL, &current);
311 nouveau_fence_ref(NULL, &screen->base.fence.current);
312 }
313 if (screen->base.pushbuf)
314 screen->base.pushbuf->user_priv = NULL;
315
316 if (screen->blitter)
317 nv50_blitter_destroy(screen);
318
319 nouveau_bo_ref(NULL, &screen->code);
320 nouveau_bo_ref(NULL, &screen->tls_bo);
321 nouveau_bo_ref(NULL, &screen->stack_bo);
322 nouveau_bo_ref(NULL, &screen->txc);
323 nouveau_bo_ref(NULL, &screen->uniforms);
324 nouveau_bo_ref(NULL, &screen->fence.bo);
325
326 nouveau_heap_destroy(&screen->vp_code_heap);
327 nouveau_heap_destroy(&screen->gp_code_heap);
328 nouveau_heap_destroy(&screen->fp_code_heap);
329
330 FREE(screen->tic.entries);
331
332 nouveau_object_del(&screen->tesla);
333 nouveau_object_del(&screen->eng2d);
334 nouveau_object_del(&screen->m2mf);
335 nouveau_object_del(&screen->sync);
336
337 nouveau_screen_fini(&screen->base);
338
339 FREE(screen);
340 }
341
342 static void
343 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
344 {
345 struct nv50_screen *screen = nv50_screen(pscreen);
346 struct nouveau_pushbuf *push = screen->base.pushbuf;
347
348 /* we need to do it after possible flush in MARK_RING */
349 *sequence = ++screen->base.fence.sequence;
350
351 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
352 PUSH_DATAh(push, screen->fence.bo->offset);
353 PUSH_DATA (push, screen->fence.bo->offset);
354 PUSH_DATA (push, *sequence);
355 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
356 NV50_3D_QUERY_GET_UNK4 |
357 NV50_3D_QUERY_GET_UNIT_CROP |
358 NV50_3D_QUERY_GET_TYPE_QUERY |
359 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
360 NV50_3D_QUERY_GET_SHORT);
361 }
362
363 static u32
364 nv50_screen_fence_update(struct pipe_screen *pscreen)
365 {
366 return nv50_screen(pscreen)->fence.map[0];
367 }
368
369 static void
370 nv50_screen_init_hwctx(struct nv50_screen *screen)
371 {
372 struct nouveau_pushbuf *push = screen->base.pushbuf;
373 struct nv04_fifo *fifo;
374 unsigned i;
375
376 fifo = (struct nv04_fifo *)screen->base.channel->data;
377
378 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
379 PUSH_DATA (push, screen->m2mf->handle);
380 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
381 PUSH_DATA (push, screen->sync->handle);
382 PUSH_DATA (push, fifo->vram);
383 PUSH_DATA (push, fifo->vram);
384
385 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
386 PUSH_DATA (push, screen->eng2d->handle);
387 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
388 PUSH_DATA (push, screen->sync->handle);
389 PUSH_DATA (push, fifo->vram);
390 PUSH_DATA (push, fifo->vram);
391 PUSH_DATA (push, fifo->vram);
392 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
393 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
394 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
395 PUSH_DATA (push, 0);
396 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
397 PUSH_DATA (push, 0);
398 BEGIN_NV04(push, SUBC_2D(0x0888), 1);
399 PUSH_DATA (push, 1);
400
401 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
402 PUSH_DATA (push, screen->tesla->handle);
403
404 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
405 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
406
407 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
408 PUSH_DATA (push, screen->sync->handle);
409 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
410 for (i = 0; i < 11; ++i)
411 PUSH_DATA(push, fifo->vram);
412 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
413 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
414 PUSH_DATA(push, fifo->vram);
415
416 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
417 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
418 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
419 PUSH_DATA (push, 0xf);
420
421 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
422 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
423 PUSH_DATA (push, 0x18);
424 }
425
426 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
427 PUSH_DATA (push, 1);
428
429 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
430 PUSH_DATA (push, 0);
431 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
432 PUSH_DATA (push, 0);
433 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
434 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
435 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
436 PUSH_DATA (push, 0);
437 BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
438 PUSH_DATA (push, 0);
439 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
440 PUSH_DATA (push, 1);
441
442 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
443 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
444 PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
445 }
446
447 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
448 PUSH_DATA (push, 0);
449 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
450 PUSH_DATA (push, 0);
451 PUSH_DATA (push, 0);
452 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
453 PUSH_DATA (push, 0x3f);
454
455 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
456 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
457 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
458
459 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
460 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
461 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
462
463 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
464 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
465 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
466
467 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
468 PUSH_DATAh(push, screen->tls_bo->offset);
469 PUSH_DATA (push, screen->tls_bo->offset);
470 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
471
472 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
473 PUSH_DATAh(push, screen->stack_bo->offset);
474 PUSH_DATA (push, screen->stack_bo->offset);
475 PUSH_DATA (push, 4);
476
477 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
478 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
479 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
480 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
481
482 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
483 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
484 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
485 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
486
487 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
488 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
489 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
490 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
491
492 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
493 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
494 PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
495 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
496
497 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
498 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
499 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
500 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
501
502 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
503 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
504 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
505 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
506 PUSH_DATAf(push, 0.0f);
507 PUSH_DATAf(push, 0.0f);
508 PUSH_DATAf(push, 0.0f);
509 PUSH_DATAf(push, 0.0f);
510 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
511 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
512 PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
513
514 nv50_upload_ms_info(push);
515
516 /* max TIC (bits 4:8) & TSC bindings, per program type */
517 for (i = 0; i < 3; ++i) {
518 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
519 PUSH_DATA (push, 0x54);
520 }
521
522 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
523 PUSH_DATAh(push, screen->txc->offset);
524 PUSH_DATA (push, screen->txc->offset);
525 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
526
527 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
528 PUSH_DATAh(push, screen->txc->offset + 65536);
529 PUSH_DATA (push, screen->txc->offset + 65536);
530 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
531
532 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
533 PUSH_DATA (push, 0);
534
535 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
536 PUSH_DATA (push, 0);
537 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
538 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
539 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
540 for (i = 0; i < 8 * 2; ++i)
541 PUSH_DATA(push, 0);
542 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
543 PUSH_DATA (push, 0);
544
545 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
546 PUSH_DATA (push, 1);
547 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
548 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
549 PUSH_DATAf(push, 0.0f);
550 PUSH_DATAf(push, 1.0f);
551 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
552 PUSH_DATA (push, 8192 << 16);
553 PUSH_DATA (push, 8192 << 16);
554 }
555
556 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
557 #ifdef NV50_SCISSORS_CLIPPING
558 PUSH_DATA (push, 0x0000);
559 #else
560 PUSH_DATA (push, 0x1080);
561 #endif
562
563 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
564 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
565
566 /* We use scissors instead of exact view volume clipping,
567 * so they're always enabled.
568 */
569 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
570 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
571 PUSH_DATA (push, 1);
572 PUSH_DATA (push, 8192 << 16);
573 PUSH_DATA (push, 8192 << 16);
574 }
575
576 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
577 PUSH_DATA (push, 1);
578 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
579 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
580 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
581 PUSH_DATA (push, 0x11111111);
582 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
583 PUSH_DATA (push, 1);
584
585 PUSH_KICK (push);
586 }
587
588 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
589 uint64_t *tls_size)
590 {
591 struct nouveau_device *dev = screen->base.device;
592 int ret;
593
594 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
595 ONE_TEMP_SIZE;
596 if (nouveau_mesa_debug)
597 debug_printf("allocating space for %u temps\n",
598 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
599 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
600 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
601
602 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
603 *tls_size, NULL, &screen->tls_bo);
604 if (ret) {
605 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
606 return ret;
607 }
608
609 return 0;
610 }
611
612 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
613 {
614 struct nouveau_pushbuf *push = screen->base.pushbuf;
615 int ret;
616 uint64_t tls_size;
617
618 if (tls_space < screen->cur_tls_space)
619 return 0;
620 if (tls_space > screen->max_tls_space) {
621 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
622 * LOCAL_WARPS_NO_CLAMP) */
623 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
624 (unsigned)(tls_space / ONE_TEMP_SIZE),
625 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
626 return -ENOMEM;
627 }
628
629 nouveau_bo_ref(NULL, &screen->tls_bo);
630 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
631 if (ret)
632 return ret;
633
634 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
635 PUSH_DATAh(push, screen->tls_bo->offset);
636 PUSH_DATA (push, screen->tls_bo->offset);
637 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
638
639 return 1;
640 }
641
642 struct pipe_screen *
643 nv50_screen_create(struct nouveau_device *dev)
644 {
645 struct nv50_screen *screen;
646 struct pipe_screen *pscreen;
647 struct nouveau_object *chan;
648 uint64_t value;
649 uint32_t tesla_class;
650 unsigned stack_size;
651 int ret;
652
653 screen = CALLOC_STRUCT(nv50_screen);
654 if (!screen)
655 return NULL;
656 pscreen = &screen->base.base;
657
658 ret = nouveau_screen_init(&screen->base, dev);
659 if (ret) {
660 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
661 goto fail;
662 }
663
664 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
665 * admit them to VRAM.
666 */
667 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
668 PIPE_BIND_VERTEX_BUFFER;
669 screen->base.sysmem_bindings |=
670 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
671
672 screen->base.pushbuf->user_priv = screen;
673 screen->base.pushbuf->rsvd_kick = 5;
674
675 chan = screen->base.channel;
676
677 pscreen->destroy = nv50_screen_destroy;
678 pscreen->context_create = nv50_create;
679 pscreen->is_format_supported = nv50_screen_is_format_supported;
680 pscreen->get_param = nv50_screen_get_param;
681 pscreen->get_shader_param = nv50_screen_get_shader_param;
682 pscreen->get_paramf = nv50_screen_get_paramf;
683
684 nv50_screen_init_resource_functions(pscreen);
685
686 if (screen->base.device->chipset < 0x84 ||
687 debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
688 /* PMPEG */
689 nouveau_screen_init_vdec(&screen->base);
690 } else if (screen->base.device->chipset < 0x98 ||
691 screen->base.device->chipset == 0xa0) {
692 /* VP2 */
693 screen->base.base.get_video_param = nv84_screen_get_video_param;
694 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
695 } else {
696 /* VP3/4 */
697 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
698 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
699 }
700
701 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
702 NULL, &screen->fence.bo);
703 if (ret) {
704 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
705 goto fail;
706 }
707
708 nouveau_bo_map(screen->fence.bo, 0, NULL);
709 screen->fence.map = screen->fence.bo->map;
710 screen->base.fence.emit = nv50_screen_fence_emit;
711 screen->base.fence.update = nv50_screen_fence_update;
712
713 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
714 &(struct nv04_notify){ .length = 32 },
715 sizeof(struct nv04_notify), &screen->sync);
716 if (ret) {
717 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
718 goto fail;
719 }
720
721 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
722 NULL, 0, &screen->m2mf);
723 if (ret) {
724 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
725 goto fail;
726 }
727
728 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
729 NULL, 0, &screen->eng2d);
730 if (ret) {
731 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
732 goto fail;
733 }
734
735 switch (dev->chipset & 0xf0) {
736 case 0x50:
737 tesla_class = NV50_3D_CLASS;
738 break;
739 case 0x80:
740 case 0x90:
741 tesla_class = NV84_3D_CLASS;
742 break;
743 case 0xa0:
744 switch (dev->chipset) {
745 case 0xa0:
746 case 0xaa:
747 case 0xac:
748 tesla_class = NVA0_3D_CLASS;
749 break;
750 case 0xaf:
751 tesla_class = NVAF_3D_CLASS;
752 break;
753 default:
754 tesla_class = NVA3_3D_CLASS;
755 break;
756 }
757 break;
758 default:
759 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
760 goto fail;
761 }
762 screen->base.class_3d = tesla_class;
763
764 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
765 NULL, 0, &screen->tesla);
766 if (ret) {
767 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
768 goto fail;
769 }
770
771 /* This over-allocates by a page. The GP, which would execute at the end of
772 * the last page, would trigger faults. The going theory is that it
773 * prefetches up to a certain amount.
774 */
775 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
776 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
777 NULL, &screen->code);
778 if (ret) {
779 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
780 goto fail;
781 }
782
783 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
784 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
785 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
786
787 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
788
789 screen->TPs = util_bitcount(value & 0xffff);
790 screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
791
792 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
793 STACK_WARPS_ALLOC * 64 * 8;
794
795 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
796 &screen->stack_bo);
797 if (ret) {
798 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
799 goto fail;
800 }
801
802 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
803 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
804 ONE_TEMP_SIZE;
805 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
806 screen->max_tls_space /= 2; /* half of vram */
807
808 /* hw can address max 64 KiB */
809 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
810
811 uint64_t tls_size;
812 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
813 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
814 if (ret)
815 goto fail;
816
817 if (nouveau_mesa_debug)
818 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
819 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
820
821 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
822 &screen->uniforms);
823 if (ret) {
824 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
825 goto fail;
826 }
827
828 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
829 &screen->txc);
830 if (ret) {
831 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
832 goto fail;
833 }
834
835 screen->tic.entries = CALLOC(4096, sizeof(void *));
836 screen->tsc.entries = screen->tic.entries + 2048;
837
838 if (!nv50_blitter_create(screen))
839 goto fail;
840
841 nv50_screen_init_hwctx(screen);
842
843 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
844
845 return pscreen;
846
847 fail:
848 nv50_screen_destroy(pscreen);
849 return NULL;
850 }
851
852 int
853 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
854 {
855 int i = screen->tic.next;
856
857 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
858 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
859
860 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
861
862 if (screen->tic.entries[i])
863 nv50_tic_entry(screen->tic.entries[i])->id = -1;
864
865 screen->tic.entries[i] = entry;
866 return i;
867 }
868
869 int
870 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
871 {
872 int i = screen->tsc.next;
873
874 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
875 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
876
877 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
878
879 if (screen->tsc.entries[i])
880 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
881
882 screen->tsc.entries[i] = entry;
883 return i;
884 }