src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* transfers & shared are always supported */
  79    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  80                  PIPE_BIND_TRANSFER_WRITE |
  81                  PIPE_BIND_LINEAR |
  82                  PIPE_BIND_SHARED);
  83
  84    return (( nv50_format_table[format].usage |
  85             nv50_vertex_format[format].usage) & bindings) == bindings;
  86 }
  87
  88 static int
  89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  90 {
  91    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  92    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  93
  94    switch (param) {
  95    /* non-boolean caps */
  96    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  97       return 14;
  98    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  99       return 12;
 100    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 101       return 14;
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103       return 512;
 104    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 105    case PIPE_CAP_MIN_TEXEL_OFFSET:
 106       return -8;
 107    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109       return 7;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 128 * 1024 * 1024;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 113       return 330;
 114    case PIPE_CAP_MAX_RENDER_TARGETS:
 115       return 8;
 116    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 117       return 1;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 119       return 4;
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122       return 64;
 123    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 124    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 125       return 1024;
 126    case PIPE_CAP_MAX_VERTEX_STREAMS:
 127       return 1;
 128    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 129       return 2048;
 130    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 131       return 256;
 132    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 133       return 16; /* 256 for binding as RT, but that's not possible in GL */
 134    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 135       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 136    case PIPE_CAP_MAX_VIEWPORTS:
 137       return NV50_MAX_VIEWPORTS;
 138    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 139       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 140    case PIPE_CAP_ENDIANNESS:
 141       return PIPE_ENDIAN_LITTLE;
 142    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 143       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 144    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 145       return NV50_MAX_WINDOW_RECTANGLES;
 146
 147    /* supported caps */
 148    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 149    case PIPE_CAP_TEXTURE_SWIZZLE:
 150    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 151    case PIPE_CAP_NPOT_TEXTURES:
 152    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 153    case PIPE_CAP_ANISOTROPIC_FILTER:
 154    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 155    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 156    case PIPE_CAP_TWO_SIDED_STENCIL:
 157    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 158    case PIPE_CAP_POINT_SPRITE:
 159    case PIPE_CAP_SM3:
 160    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 161    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 162    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 163    case PIPE_CAP_QUERY_TIMESTAMP:
 164    case PIPE_CAP_QUERY_TIME_ELAPSED:
 165    case PIPE_CAP_OCCLUSION_QUERY:
 166    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 167    case PIPE_CAP_INDEP_BLEND_ENABLE:
 168    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 169    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 170    case PIPE_CAP_PRIMITIVE_RESTART:
 171    case PIPE_CAP_TGSI_INSTANCEID:
 172    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 173    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 174    case PIPE_CAP_CONDITIONAL_RENDER:
 175    case PIPE_CAP_TEXTURE_BARRIER:
 176    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 177    case PIPE_CAP_START_INSTANCE:
 178    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 179    case PIPE_CAP_USER_INDEX_BUFFERS:
 180    case PIPE_CAP_USER_VERTEX_BUFFERS:
 181    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 182    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 183    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 184    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 185    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 186    case PIPE_CAP_CLIP_HALFZ:
 187    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 188    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 189    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 190    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 191    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 192    case PIPE_CAP_TGSI_TXQS:
 193    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 194    case PIPE_CAP_SHAREABLE_SHADERS:
 195    case PIPE_CAP_CLEAR_TEXTURE:
 196    case PIPE_CAP_COMPUTE:
 197    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 198    case PIPE_CAP_INVALIDATE_BUFFER:
 199    case PIPE_CAP_STRING_MARKER:
 200    case PIPE_CAP_CULL_DISTANCE:
 201       return 1;
 202    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 203       return 1; /* class_3d >= NVA0_3D_CLASS; */
 204    /* supported on nva0+ */
 205    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 206       return class_3d >= NVA0_3D_CLASS;
 207    /* supported on nva3+ */
 208    case PIPE_CAP_CUBE_MAP_ARRAY:
 209    case PIPE_CAP_INDEP_BLEND_FUNC:
 210    case PIPE_CAP_TEXTURE_QUERY_LOD:
 211    case PIPE_CAP_SAMPLE_SHADING:
 212    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 213       return class_3d >= NVA3_3D_CLASS;
 214
 215    /* unsupported caps */
 216    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 217    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 218    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 219    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 220    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 221    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 222    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 223    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 224    case PIPE_CAP_TGSI_TEXCOORD:
 225    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 226    case PIPE_CAP_TEXTURE_GATHER_SM5:
 227    case PIPE_CAP_FAKE_SW_MSAA:
 228    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 229    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 230    case PIPE_CAP_DRAW_INDIRECT:
 231    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 232    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 233    case PIPE_CAP_VERTEXID_NOBASE:
 234    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 235    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 236    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 237    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 238    case PIPE_CAP_DRAW_PARAMETERS:
 239    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 240    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 241    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 242    case PIPE_CAP_GENERATE_MIPMAP:
 243    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 244    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 245    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 246    case PIPE_CAP_QUERY_MEMORY_INFO:
 247    case PIPE_CAP_PCI_GROUP:
 248    case PIPE_CAP_PCI_BUS:
 249    case PIPE_CAP_PCI_DEVICE:
 250    case PIPE_CAP_PCI_FUNCTION:
 251    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 252    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 253    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 254    case PIPE_CAP_TGSI_VOTE:
 255    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 256       return 0;
 257
 258    case PIPE_CAP_VENDOR_ID:
 259       return 0x10de;
 260    case PIPE_CAP_DEVICE_ID: {
 261       uint64_t device_id;
 262       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 263          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 264          return -1;
 265       }
 266       return device_id;
 267    }
 268    case PIPE_CAP_ACCELERATED:
 269       return 1;
 270    case PIPE_CAP_VIDEO_MEMORY:
 271       return dev->vram_size >> 20;
 272    case PIPE_CAP_UMA:
 273       return 0;
 274    }
 275
 276    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 277    return 0;
 278 }
 279
 280 static int
 281 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 282                              enum pipe_shader_cap param)
 283 {
 284    switch (shader) {
 285    case PIPE_SHADER_VERTEX:
 286    case PIPE_SHADER_GEOMETRY:
 287    case PIPE_SHADER_FRAGMENT:
 288       break;
 289    case PIPE_SHADER_COMPUTE:
 290    default:
 291       return 0;
 292    }
 293
 294    switch (param) {
 295    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 296    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 297    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 298    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 299       return 16384;
 300    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 301       return 4;
 302    case PIPE_SHADER_CAP_MAX_INPUTS:
 303       if (shader == PIPE_SHADER_VERTEX)
 304          return 32;
 305       return 15;
 306    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 307       return 16;
 308    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 309       return 65536;
 310    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 311       return NV50_MAX_PIPE_CONSTBUFS;
 312    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 313       return shader != PIPE_SHADER_FRAGMENT;
 314    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 315    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 316    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 317       return 1;
 318    case PIPE_SHADER_CAP_MAX_PREDS:
 319       return 0;
 320    case PIPE_SHADER_CAP_MAX_TEMPS:
 321       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 322    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 323       return 1;
 324    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 325       return 1;
 326    case PIPE_SHADER_CAP_SUBROUTINES:
 327       return 0; /* please inline, or provide function declarations */
 328    case PIPE_SHADER_CAP_INTEGERS:
 329       return 1;
 330    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 331       /* The chip could handle more sampler views than samplers */
 332    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 333       return MIN2(16, PIPE_MAX_SAMPLERS);
 334    case PIPE_SHADER_CAP_PREFERRED_IR:
 335       return PIPE_SHADER_IR_TGSI;
 336    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 337       return 32;
 338    case PIPE_SHADER_CAP_DOUBLES:
 339    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 340    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 341    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 342    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 343    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 344    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 345    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 346       return 0;
 347    default:
 348       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 349       return 0;
 350    }
 351 }
 352
 353 static float
 354 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 355 {
 356    switch (param) {
 357    case PIPE_CAPF_MAX_LINE_WIDTH:
 358    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 359       return 10.0f;
 360    case PIPE_CAPF_MAX_POINT_WIDTH:
 361    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 362       return 64.0f;
 363    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 364       return 16.0f;
 365    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 366       return 4.0f;
 367    case PIPE_CAPF_GUARD_BAND_LEFT:
 368    case PIPE_CAPF_GUARD_BAND_TOP:
 369       return 0.0f;
 370    case PIPE_CAPF_GUARD_BAND_RIGHT:
 371    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 372       return 0.0f; /* that or infinity */
 373    }
 374
 375    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 376    return 0.0f;
 377 }
 378
 379 static int
 380 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 381                               enum pipe_shader_ir ir_type,
 382                               enum pipe_compute_cap param, void *data)
 383 {
 384    struct nv50_screen *screen = nv50_screen(pscreen);
 385
 386 #define RET(x) do {                  \
 387    if (data)                         \
 388       memcpy(data, x, sizeof(x));    \
 389    return sizeof(x);                 \
 390 } while (0)
 391
 392    switch (param) {
 393    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 394       RET((uint64_t []) { 2 });
 395    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 396       RET(((uint64_t []) { 65535, 65535 }));
 397    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 398       RET(((uint64_t []) { 512, 512, 64 }));
 399    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 400       RET((uint64_t []) { 512 });
 401    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 402       RET((uint64_t []) { 1ULL << 32 });
 403    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 404       RET((uint64_t []) { 16 << 10 });
 405    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 406       RET((uint64_t []) { 16 << 10 });
 407    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 408       RET((uint64_t []) { 4096 });
 409    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 410       RET((uint32_t []) { 32 });
 411    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 412       RET((uint64_t []) { 1ULL << 40 });
 413    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 414       RET((uint32_t []) { 0 });
 415    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 416       RET((uint32_t []) { screen->mp_count });
 417    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 418       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 419    default:
 420       return 0;
 421    }
 422
 423 #undef RET
 424 }
 425
 426 static void
 427 nv50_screen_destroy(struct pipe_screen *pscreen)
 428 {
 429    struct nv50_screen *screen = nv50_screen(pscreen);
 430
 431    if (!nouveau_drm_screen_unref(&screen->base))
 432       return;
 433
 434    if (screen->base.fence.current) {
 435       struct nouveau_fence *current = NULL;
 436
 437       /* nouveau_fence_wait will create a new current fence, so wait on the
 438        * _current_ one, and remove both.
 439        */
 440       nouveau_fence_ref(screen->base.fence.current, &current);
 441       nouveau_fence_wait(current, NULL);
 442       nouveau_fence_ref(NULL, &current);
 443       nouveau_fence_ref(NULL, &screen->base.fence.current);
 444    }
 445    if (screen->base.pushbuf)
 446       screen->base.pushbuf->user_priv = NULL;
 447
 448    if (screen->blitter)
 449       nv50_blitter_destroy(screen);
 450    if (screen->pm.prog) {
 451       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 452       nv50_program_destroy(NULL, screen->pm.prog);
 453       FREE(screen->pm.prog);
 454    }
 455
 456    nouveau_bo_ref(NULL, &screen->code);
 457    nouveau_bo_ref(NULL, &screen->tls_bo);
 458    nouveau_bo_ref(NULL, &screen->stack_bo);
 459    nouveau_bo_ref(NULL, &screen->txc);
 460    nouveau_bo_ref(NULL, &screen->uniforms);
 461    nouveau_bo_ref(NULL, &screen->fence.bo);
 462
 463    nouveau_heap_destroy(&screen->vp_code_heap);
 464    nouveau_heap_destroy(&screen->gp_code_heap);
 465    nouveau_heap_destroy(&screen->fp_code_heap);
 466
 467    FREE(screen->tic.entries);
 468
 469    nouveau_object_del(&screen->tesla);
 470    nouveau_object_del(&screen->eng2d);
 471    nouveau_object_del(&screen->m2mf);
 472    nouveau_object_del(&screen->compute);
 473    nouveau_object_del(&screen->sync);
 474
 475    nouveau_screen_fini(&screen->base);
 476
 477    FREE(screen);
 478 }
 479
 480 static void
 481 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 482 {
 483    struct nv50_screen *screen = nv50_screen(pscreen);
 484    struct nouveau_pushbuf *push = screen->base.pushbuf;
 485
 486    /* we need to do it after possible flush in MARK_RING */
 487    *sequence = ++screen->base.fence.sequence;
 488
 489    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 490    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 491    PUSH_DATAh(push, screen->fence.bo->offset);
 492    PUSH_DATA (push, screen->fence.bo->offset);
 493    PUSH_DATA (push, *sequence);
 494    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 495                     NV50_3D_QUERY_GET_UNK4 |
 496                     NV50_3D_QUERY_GET_UNIT_CROP |
 497                     NV50_3D_QUERY_GET_TYPE_QUERY |
 498                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 499                     NV50_3D_QUERY_GET_SHORT);
 500 }
 501
 502 static u32
 503 nv50_screen_fence_update(struct pipe_screen *pscreen)
 504 {
 505    return nv50_screen(pscreen)->fence.map[0];
 506 }
 507
 508 static void
 509 nv50_screen_init_hwctx(struct nv50_screen *screen)
 510 {
 511    struct nouveau_pushbuf *push = screen->base.pushbuf;
 512    struct nv04_fifo *fifo;
 513    unsigned i;
 514
 515    fifo = (struct nv04_fifo *)screen->base.channel->data;
 516
 517    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 518    PUSH_DATA (push, screen->m2mf->handle);
 519    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 520    PUSH_DATA (push, screen->sync->handle);
 521    PUSH_DATA (push, fifo->vram);
 522    PUSH_DATA (push, fifo->vram);
 523
 524    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 525    PUSH_DATA (push, screen->eng2d->handle);
 526    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 527    PUSH_DATA (push, screen->sync->handle);
 528    PUSH_DATA (push, fifo->vram);
 529    PUSH_DATA (push, fifo->vram);
 530    PUSH_DATA (push, fifo->vram);
 531    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 532    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 533    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 534    PUSH_DATA (push, 0);
 535    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 536    PUSH_DATA (push, 0);
 537    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 538    PUSH_DATA (push, 1);
 539    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 540    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 541
 542    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 543    PUSH_DATA (push, screen->tesla->handle);
 544
 545    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 546    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 547
 548    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 549    PUSH_DATA (push, screen->sync->handle);
 550    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 551    for (i = 0; i < 11; ++i)
 552       PUSH_DATA(push, fifo->vram);
 553    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 554    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 555       PUSH_DATA(push, fifo->vram);
 556
 557    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 558    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 559    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 560    PUSH_DATA (push, 0xf);
 561
 562    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 563       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 564       PUSH_DATA (push, 0x18);
 565    }
 566
 567    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 568    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 569
 570    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 571    for (i = 0; i < 8; ++i)
 572       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 573
 574    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 575    PUSH_DATA (push, 1);
 576
 577    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 578    PUSH_DATA (push, 0);
 579    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 580    PUSH_DATA (push, 0);
 581    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 582    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 583    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 584    PUSH_DATA (push, 0);
 585    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 586    PUSH_DATA (push, 1);
 587    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 588    PUSH_DATA (push, 1);
 589
 590    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 591       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 592       PUSH_DATA (push, 0);
 593    }
 594
 595    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 596    PUSH_DATA (push, 0);
 597    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 598    PUSH_DATA (push, 0);
 599    PUSH_DATA (push, 0);
 600    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 601    PUSH_DATA (push, 0x3f);
 602
 603    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 604    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 605    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 606
 607    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 608    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 609    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 610
 611    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 612    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 613    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 614
 615    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 616    PUSH_DATAh(push, screen->tls_bo->offset);
 617    PUSH_DATA (push, screen->tls_bo->offset);
 618    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 619
 620    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 621    PUSH_DATAh(push, screen->stack_bo->offset);
 622    PUSH_DATA (push, screen->stack_bo->offset);
 623    PUSH_DATA (push, 4);
 624
 625    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 626    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 627    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 628    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 629
 630    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 631    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 632    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 633    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 634
 635    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 636    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 637    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 638    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 639
 640    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 641    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 642    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 643    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 644
 645    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 646    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 647    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 648    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 649
 650    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 651    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 652    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 653    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 654    PUSH_DATAf(push, 0.0f);
 655    PUSH_DATAf(push, 0.0f);
 656    PUSH_DATAf(push, 0.0f);
 657    PUSH_DATAf(push, 0.0f);
 658    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 659    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 660    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 661
 662    nv50_upload_ms_info(push);
 663
 664    /* max TIC (bits 4:8) & TSC bindings, per program type */
 665    for (i = 0; i < 3; ++i) {
 666       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 667       PUSH_DATA (push, 0x54);
 668    }
 669
 670    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 671    PUSH_DATAh(push, screen->txc->offset);
 672    PUSH_DATA (push, screen->txc->offset);
 673    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 674
 675    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 676    PUSH_DATAh(push, screen->txc->offset + 65536);
 677    PUSH_DATA (push, screen->txc->offset + 65536);
 678    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 679
 680    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 681    PUSH_DATA (push, 0);
 682
 683    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 684    PUSH_DATA (push, 0);
 685    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 686    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 687    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 688    for (i = 0; i < 8 * 2; ++i)
 689       PUSH_DATA(push, 0);
 690    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 691    PUSH_DATA (push, 0);
 692
 693    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 694    PUSH_DATA (push, 1);
 695    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 696       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 697       PUSH_DATAf(push, 0.0f);
 698       PUSH_DATAf(push, 1.0f);
 699       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 700       PUSH_DATA (push, 8192 << 16);
 701       PUSH_DATA (push, 8192 << 16);
 702    }
 703
 704    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 705 #ifdef NV50_SCISSORS_CLIPPING
 706    PUSH_DATA (push, 0x0000);
 707 #else
 708    PUSH_DATA (push, 0x1080);
 709 #endif
 710
 711    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 712    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 713
 714    /* We use scissors instead of exact view volume clipping,
 715     * so they're always enabled.
 716     */
 717    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 718       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 719       PUSH_DATA (push, 1);
 720       PUSH_DATA (push, 8192 << 16);
 721       PUSH_DATA (push, 8192 << 16);
 722    }
 723
 724    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 725    PUSH_DATA (push, 1);
 726    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 727    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 728    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 729    PUSH_DATA (push, 0x11111111);
 730    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 731    PUSH_DATA (push, 1);
 732
 733    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 734    PUSH_DATA (push, 0);
 735    if (screen->base.class_3d >= NV84_3D_CLASS) {
 736       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 737       PUSH_DATA (push, 0);
 738    }
 739
 740    PUSH_KICK (push);
 741 }
 742
 743 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 744       uint64_t *tls_size)
 745 {
 746    struct nouveau_device *dev = screen->base.device;
 747    int ret;
 748
 749    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 750          ONE_TEMP_SIZE;
 751    if (nouveau_mesa_debug)
 752       debug_printf("allocating space for %u temps\n",
 753             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 754    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 755          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 756
 757    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 758                         *tls_size, NULL, &screen->tls_bo);
 759    if (ret) {
 760       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 761       return ret;
 762    }
 763
 764    return 0;
 765 }
 766
 767 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 768 {
 769    struct nouveau_pushbuf *push = screen->base.pushbuf;
 770    int ret;
 771    uint64_t tls_size;
 772
 773    if (tls_space < screen->cur_tls_space)
 774       return 0;
 775    if (tls_space > screen->max_tls_space) {
 776       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 777        * LOCAL_WARPS_NO_CLAMP) */
 778       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 779             (unsigned)(tls_space / ONE_TEMP_SIZE),
 780             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 781       return -ENOMEM;
 782    }
 783
 784    nouveau_bo_ref(NULL, &screen->tls_bo);
 785    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 786    if (ret)
 787       return ret;
 788
 789    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 790    PUSH_DATAh(push, screen->tls_bo->offset);
 791    PUSH_DATA (push, screen->tls_bo->offset);
 792    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 793
 794    return 1;
 795 }
 796
 797 struct nouveau_screen *
 798 nv50_screen_create(struct nouveau_device *dev)
 799 {
 800    struct nv50_screen *screen;
 801    struct pipe_screen *pscreen;
 802    struct nouveau_object *chan;
 803    uint64_t value;
 804    uint32_t tesla_class;
 805    unsigned stack_size;
 806    int ret;
 807
 808    screen = CALLOC_STRUCT(nv50_screen);
 809    if (!screen)
 810       return NULL;
 811    pscreen = &screen->base.base;
 812    pscreen->destroy = nv50_screen_destroy;
 813
 814    ret = nouveau_screen_init(&screen->base, dev);
 815    if (ret) {
 816       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 817       goto fail;
 818    }
 819
 820    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 821     *  admit them to VRAM.
 822     */
 823    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 824       PIPE_BIND_VERTEX_BUFFER;
 825    screen->base.sysmem_bindings |=
 826       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 827
 828    screen->base.pushbuf->user_priv = screen;
 829    screen->base.pushbuf->rsvd_kick = 5;
 830
 831    chan = screen->base.channel;
 832
 833    pscreen->context_create = nv50_create;
 834    pscreen->is_format_supported = nv50_screen_is_format_supported;
 835    pscreen->get_param = nv50_screen_get_param;
 836    pscreen->get_shader_param = nv50_screen_get_shader_param;
 837    pscreen->get_paramf = nv50_screen_get_paramf;
 838    pscreen->get_compute_param = nv50_screen_get_compute_param;
 839    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 840    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 841
 842    nv50_screen_init_resource_functions(pscreen);
 843
 844    if (screen->base.device->chipset < 0x84 ||
 845        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 846       /* PMPEG */
 847       nouveau_screen_init_vdec(&screen->base);
 848    } else if (screen->base.device->chipset < 0x98 ||
 849               screen->base.device->chipset == 0xa0) {
 850       /* VP2 */
 851       screen->base.base.get_video_param = nv84_screen_get_video_param;
 852       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 853    } else {
 854       /* VP3/4 */
 855       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 856       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 857    }
 858
 859    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 860                         NULL, &screen->fence.bo);
 861    if (ret) {
 862       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 863       goto fail;
 864    }
 865
 866    nouveau_bo_map(screen->fence.bo, 0, NULL);
 867    screen->fence.map = screen->fence.bo->map;
 868    screen->base.fence.emit = nv50_screen_fence_emit;
 869    screen->base.fence.update = nv50_screen_fence_update;
 870
 871    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 872                             &(struct nv04_notify){ .length = 32 },
 873                             sizeof(struct nv04_notify), &screen->sync);
 874    if (ret) {
 875       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 876       goto fail;
 877    }
 878
 879    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 880                             NULL, 0, &screen->m2mf);
 881    if (ret) {
 882       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 883       goto fail;
 884    }
 885
 886    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 887                             NULL, 0, &screen->eng2d);
 888    if (ret) {
 889       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 890       goto fail;
 891    }
 892
 893    switch (dev->chipset & 0xf0) {
 894    case 0x50:
 895       tesla_class = NV50_3D_CLASS;
 896       break;
 897    case 0x80:
 898    case 0x90:
 899       tesla_class = NV84_3D_CLASS;
 900       break;
 901    case 0xa0:
 902       switch (dev->chipset) {
 903       case 0xa0:
 904       case 0xaa:
 905       case 0xac:
 906          tesla_class = NVA0_3D_CLASS;
 907          break;
 908       case 0xaf:
 909          tesla_class = NVAF_3D_CLASS;
 910          break;
 911       default:
 912          tesla_class = NVA3_3D_CLASS;
 913          break;
 914       }
 915       break;
 916    default:
 917       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 918       goto fail;
 919    }
 920    screen->base.class_3d = tesla_class;
 921
 922    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 923                             NULL, 0, &screen->tesla);
 924    if (ret) {
 925       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 926       goto fail;
 927    }
 928
 929    /* This over-allocates by a page. The GP, which would execute at the end of
 930     * the last page, would trigger faults. The going theory is that it
 931     * prefetches up to a certain amount.
 932     */
 933    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 934                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 935                         NULL, &screen->code);
 936    if (ret) {
 937       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 938       goto fail;
 939    }
 940
 941    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 942    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 943    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 944
 945    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 946
 947    screen->TPs = util_bitcount(value & 0xffff);
 948    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 949
 950    screen->mp_count = screen->TPs * screen->MPsInTP;
 951
 952    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 953          STACK_WARPS_ALLOC * 64 * 8;
 954
 955    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 956                         &screen->stack_bo);
 957    if (ret) {
 958       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 959       goto fail;
 960    }
 961
 962    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 963          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 964          ONE_TEMP_SIZE;
 965    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 966    screen->max_tls_space /= 2; /* half of vram */
 967
 968    /* hw can address max 64 KiB */
 969    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 970
 971    uint64_t tls_size;
 972    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 973    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 974    if (ret)
 975       goto fail;
 976
 977    if (nouveau_mesa_debug)
 978       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 979             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 980
 981    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 982                         &screen->uniforms);
 983    if (ret) {
 984       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 985       goto fail;
 986    }
 987
 988    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 989                         &screen->txc);
 990    if (ret) {
 991       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 992       goto fail;
 993    }
 994
 995    screen->tic.entries = CALLOC(4096, sizeof(void *));
 996    screen->tsc.entries = screen->tic.entries + 2048;
 997
 998    if (!nv50_blitter_create(screen))
 999       goto fail;
1000
1001    nv50_screen_init_hwctx(screen);
1002
1003    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1004    if (ret) {
1005       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1006       goto fail;
1007    }
1008
1009    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1010
1011    return &screen->base;
1012
1013 fail:
1014    screen->base.base.context_create = NULL;
1015    return &screen->base;
1016 }
1017
1018 int
1019 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1020 {
1021    int i = screen->tic.next;
1022
1023    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1024       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1025
1026    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1027
1028    if (screen->tic.entries[i])
1029       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1030
1031    screen->tic.entries[i] = entry;
1032    return i;
1033 }
1034
1035 int
1036 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1037 {
1038    int i = screen->tsc.next;
1039
1040    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1041       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1042
1043    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1044
1045    if (screen->tsc.entries[i])
1046       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1047
1048    screen->tsc.entries[i] = entry;
1049    return i;
1050 }