src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  45
  46 static boolean
  47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  48                                 enum pipe_format format,
  49                                 enum pipe_texture_target target,
  50                                 unsigned sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (sample_count > 8)
  54       return FALSE;
  55    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  56       return FALSE;
  57    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  58       return FALSE;
  59
  60    if (!util_format_is_supported(format, bindings))
  61       return FALSE;
  62
  63    switch (format) {
  64    case PIPE_FORMAT_Z16_UNORM:
  65       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  66          return FALSE;
  67       break;
  68    default:
  69       break;
  70    }
  71
  72    /* transfers & shared are always supported */
  73    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  74                  PIPE_BIND_TRANSFER_WRITE |
  75                  PIPE_BIND_SHARED);
  76
  77    return (nv50_format_table[format].usage & bindings) == bindings;
  78 }
  79
  80 static int
  81 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  82 {
  83    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  84    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  85
  86    switch (param) {
  87    /* non-boolean caps */
  88    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  89       return 14;
  90    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  91       return 12;
  92    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  93       return 14;
  94    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  95       return 512;
  96    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  97    case PIPE_CAP_MIN_TEXEL_OFFSET:
  98       return -8;
  99    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 100    case PIPE_CAP_MAX_TEXEL_OFFSET:
 101       return 7;
 102    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 103       return 65536;
 104    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 105       return 330;
 106    case PIPE_CAP_MAX_RENDER_TARGETS:
 107       return 8;
 108    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 109       return 1;
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 111       return 4;
 112    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 113    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 114       return 64;
 115    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 116    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 117       return 1024;
 118    case PIPE_CAP_MAX_VERTEX_STREAMS:
 119       return 1;
 120    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 121       return 2048;
 122    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 123       return 256;
 124    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 125       return 1; /* 256 for binding as RT, but that's not possible in GL */
 126    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 127       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 128    case PIPE_CAP_MAX_VIEWPORTS:
 129       return NV50_MAX_VIEWPORTS;
 130    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 131       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 132    case PIPE_CAP_ENDIANNESS:
 133       return PIPE_ENDIAN_LITTLE;
 134    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 135       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 136
 137    /* supported caps */
 138    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 139    case PIPE_CAP_TEXTURE_SWIZZLE:
 140    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 141    case PIPE_CAP_NPOT_TEXTURES:
 142    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 143    case PIPE_CAP_ANISOTROPIC_FILTER:
 144    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 145    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 146    case PIPE_CAP_TWO_SIDED_STENCIL:
 147    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 148    case PIPE_CAP_POINT_SPRITE:
 149    case PIPE_CAP_SM3:
 150    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 151    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 152    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 153    case PIPE_CAP_QUERY_TIMESTAMP:
 154    case PIPE_CAP_QUERY_TIME_ELAPSED:
 155    case PIPE_CAP_OCCLUSION_QUERY:
 156    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 157    case PIPE_CAP_INDEP_BLEND_ENABLE:
 158    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 159    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 160    case PIPE_CAP_PRIMITIVE_RESTART:
 161    case PIPE_CAP_TGSI_INSTANCEID:
 162    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 163    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 164    case PIPE_CAP_CONDITIONAL_RENDER:
 165    case PIPE_CAP_TEXTURE_BARRIER:
 166    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 167    case PIPE_CAP_START_INSTANCE:
 168    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 169    case PIPE_CAP_USER_INDEX_BUFFERS:
 170    case PIPE_CAP_USER_VERTEX_BUFFERS:
 171    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 172    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 173    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 174    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 175       return 1;
 176    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 177       return 1; /* class_3d >= NVA0_3D_CLASS; */
 178    /* supported on nva0+ */
 179    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 180       return class_3d >= NVA0_3D_CLASS;
 181    /* supported on nva3+ */
 182    case PIPE_CAP_CUBE_MAP_ARRAY:
 183    case PIPE_CAP_INDEP_BLEND_FUNC:
 184    case PIPE_CAP_TEXTURE_QUERY_LOD:
 185    case PIPE_CAP_SAMPLE_SHADING:
 186       return class_3d >= NVA3_3D_CLASS;
 187
 188    /* unsupported caps */
 189    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 190    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 191    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 192    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 193    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 194    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 195    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 196    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 197    case PIPE_CAP_TGSI_TEXCOORD:
 198    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 199    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 200    case PIPE_CAP_TEXTURE_GATHER_SM5:
 201    case PIPE_CAP_FAKE_SW_MSAA:
 202    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 203    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 204    case PIPE_CAP_COMPUTE:
 205    case PIPE_CAP_DRAW_INDIRECT:
 206    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 207       return 0;
 208
 209    case PIPE_CAP_VENDOR_ID:
 210       return 0x10de;
 211    case PIPE_CAP_DEVICE_ID: {
 212       uint64_t device_id;
 213       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 214          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 215          return -1;
 216       }
 217       return device_id;
 218    }
 219    case PIPE_CAP_ACCELERATED:
 220       return 1;
 221    case PIPE_CAP_VIDEO_MEMORY:
 222       return dev->vram_size >> 20;
 223    case PIPE_CAP_UMA:
 224       return 0;
 225    }
 226
 227    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 228    return 0;
 229 }
 230
 231 static int
 232 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 233                              enum pipe_shader_cap param)
 234 {
 235    switch (shader) {
 236    case PIPE_SHADER_VERTEX:
 237    case PIPE_SHADER_GEOMETRY:
 238    case PIPE_SHADER_FRAGMENT:
 239       break;
 240    default:
 241       return 0;
 242    }
 243
 244    switch (param) {
 245    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 246    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 247    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 248    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 249       return 16384;
 250    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 251       return 4;
 252    case PIPE_SHADER_CAP_MAX_INPUTS:
 253       if (shader == PIPE_SHADER_VERTEX)
 254          return 32;
 255       return 15;
 256    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 257       return 65536;
 258    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 259       return NV50_MAX_PIPE_CONSTBUFS;
 260    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 261    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 262       return shader != PIPE_SHADER_FRAGMENT;
 263    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 264    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 265       return 1;
 266    case PIPE_SHADER_CAP_MAX_PREDS:
 267       return 0;
 268    case PIPE_SHADER_CAP_MAX_TEMPS:
 269       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 270    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 271       return 1;
 272    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 273       return 0;
 274    case PIPE_SHADER_CAP_SUBROUTINES:
 275       return 0; /* please inline, or provide function declarations */
 276    case PIPE_SHADER_CAP_INTEGERS:
 277       return 1;
 278    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 279       /* The chip could handle more sampler views than samplers */
 280    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 281       return MIN2(32, PIPE_MAX_SAMPLERS);
 282    default:
 283       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 284       return 0;
 285    }
 286 }
 287
 288 static float
 289 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 290 {
 291    switch (param) {
 292    case PIPE_CAPF_MAX_LINE_WIDTH:
 293    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 294       return 10.0f;
 295    case PIPE_CAPF_MAX_POINT_WIDTH:
 296    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 297       return 64.0f;
 298    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 299       return 16.0f;
 300    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 301       return 4.0f;
 302    case PIPE_CAPF_GUARD_BAND_LEFT:
 303    case PIPE_CAPF_GUARD_BAND_TOP:
 304       return 0.0f;
 305    case PIPE_CAPF_GUARD_BAND_RIGHT:
 306    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 307       return 0.0f; /* that or infinity */
 308    }
 309
 310    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 311    return 0.0f;
 312 }
 313
 314 static void
 315 nv50_screen_destroy(struct pipe_screen *pscreen)
 316 {
 317    struct nv50_screen *screen = nv50_screen(pscreen);
 318
 319    if (!nouveau_drm_screen_unref(&screen->base))
 320       return;
 321
 322    if (screen->base.fence.current) {
 323       struct nouveau_fence *current = NULL;
 324
 325       /* nouveau_fence_wait will create a new current fence, so wait on the
 326        * _current_ one, and remove both.
 327        */
 328       nouveau_fence_ref(screen->base.fence.current, &current);
 329       nouveau_fence_wait(current);
 330       nouveau_fence_ref(NULL, &current);
 331       nouveau_fence_ref(NULL, &screen->base.fence.current);
 332    }
 333    if (screen->base.pushbuf)
 334       screen->base.pushbuf->user_priv = NULL;
 335
 336    if (screen->blitter)
 337       nv50_blitter_destroy(screen);
 338
 339    nouveau_bo_ref(NULL, &screen->code);
 340    nouveau_bo_ref(NULL, &screen->tls_bo);
 341    nouveau_bo_ref(NULL, &screen->stack_bo);
 342    nouveau_bo_ref(NULL, &screen->txc);
 343    nouveau_bo_ref(NULL, &screen->uniforms);
 344    nouveau_bo_ref(NULL, &screen->fence.bo);
 345
 346    nouveau_heap_destroy(&screen->vp_code_heap);
 347    nouveau_heap_destroy(&screen->gp_code_heap);
 348    nouveau_heap_destroy(&screen->fp_code_heap);
 349
 350    FREE(screen->tic.entries);
 351
 352    nouveau_object_del(&screen->tesla);
 353    nouveau_object_del(&screen->eng2d);
 354    nouveau_object_del(&screen->m2mf);
 355    nouveau_object_del(&screen->sync);
 356
 357    nouveau_screen_fini(&screen->base);
 358
 359    FREE(screen);
 360 }
 361
 362 static void
 363 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 364 {
 365    struct nv50_screen *screen = nv50_screen(pscreen);
 366    struct nouveau_pushbuf *push = screen->base.pushbuf;
 367
 368    /* we need to do it after possible flush in MARK_RING */
 369    *sequence = ++screen->base.fence.sequence;
 370
 371    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 372    PUSH_DATAh(push, screen->fence.bo->offset);
 373    PUSH_DATA (push, screen->fence.bo->offset);
 374    PUSH_DATA (push, *sequence);
 375    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 376                     NV50_3D_QUERY_GET_UNK4 |
 377                     NV50_3D_QUERY_GET_UNIT_CROP |
 378                     NV50_3D_QUERY_GET_TYPE_QUERY |
 379                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 380                     NV50_3D_QUERY_GET_SHORT);
 381 }
 382
 383 static u32
 384 nv50_screen_fence_update(struct pipe_screen *pscreen)
 385 {
 386    return nv50_screen(pscreen)->fence.map[0];
 387 }
 388
 389 static void
 390 nv50_screen_init_hwctx(struct nv50_screen *screen)
 391 {
 392    struct nouveau_pushbuf *push = screen->base.pushbuf;
 393    struct nv04_fifo *fifo;
 394    unsigned i;
 395
 396    fifo = (struct nv04_fifo *)screen->base.channel->data;
 397
 398    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 399    PUSH_DATA (push, screen->m2mf->handle);
 400    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 401    PUSH_DATA (push, screen->sync->handle);
 402    PUSH_DATA (push, fifo->vram);
 403    PUSH_DATA (push, fifo->vram);
 404
 405    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 406    PUSH_DATA (push, screen->eng2d->handle);
 407    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 408    PUSH_DATA (push, screen->sync->handle);
 409    PUSH_DATA (push, fifo->vram);
 410    PUSH_DATA (push, fifo->vram);
 411    PUSH_DATA (push, fifo->vram);
 412    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 413    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 414    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 415    PUSH_DATA (push, 0);
 416    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 417    PUSH_DATA (push, 0);
 418    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 419    PUSH_DATA (push, 1);
 420    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 421    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 422
 423    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 424    PUSH_DATA (push, screen->tesla->handle);
 425
 426    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 427    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 428
 429    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 430    PUSH_DATA (push, screen->sync->handle);
 431    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 432    for (i = 0; i < 11; ++i)
 433       PUSH_DATA(push, fifo->vram);
 434    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 435    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 436       PUSH_DATA(push, fifo->vram);
 437
 438    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 439    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 440    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 441    PUSH_DATA (push, 0xf);
 442
 443    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 444       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 445       PUSH_DATA (push, 0x18);
 446    }
 447
 448    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 449    PUSH_DATA (push, 1);
 450
 451    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 452    PUSH_DATA (push, 0);
 453    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 454    PUSH_DATA (push, 0);
 455    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 456    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 457    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 458    PUSH_DATA (push, 0);
 459    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 460    PUSH_DATA (push, 1);
 461    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 462    PUSH_DATA (push, 0);
 463    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 464    PUSH_DATA (push, 1);
 465
 466    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 467       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 468       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 469    }
 470
 471    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 472    PUSH_DATA (push, 0);
 473    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 474    PUSH_DATA (push, 0);
 475    PUSH_DATA (push, 0);
 476    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 477    PUSH_DATA (push, 0x3f);
 478
 479    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 480    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 481    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 482
 483    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 484    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 485    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 486
 487    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 488    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 489    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 490
 491    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 492    PUSH_DATAh(push, screen->tls_bo->offset);
 493    PUSH_DATA (push, screen->tls_bo->offset);
 494    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 495
 496    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 497    PUSH_DATAh(push, screen->stack_bo->offset);
 498    PUSH_DATA (push, screen->stack_bo->offset);
 499    PUSH_DATA (push, 4);
 500
 501    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 502    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 503    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 504    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 505
 506    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 507    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 508    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 509    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 510
 511    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 512    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 513    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 514    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 515
 516    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 517    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 518    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 519    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 520
 521    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 522    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 523    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 524    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 525
 526    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 527    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 528    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 529    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 530    PUSH_DATAf(push, 0.0f);
 531    PUSH_DATAf(push, 0.0f);
 532    PUSH_DATAf(push, 0.0f);
 533    PUSH_DATAf(push, 0.0f);
 534    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 535    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 536    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 537
 538    nv50_upload_ms_info(push);
 539
 540    /* max TIC (bits 4:8) & TSC bindings, per program type */
 541    for (i = 0; i < 3; ++i) {
 542       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 543       PUSH_DATA (push, 0x54);
 544    }
 545
 546    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 547    PUSH_DATAh(push, screen->txc->offset);
 548    PUSH_DATA (push, screen->txc->offset);
 549    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 550
 551    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 552    PUSH_DATAh(push, screen->txc->offset + 65536);
 553    PUSH_DATA (push, screen->txc->offset + 65536);
 554    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 555
 556    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 557    PUSH_DATA (push, 0);
 558
 559    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 560    PUSH_DATA (push, 0);
 561    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 562    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 563    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 564    for (i = 0; i < 8 * 2; ++i)
 565       PUSH_DATA(push, 0);
 566    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 567    PUSH_DATA (push, 0);
 568
 569    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 570    PUSH_DATA (push, 1);
 571    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 572       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 573       PUSH_DATAf(push, 0.0f);
 574       PUSH_DATAf(push, 1.0f);
 575       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 576       PUSH_DATA (push, 8192 << 16);
 577       PUSH_DATA (push, 8192 << 16);
 578    }
 579
 580    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 581 #ifdef NV50_SCISSORS_CLIPPING
 582    PUSH_DATA (push, 0x0000);
 583 #else
 584    PUSH_DATA (push, 0x1080);
 585 #endif
 586
 587    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 588    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 589
 590    /* We use scissors instead of exact view volume clipping,
 591     * so they're always enabled.
 592     */
 593    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 594       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 595       PUSH_DATA (push, 1);
 596       PUSH_DATA (push, 8192 << 16);
 597       PUSH_DATA (push, 8192 << 16);
 598    }
 599
 600    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 601    PUSH_DATA (push, 1);
 602    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 603    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 604    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 605    PUSH_DATA (push, 0x11111111);
 606    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 607    PUSH_DATA (push, 1);
 608
 609    PUSH_KICK (push);
 610 }
 611
 612 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 613       uint64_t *tls_size)
 614 {
 615    struct nouveau_device *dev = screen->base.device;
 616    int ret;
 617
 618    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 619          ONE_TEMP_SIZE;
 620    if (nouveau_mesa_debug)
 621       debug_printf("allocating space for %u temps\n",
 622             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 623    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 624          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 625
 626    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 627                         *tls_size, NULL, &screen->tls_bo);
 628    if (ret) {
 629       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 630       return ret;
 631    }
 632
 633    return 0;
 634 }
 635
 636 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 637 {
 638    struct nouveau_pushbuf *push = screen->base.pushbuf;
 639    int ret;
 640    uint64_t tls_size;
 641
 642    if (tls_space < screen->cur_tls_space)
 643       return 0;
 644    if (tls_space > screen->max_tls_space) {
 645       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 646        * LOCAL_WARPS_NO_CLAMP) */
 647       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 648             (unsigned)(tls_space / ONE_TEMP_SIZE),
 649             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 650       return -ENOMEM;
 651    }
 652
 653    nouveau_bo_ref(NULL, &screen->tls_bo);
 654    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 655    if (ret)
 656       return ret;
 657
 658    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 659    PUSH_DATAh(push, screen->tls_bo->offset);
 660    PUSH_DATA (push, screen->tls_bo->offset);
 661    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 662
 663    return 1;
 664 }
 665
 666 struct pipe_screen *
 667 nv50_screen_create(struct nouveau_device *dev)
 668 {
 669    struct nv50_screen *screen;
 670    struct pipe_screen *pscreen;
 671    struct nouveau_object *chan;
 672    uint64_t value;
 673    uint32_t tesla_class;
 674    unsigned stack_size;
 675    int ret;
 676
 677    screen = CALLOC_STRUCT(nv50_screen);
 678    if (!screen)
 679       return NULL;
 680    pscreen = &screen->base.base;
 681
 682    ret = nouveau_screen_init(&screen->base, dev);
 683    if (ret) {
 684       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 685       goto fail;
 686    }
 687
 688    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 689     *  admit them to VRAM.
 690     */
 691    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 692       PIPE_BIND_VERTEX_BUFFER;
 693    screen->base.sysmem_bindings |=
 694       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 695
 696    screen->base.pushbuf->user_priv = screen;
 697    screen->base.pushbuf->rsvd_kick = 5;
 698
 699    chan = screen->base.channel;
 700
 701    pscreen->destroy = nv50_screen_destroy;
 702    pscreen->context_create = nv50_create;
 703    pscreen->is_format_supported = nv50_screen_is_format_supported;
 704    pscreen->get_param = nv50_screen_get_param;
 705    pscreen->get_shader_param = nv50_screen_get_shader_param;
 706    pscreen->get_paramf = nv50_screen_get_paramf;
 707
 708    nv50_screen_init_resource_functions(pscreen);
 709
 710    if (screen->base.device->chipset < 0x84 ||
 711        debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
 712       /* PMPEG */
 713       nouveau_screen_init_vdec(&screen->base);
 714    } else if (screen->base.device->chipset < 0x98 ||
 715               screen->base.device->chipset == 0xa0) {
 716       /* VP2 */
 717       screen->base.base.get_video_param = nv84_screen_get_video_param;
 718       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 719    } else {
 720       /* VP3/4 */
 721       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 722       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 723    }
 724
 725    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 726                         NULL, &screen->fence.bo);
 727    if (ret) {
 728       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 729       goto fail;
 730    }
 731
 732    nouveau_bo_map(screen->fence.bo, 0, NULL);
 733    screen->fence.map = screen->fence.bo->map;
 734    screen->base.fence.emit = nv50_screen_fence_emit;
 735    screen->base.fence.update = nv50_screen_fence_update;
 736
 737    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 738                             &(struct nv04_notify){ .length = 32 },
 739                             sizeof(struct nv04_notify), &screen->sync);
 740    if (ret) {
 741       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 742       goto fail;
 743    }
 744
 745    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 746                             NULL, 0, &screen->m2mf);
 747    if (ret) {
 748       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 749       goto fail;
 750    }
 751
 752    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 753                             NULL, 0, &screen->eng2d);
 754    if (ret) {
 755       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 756       goto fail;
 757    }
 758
 759    switch (dev->chipset & 0xf0) {
 760    case 0x50:
 761       tesla_class = NV50_3D_CLASS;
 762       break;
 763    case 0x80:
 764    case 0x90:
 765       tesla_class = NV84_3D_CLASS;
 766       break;
 767    case 0xa0:
 768       switch (dev->chipset) {
 769       case 0xa0:
 770       case 0xaa:
 771       case 0xac:
 772          tesla_class = NVA0_3D_CLASS;
 773          break;
 774       case 0xaf:
 775          tesla_class = NVAF_3D_CLASS;
 776          break;
 777       default:
 778          tesla_class = NVA3_3D_CLASS;
 779          break;
 780       }
 781       break;
 782    default:
 783       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 784       goto fail;
 785    }
 786    screen->base.class_3d = tesla_class;
 787
 788    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 789                             NULL, 0, &screen->tesla);
 790    if (ret) {
 791       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 792       goto fail;
 793    }
 794
 795    /* This over-allocates by a page. The GP, which would execute at the end of
 796     * the last page, would trigger faults. The going theory is that it
 797     * prefetches up to a certain amount.
 798     */
 799    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 800                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 801                         NULL, &screen->code);
 802    if (ret) {
 803       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 804       goto fail;
 805    }
 806
 807    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 808    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 809    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 810
 811    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 812
 813    screen->TPs = util_bitcount(value & 0xffff);
 814    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 815
 816    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 817          STACK_WARPS_ALLOC * 64 * 8;
 818
 819    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 820                         &screen->stack_bo);
 821    if (ret) {
 822       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 823       goto fail;
 824    }
 825
 826    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 827          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 828          ONE_TEMP_SIZE;
 829    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 830    screen->max_tls_space /= 2; /* half of vram */
 831
 832    /* hw can address max 64 KiB */
 833    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 834
 835    uint64_t tls_size;
 836    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 837    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 838    if (ret)
 839       goto fail;
 840
 841    if (nouveau_mesa_debug)
 842       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 843             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 844
 845    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 846                         &screen->uniforms);
 847    if (ret) {
 848       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 849       goto fail;
 850    }
 851
 852    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 853                         &screen->txc);
 854    if (ret) {
 855       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 856       goto fail;
 857    }
 858
 859    screen->tic.entries = CALLOC(4096, sizeof(void *));
 860    screen->tsc.entries = screen->tic.entries + 2048;
 861
 862    if (!nv50_blitter_create(screen))
 863       goto fail;
 864
 865    nv50_screen_init_hwctx(screen);
 866
 867    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 868
 869    return pscreen;
 870
 871 fail:
 872    nv50_screen_destroy(pscreen);
 873    return NULL;
 874 }
 875
 876 int
 877 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 878 {
 879    int i = screen->tic.next;
 880
 881    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 882       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 883
 884    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 885
 886    if (screen->tic.entries[i])
 887       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 888
 889    screen->tic.entries[i] = entry;
 890    return i;
 891 }
 892
 893 int
 894 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 895 {
 896    int i = screen->tsc.next;
 897
 898    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 899       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 900
 901    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 902
 903    if (screen->tsc.entries[i])
 904       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 905
 906    screen->tsc.entries[i] = entry;
 907    return i;
 908 }