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5b388b5aa1792a288768b4d5a1cce3aef811470e
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <errno.h>
24 #include <xf86drm.h>
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nv_object.xml.h"
36
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
41
42 #define THREADS_IN_WARP 32
43
44 static boolean
45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
46 enum pipe_format format,
47 enum pipe_texture_target target,
48 unsigned sample_count,
49 unsigned bindings)
50 {
51 if (sample_count > 8)
52 return false;
53 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
54 return false;
55 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
56 return false;
57
58 if (!util_format_is_supported(format, bindings))
59 return false;
60
61 switch (format) {
62 case PIPE_FORMAT_Z16_UNORM:
63 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
64 return false;
65 break;
66 default:
67 break;
68 }
69
70 if (bindings & PIPE_BIND_LINEAR)
71 if (util_format_is_depth_or_stencil(format) ||
72 (target != PIPE_TEXTURE_1D &&
73 target != PIPE_TEXTURE_2D &&
74 target != PIPE_TEXTURE_RECT) ||
75 sample_count > 1)
76 return false;
77
78 /* shared is always supported */
79 bindings &= ~(PIPE_BIND_LINEAR |
80 PIPE_BIND_SHARED);
81
82 return (( nv50_format_table[format].usage |
83 nv50_vertex_format[format].usage) & bindings) == bindings;
84 }
85
86 static int
87 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
88 {
89 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
90 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
91
92 switch (param) {
93 /* non-boolean caps */
94 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
95 return 14;
96 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
97 return 12;
98 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
99 return 14;
100 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
101 return 512;
102 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
103 case PIPE_CAP_MIN_TEXEL_OFFSET:
104 return -8;
105 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
106 case PIPE_CAP_MAX_TEXEL_OFFSET:
107 return 7;
108 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
109 return 128 * 1024 * 1024;
110 case PIPE_CAP_GLSL_FEATURE_LEVEL:
111 return 330;
112 case PIPE_CAP_MAX_RENDER_TARGETS:
113 return 8;
114 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
115 return 1;
116 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
117 return 4;
118 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
119 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
120 return 64;
121 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
122 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
123 return 1024;
124 case PIPE_CAP_MAX_VERTEX_STREAMS:
125 return 1;
126 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
127 return 2048;
128 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
129 return 256;
130 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
131 return 16; /* 256 for binding as RT, but that's not possible in GL */
132 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
133 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
134 case PIPE_CAP_MAX_VIEWPORTS:
135 return NV50_MAX_VIEWPORTS;
136 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
137 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
138 case PIPE_CAP_ENDIANNESS:
139 return PIPE_ENDIAN_LITTLE;
140 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
141 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
142 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
143 return NV50_MAX_WINDOW_RECTANGLES;
144
145 /* supported caps */
146 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
147 case PIPE_CAP_TEXTURE_SWIZZLE:
148 case PIPE_CAP_TEXTURE_SHADOW_MAP:
149 case PIPE_CAP_NPOT_TEXTURES:
150 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
151 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
152 case PIPE_CAP_ANISOTROPIC_FILTER:
153 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
154 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
155 case PIPE_CAP_TWO_SIDED_STENCIL:
156 case PIPE_CAP_DEPTH_CLIP_DISABLE:
157 case PIPE_CAP_POINT_SPRITE:
158 case PIPE_CAP_SM3:
159 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
160 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
161 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
162 case PIPE_CAP_QUERY_TIMESTAMP:
163 case PIPE_CAP_QUERY_TIME_ELAPSED:
164 case PIPE_CAP_OCCLUSION_QUERY:
165 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
166 case PIPE_CAP_INDEP_BLEND_ENABLE:
167 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
168 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
169 case PIPE_CAP_PRIMITIVE_RESTART:
170 case PIPE_CAP_TGSI_INSTANCEID:
171 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
172 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
173 case PIPE_CAP_CONDITIONAL_RENDER:
174 case PIPE_CAP_TEXTURE_BARRIER:
175 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
176 case PIPE_CAP_START_INSTANCE:
177 case PIPE_CAP_USER_CONSTANT_BUFFERS:
178 case PIPE_CAP_USER_INDEX_BUFFERS:
179 case PIPE_CAP_USER_VERTEX_BUFFERS:
180 case PIPE_CAP_TEXTURE_MULTISAMPLE:
181 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
182 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
183 case PIPE_CAP_SAMPLER_VIEW_TARGET:
184 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
185 case PIPE_CAP_CLIP_HALFZ:
186 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
187 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
188 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
189 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
190 case PIPE_CAP_DEPTH_BOUNDS_TEST:
191 case PIPE_CAP_TGSI_TXQS:
192 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
193 case PIPE_CAP_SHAREABLE_SHADERS:
194 case PIPE_CAP_CLEAR_TEXTURE:
195 case PIPE_CAP_COMPUTE:
196 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
197 case PIPE_CAP_INVALIDATE_BUFFER:
198 case PIPE_CAP_STRING_MARKER:
199 case PIPE_CAP_CULL_DISTANCE:
200 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
201 return 1;
202 case PIPE_CAP_SEAMLESS_CUBE_MAP:
203 return 1; /* class_3d >= NVA0_3D_CLASS; */
204 /* supported on nva0+ */
205 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
206 return class_3d >= NVA0_3D_CLASS;
207 /* supported on nva3+ */
208 case PIPE_CAP_CUBE_MAP_ARRAY:
209 case PIPE_CAP_INDEP_BLEND_FUNC:
210 case PIPE_CAP_TEXTURE_QUERY_LOD:
211 case PIPE_CAP_SAMPLE_SHADING:
212 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
213 return class_3d >= NVA3_3D_CLASS;
214
215 /* unsupported caps */
216 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
217 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
218 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
219 case PIPE_CAP_SHADER_STENCIL_EXPORT:
220 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
221 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
222 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
223 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
224 case PIPE_CAP_TGSI_TEXCOORD:
225 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
226 case PIPE_CAP_TEXTURE_GATHER_SM5:
227 case PIPE_CAP_FAKE_SW_MSAA:
228 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
229 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
230 case PIPE_CAP_DRAW_INDIRECT:
231 case PIPE_CAP_MULTI_DRAW_INDIRECT:
232 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
233 case PIPE_CAP_VERTEXID_NOBASE:
234 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
235 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
236 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
237 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
238 case PIPE_CAP_DRAW_PARAMETERS:
239 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
240 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
241 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
242 case PIPE_CAP_GENERATE_MIPMAP:
243 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
244 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
245 case PIPE_CAP_QUERY_BUFFER_OBJECT:
246 case PIPE_CAP_QUERY_MEMORY_INFO:
247 case PIPE_CAP_PCI_GROUP:
248 case PIPE_CAP_PCI_BUS:
249 case PIPE_CAP_PCI_DEVICE:
250 case PIPE_CAP_PCI_FUNCTION:
251 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
252 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
253 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
254 case PIPE_CAP_TGSI_VOTE:
255 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
256 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
257 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
258 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
259 case PIPE_CAP_NATIVE_FENCE_FD:
260 return 0;
261
262 case PIPE_CAP_VENDOR_ID:
263 return 0x10de;
264 case PIPE_CAP_DEVICE_ID: {
265 uint64_t device_id;
266 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
267 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
268 return -1;
269 }
270 return device_id;
271 }
272 case PIPE_CAP_ACCELERATED:
273 return 1;
274 case PIPE_CAP_VIDEO_MEMORY:
275 return dev->vram_size >> 20;
276 case PIPE_CAP_UMA:
277 return 0;
278 }
279
280 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
281 return 0;
282 }
283
284 static int
285 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
286 enum pipe_shader_cap param)
287 {
288 switch (shader) {
289 case PIPE_SHADER_VERTEX:
290 case PIPE_SHADER_GEOMETRY:
291 case PIPE_SHADER_FRAGMENT:
292 break;
293 case PIPE_SHADER_COMPUTE:
294 default:
295 return 0;
296 }
297
298 switch (param) {
299 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
300 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
301 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
302 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
303 return 16384;
304 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
305 return 4;
306 case PIPE_SHADER_CAP_MAX_INPUTS:
307 if (shader == PIPE_SHADER_VERTEX)
308 return 32;
309 return 15;
310 case PIPE_SHADER_CAP_MAX_OUTPUTS:
311 return 16;
312 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
313 return 65536;
314 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
315 return NV50_MAX_PIPE_CONSTBUFS;
316 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
317 return shader != PIPE_SHADER_FRAGMENT;
318 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
319 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
320 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
321 return 1;
322 case PIPE_SHADER_CAP_MAX_PREDS:
323 return 0;
324 case PIPE_SHADER_CAP_MAX_TEMPS:
325 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
326 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
327 return 1;
328 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
329 return 1;
330 case PIPE_SHADER_CAP_SUBROUTINES:
331 return 0; /* please inline, or provide function declarations */
332 case PIPE_SHADER_CAP_INTEGERS:
333 return 1;
334 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
335 /* The chip could handle more sampler views than samplers */
336 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
337 return MIN2(16, PIPE_MAX_SAMPLERS);
338 case PIPE_SHADER_CAP_PREFERRED_IR:
339 return PIPE_SHADER_IR_TGSI;
340 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
341 return 32;
342 case PIPE_SHADER_CAP_DOUBLES:
343 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
344 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
345 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
346 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
347 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
348 case PIPE_SHADER_CAP_SUPPORTED_IRS:
349 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
350 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
351 return 0;
352 default:
353 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
354 return 0;
355 }
356 }
357
358 static float
359 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
360 {
361 switch (param) {
362 case PIPE_CAPF_MAX_LINE_WIDTH:
363 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
364 return 10.0f;
365 case PIPE_CAPF_MAX_POINT_WIDTH:
366 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
367 return 64.0f;
368 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
369 return 16.0f;
370 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
371 return 4.0f;
372 case PIPE_CAPF_GUARD_BAND_LEFT:
373 case PIPE_CAPF_GUARD_BAND_TOP:
374 return 0.0f;
375 case PIPE_CAPF_GUARD_BAND_RIGHT:
376 case PIPE_CAPF_GUARD_BAND_BOTTOM:
377 return 0.0f; /* that or infinity */
378 }
379
380 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
381 return 0.0f;
382 }
383
384 static int
385 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
386 enum pipe_shader_ir ir_type,
387 enum pipe_compute_cap param, void *data)
388 {
389 struct nv50_screen *screen = nv50_screen(pscreen);
390
391 #define RET(x) do { \
392 if (data) \
393 memcpy(data, x, sizeof(x)); \
394 return sizeof(x); \
395 } while (0)
396
397 switch (param) {
398 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
399 RET((uint64_t []) { 2 });
400 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
401 RET(((uint64_t []) { 65535, 65535 }));
402 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
403 RET(((uint64_t []) { 512, 512, 64 }));
404 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
405 RET((uint64_t []) { 512 });
406 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
407 RET((uint64_t []) { 1ULL << 32 });
408 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
409 RET((uint64_t []) { 16 << 10 });
410 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
411 RET((uint64_t []) { 16 << 10 });
412 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
413 RET((uint64_t []) { 4096 });
414 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
415 RET((uint32_t []) { 32 });
416 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
417 RET((uint64_t []) { 1ULL << 40 });
418 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
419 RET((uint32_t []) { 0 });
420 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
421 RET((uint32_t []) { screen->mp_count });
422 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
423 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
424 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
425 RET((uint32_t []) { 32 });
426 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
427 RET((uint64_t []) { 0 });
428 default:
429 return 0;
430 }
431
432 #undef RET
433 }
434
435 static void
436 nv50_screen_destroy(struct pipe_screen *pscreen)
437 {
438 struct nv50_screen *screen = nv50_screen(pscreen);
439
440 if (!nouveau_drm_screen_unref(&screen->base))
441 return;
442
443 if (screen->base.fence.current) {
444 struct nouveau_fence *current = NULL;
445
446 /* nouveau_fence_wait will create a new current fence, so wait on the
447 * _current_ one, and remove both.
448 */
449 nouveau_fence_ref(screen->base.fence.current, &current);
450 nouveau_fence_wait(current, NULL);
451 nouveau_fence_ref(NULL, &current);
452 nouveau_fence_ref(NULL, &screen->base.fence.current);
453 }
454 if (screen->base.pushbuf)
455 screen->base.pushbuf->user_priv = NULL;
456
457 if (screen->blitter)
458 nv50_blitter_destroy(screen);
459 if (screen->pm.prog) {
460 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
461 nv50_program_destroy(NULL, screen->pm.prog);
462 FREE(screen->pm.prog);
463 }
464
465 nouveau_bo_ref(NULL, &screen->code);
466 nouveau_bo_ref(NULL, &screen->tls_bo);
467 nouveau_bo_ref(NULL, &screen->stack_bo);
468 nouveau_bo_ref(NULL, &screen->txc);
469 nouveau_bo_ref(NULL, &screen->uniforms);
470 nouveau_bo_ref(NULL, &screen->fence.bo);
471
472 nouveau_heap_destroy(&screen->vp_code_heap);
473 nouveau_heap_destroy(&screen->gp_code_heap);
474 nouveau_heap_destroy(&screen->fp_code_heap);
475
476 FREE(screen->tic.entries);
477
478 nouveau_object_del(&screen->tesla);
479 nouveau_object_del(&screen->eng2d);
480 nouveau_object_del(&screen->m2mf);
481 nouveau_object_del(&screen->compute);
482 nouveau_object_del(&screen->sync);
483
484 nouveau_screen_fini(&screen->base);
485
486 FREE(screen);
487 }
488
489 static void
490 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
491 {
492 struct nv50_screen *screen = nv50_screen(pscreen);
493 struct nouveau_pushbuf *push = screen->base.pushbuf;
494
495 /* we need to do it after possible flush in MARK_RING */
496 *sequence = ++screen->base.fence.sequence;
497
498 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
499 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
500 PUSH_DATAh(push, screen->fence.bo->offset);
501 PUSH_DATA (push, screen->fence.bo->offset);
502 PUSH_DATA (push, *sequence);
503 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
504 NV50_3D_QUERY_GET_UNK4 |
505 NV50_3D_QUERY_GET_UNIT_CROP |
506 NV50_3D_QUERY_GET_TYPE_QUERY |
507 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
508 NV50_3D_QUERY_GET_SHORT);
509 }
510
511 static u32
512 nv50_screen_fence_update(struct pipe_screen *pscreen)
513 {
514 return nv50_screen(pscreen)->fence.map[0];
515 }
516
517 static void
518 nv50_screen_init_hwctx(struct nv50_screen *screen)
519 {
520 struct nouveau_pushbuf *push = screen->base.pushbuf;
521 struct nv04_fifo *fifo;
522 unsigned i;
523
524 fifo = (struct nv04_fifo *)screen->base.channel->data;
525
526 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
527 PUSH_DATA (push, screen->m2mf->handle);
528 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
529 PUSH_DATA (push, screen->sync->handle);
530 PUSH_DATA (push, fifo->vram);
531 PUSH_DATA (push, fifo->vram);
532
533 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
534 PUSH_DATA (push, screen->eng2d->handle);
535 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
536 PUSH_DATA (push, screen->sync->handle);
537 PUSH_DATA (push, fifo->vram);
538 PUSH_DATA (push, fifo->vram);
539 PUSH_DATA (push, fifo->vram);
540 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
541 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
542 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
543 PUSH_DATA (push, 0);
544 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
545 PUSH_DATA (push, 0);
546 BEGIN_NV04(push, SUBC_2D(0x0888), 1);
547 PUSH_DATA (push, 1);
548 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
549 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
550
551 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
552 PUSH_DATA (push, screen->tesla->handle);
553
554 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
555 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
556
557 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
558 PUSH_DATA (push, screen->sync->handle);
559 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
560 for (i = 0; i < 11; ++i)
561 PUSH_DATA(push, fifo->vram);
562 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
563 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
564 PUSH_DATA(push, fifo->vram);
565
566 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
567 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
568 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
569 PUSH_DATA (push, 0xf);
570
571 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
572 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
573 PUSH_DATA (push, 0x18);
574 }
575
576 BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
577 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
578
579 BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
580 for (i = 0; i < 8; ++i)
581 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
582
583 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
584 PUSH_DATA (push, 1);
585
586 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
587 PUSH_DATA (push, 0);
588 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
589 PUSH_DATA (push, 0);
590 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
591 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
592 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
593 PUSH_DATA (push, 0);
594 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
595 PUSH_DATA (push, 1);
596 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
597 PUSH_DATA (push, 1);
598
599 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
600 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
601 PUSH_DATA (push, 0);
602 }
603
604 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
605 PUSH_DATA (push, 0);
606 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
607 PUSH_DATA (push, 0);
608 PUSH_DATA (push, 0);
609 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
610 PUSH_DATA (push, 0x3f);
611
612 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
613 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
614 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
615
616 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
617 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
618 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
619
620 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
621 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
622 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
623
624 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
625 PUSH_DATAh(push, screen->tls_bo->offset);
626 PUSH_DATA (push, screen->tls_bo->offset);
627 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
628
629 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
630 PUSH_DATAh(push, screen->stack_bo->offset);
631 PUSH_DATA (push, screen->stack_bo->offset);
632 PUSH_DATA (push, 4);
633
634 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
635 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
636 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
637 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
638
639 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
640 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
641 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
642 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
643
644 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
645 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
646 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
647 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
648
649 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
650 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
651 PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
652 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
653
654 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
655 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
656 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
657 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
658
659 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
660 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
661 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
662 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
663 PUSH_DATAf(push, 0.0f);
664 PUSH_DATAf(push, 0.0f);
665 PUSH_DATAf(push, 0.0f);
666 PUSH_DATAf(push, 0.0f);
667 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
668 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
669 PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
670
671 nv50_upload_ms_info(push);
672
673 /* max TIC (bits 4:8) & TSC bindings, per program type */
674 for (i = 0; i < 3; ++i) {
675 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
676 PUSH_DATA (push, 0x54);
677 }
678
679 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
680 PUSH_DATAh(push, screen->txc->offset);
681 PUSH_DATA (push, screen->txc->offset);
682 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
683
684 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
685 PUSH_DATAh(push, screen->txc->offset + 65536);
686 PUSH_DATA (push, screen->txc->offset + 65536);
687 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
688
689 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
690 PUSH_DATA (push, 0);
691
692 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
693 PUSH_DATA (push, 0);
694 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
695 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
696 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
697 for (i = 0; i < 8 * 2; ++i)
698 PUSH_DATA(push, 0);
699 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
700 PUSH_DATA (push, 0);
701
702 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
703 PUSH_DATA (push, 1);
704 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
705 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
706 PUSH_DATAf(push, 0.0f);
707 PUSH_DATAf(push, 1.0f);
708 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
709 PUSH_DATA (push, 8192 << 16);
710 PUSH_DATA (push, 8192 << 16);
711 }
712
713 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
714 #ifdef NV50_SCISSORS_CLIPPING
715 PUSH_DATA (push, 0x0000);
716 #else
717 PUSH_DATA (push, 0x1080);
718 #endif
719
720 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
721 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
722
723 /* We use scissors instead of exact view volume clipping,
724 * so they're always enabled.
725 */
726 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
727 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
728 PUSH_DATA (push, 1);
729 PUSH_DATA (push, 8192 << 16);
730 PUSH_DATA (push, 8192 << 16);
731 }
732
733 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
734 PUSH_DATA (push, 1);
735 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
736 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
737 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
738 PUSH_DATA (push, 0x11111111);
739 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
740 PUSH_DATA (push, 1);
741
742 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
743 PUSH_DATA (push, 0);
744 if (screen->base.class_3d >= NV84_3D_CLASS) {
745 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
746 PUSH_DATA (push, 0);
747 }
748
749 PUSH_KICK (push);
750 }
751
752 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
753 uint64_t *tls_size)
754 {
755 struct nouveau_device *dev = screen->base.device;
756 int ret;
757
758 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
759 ONE_TEMP_SIZE;
760 if (nouveau_mesa_debug)
761 debug_printf("allocating space for %u temps\n",
762 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
763 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
764 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
765
766 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
767 *tls_size, NULL, &screen->tls_bo);
768 if (ret) {
769 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
770 return ret;
771 }
772
773 return 0;
774 }
775
776 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
777 {
778 struct nouveau_pushbuf *push = screen->base.pushbuf;
779 int ret;
780 uint64_t tls_size;
781
782 if (tls_space < screen->cur_tls_space)
783 return 0;
784 if (tls_space > screen->max_tls_space) {
785 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
786 * LOCAL_WARPS_NO_CLAMP) */
787 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
788 (unsigned)(tls_space / ONE_TEMP_SIZE),
789 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
790 return -ENOMEM;
791 }
792
793 nouveau_bo_ref(NULL, &screen->tls_bo);
794 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
795 if (ret)
796 return ret;
797
798 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
799 PUSH_DATAh(push, screen->tls_bo->offset);
800 PUSH_DATA (push, screen->tls_bo->offset);
801 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
802
803 return 1;
804 }
805
806 struct nouveau_screen *
807 nv50_screen_create(struct nouveau_device *dev)
808 {
809 struct nv50_screen *screen;
810 struct pipe_screen *pscreen;
811 struct nouveau_object *chan;
812 uint64_t value;
813 uint32_t tesla_class;
814 unsigned stack_size;
815 int ret;
816
817 screen = CALLOC_STRUCT(nv50_screen);
818 if (!screen)
819 return NULL;
820 pscreen = &screen->base.base;
821 pscreen->destroy = nv50_screen_destroy;
822
823 ret = nouveau_screen_init(&screen->base, dev);
824 if (ret) {
825 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
826 goto fail;
827 }
828
829 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
830 * admit them to VRAM.
831 */
832 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
833 PIPE_BIND_VERTEX_BUFFER;
834 screen->base.sysmem_bindings |=
835 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
836
837 screen->base.pushbuf->user_priv = screen;
838 screen->base.pushbuf->rsvd_kick = 5;
839
840 chan = screen->base.channel;
841
842 pscreen->context_create = nv50_create;
843 pscreen->is_format_supported = nv50_screen_is_format_supported;
844 pscreen->get_param = nv50_screen_get_param;
845 pscreen->get_shader_param = nv50_screen_get_shader_param;
846 pscreen->get_paramf = nv50_screen_get_paramf;
847 pscreen->get_compute_param = nv50_screen_get_compute_param;
848 pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
849 pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
850
851 nv50_screen_init_resource_functions(pscreen);
852
853 if (screen->base.device->chipset < 0x84 ||
854 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
855 /* PMPEG */
856 nouveau_screen_init_vdec(&screen->base);
857 } else if (screen->base.device->chipset < 0x98 ||
858 screen->base.device->chipset == 0xa0) {
859 /* VP2 */
860 screen->base.base.get_video_param = nv84_screen_get_video_param;
861 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
862 } else {
863 /* VP3/4 */
864 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
865 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
866 }
867
868 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
869 NULL, &screen->fence.bo);
870 if (ret) {
871 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
872 goto fail;
873 }
874
875 nouveau_bo_map(screen->fence.bo, 0, NULL);
876 screen->fence.map = screen->fence.bo->map;
877 screen->base.fence.emit = nv50_screen_fence_emit;
878 screen->base.fence.update = nv50_screen_fence_update;
879
880 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
881 &(struct nv04_notify){ .length = 32 },
882 sizeof(struct nv04_notify), &screen->sync);
883 if (ret) {
884 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
885 goto fail;
886 }
887
888 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
889 NULL, 0, &screen->m2mf);
890 if (ret) {
891 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
892 goto fail;
893 }
894
895 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
896 NULL, 0, &screen->eng2d);
897 if (ret) {
898 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
899 goto fail;
900 }
901
902 switch (dev->chipset & 0xf0) {
903 case 0x50:
904 tesla_class = NV50_3D_CLASS;
905 break;
906 case 0x80:
907 case 0x90:
908 tesla_class = NV84_3D_CLASS;
909 break;
910 case 0xa0:
911 switch (dev->chipset) {
912 case 0xa0:
913 case 0xaa:
914 case 0xac:
915 tesla_class = NVA0_3D_CLASS;
916 break;
917 case 0xaf:
918 tesla_class = NVAF_3D_CLASS;
919 break;
920 default:
921 tesla_class = NVA3_3D_CLASS;
922 break;
923 }
924 break;
925 default:
926 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
927 goto fail;
928 }
929 screen->base.class_3d = tesla_class;
930
931 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
932 NULL, 0, &screen->tesla);
933 if (ret) {
934 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
935 goto fail;
936 }
937
938 /* This over-allocates by a page. The GP, which would execute at the end of
939 * the last page, would trigger faults. The going theory is that it
940 * prefetches up to a certain amount.
941 */
942 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
943 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
944 NULL, &screen->code);
945 if (ret) {
946 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
947 goto fail;
948 }
949
950 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
951 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
952 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
953
954 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
955
956 screen->TPs = util_bitcount(value & 0xffff);
957 screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
958
959 screen->mp_count = screen->TPs * screen->MPsInTP;
960
961 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
962 STACK_WARPS_ALLOC * 64 * 8;
963
964 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
965 &screen->stack_bo);
966 if (ret) {
967 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
968 goto fail;
969 }
970
971 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
972 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
973 ONE_TEMP_SIZE;
974 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
975 screen->max_tls_space /= 2; /* half of vram */
976
977 /* hw can address max 64 KiB */
978 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
979
980 uint64_t tls_size;
981 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
982 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
983 if (ret)
984 goto fail;
985
986 if (nouveau_mesa_debug)
987 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
988 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
989
990 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
991 &screen->uniforms);
992 if (ret) {
993 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
994 goto fail;
995 }
996
997 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
998 &screen->txc);
999 if (ret) {
1000 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1001 goto fail;
1002 }
1003
1004 screen->tic.entries = CALLOC(4096, sizeof(void *));
1005 screen->tsc.entries = screen->tic.entries + 2048;
1006
1007 if (!nv50_blitter_create(screen))
1008 goto fail;
1009
1010 nv50_screen_init_hwctx(screen);
1011
1012 ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1013 if (ret) {
1014 NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1015 goto fail;
1016 }
1017
1018 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1019
1020 return &screen->base;
1021
1022 fail:
1023 screen->base.base.context_create = NULL;
1024 return &screen->base;
1025 }
1026
1027 int
1028 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1029 {
1030 int i = screen->tic.next;
1031
1032 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1033 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1034
1035 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1036
1037 if (screen->tic.entries[i])
1038 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1039
1040 screen->tic.entries[i] = entry;
1041 return i;
1042 }
1043
1044 int
1045 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1046 {
1047 int i = screen->tsc.next;
1048
1049 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1050 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1051
1052 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1053
1054 if (screen->tsc.entries[i])
1055 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1056
1057 screen->tsc.entries[i] = entry;
1058 return i;
1059 }