src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* shared is always supported */
  79    bindings &= ~(PIPE_BIND_LINEAR |
  80                  PIPE_BIND_SHARED);
  81
  82    return (( nv50_format_table[format].usage |
  83             nv50_vertex_format[format].usage) & bindings) == bindings;
  84 }
  85
  86 static int
  87 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  88 {
  89    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  90    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  91
  92    switch (param) {
  93    /* non-boolean caps */
  94    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  97       return 12;
  98    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  99       return 14;
 100    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 101       return 512;
 102    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 103    case PIPE_CAP_MIN_TEXEL_OFFSET:
 104       return -8;
 105    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MAX_TEXEL_OFFSET:
 107       return 7;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 128 * 1024 * 1024;
 110    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 111       return 330;
 112    case PIPE_CAP_MAX_RENDER_TARGETS:
 113       return 8;
 114    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 115       return 1;
 116    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 117       return 4;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 120       return 64;
 121    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 122    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 123       return 1024;
 124    case PIPE_CAP_MAX_VERTEX_STREAMS:
 125       return 1;
 126    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 127       return 2048;
 128    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 129       return 256;
 130    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 131       return 16; /* 256 for binding as RT, but that's not possible in GL */
 132    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 133       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 134    case PIPE_CAP_MAX_VIEWPORTS:
 135       return NV50_MAX_VIEWPORTS;
 136    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 137       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 138    case PIPE_CAP_ENDIANNESS:
 139       return PIPE_ENDIAN_LITTLE;
 140    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 141       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 142    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 143       return NV50_MAX_WINDOW_RECTANGLES;
 144
 145    /* supported caps */
 146    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 147    case PIPE_CAP_TEXTURE_SWIZZLE:
 148    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 149    case PIPE_CAP_NPOT_TEXTURES:
 150    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 152    case PIPE_CAP_ANISOTROPIC_FILTER:
 153    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 154    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 155    case PIPE_CAP_TWO_SIDED_STENCIL:
 156    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 157    case PIPE_CAP_POINT_SPRITE:
 158    case PIPE_CAP_SM3:
 159    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 160    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 161    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 162    case PIPE_CAP_QUERY_TIMESTAMP:
 163    case PIPE_CAP_QUERY_TIME_ELAPSED:
 164    case PIPE_CAP_OCCLUSION_QUERY:
 165    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 166    case PIPE_CAP_INDEP_BLEND_ENABLE:
 167    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 168    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 169    case PIPE_CAP_PRIMITIVE_RESTART:
 170    case PIPE_CAP_TGSI_INSTANCEID:
 171    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 172    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173    case PIPE_CAP_CONDITIONAL_RENDER:
 174    case PIPE_CAP_TEXTURE_BARRIER:
 175    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 176    case PIPE_CAP_START_INSTANCE:
 177    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 178    case PIPE_CAP_USER_VERTEX_BUFFERS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 181    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 182    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 183    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 184    case PIPE_CAP_CLIP_HALFZ:
 185    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 186    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 187    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 188    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 189    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 190    case PIPE_CAP_TGSI_TXQS:
 191    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 192    case PIPE_CAP_SHAREABLE_SHADERS:
 193    case PIPE_CAP_CLEAR_TEXTURE:
 194    case PIPE_CAP_COMPUTE:
 195    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 196    case PIPE_CAP_INVALIDATE_BUFFER:
 197    case PIPE_CAP_STRING_MARKER:
 198    case PIPE_CAP_CULL_DISTANCE:
 199    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 200    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 201    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 202    case PIPE_CAP_TGSI_CLOCK:
 203    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 204    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 205       return 1;
 206    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 207       return 1; /* class_3d >= NVA0_3D_CLASS; */
 208    /* supported on nva0+ */
 209    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 210       return class_3d >= NVA0_3D_CLASS;
 211    /* supported on nva3+ */
 212    case PIPE_CAP_CUBE_MAP_ARRAY:
 213    case PIPE_CAP_INDEP_BLEND_FUNC:
 214    case PIPE_CAP_TEXTURE_QUERY_LOD:
 215    case PIPE_CAP_SAMPLE_SHADING:
 216    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 217       return class_3d >= NVA3_3D_CLASS;
 218
 219    /* unsupported caps */
 220    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 221    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 222    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 223    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 224    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 225    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 226    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 227    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 228    case PIPE_CAP_TGSI_TEXCOORD:
 229    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 230    case PIPE_CAP_TEXTURE_GATHER_SM5:
 231    case PIPE_CAP_FAKE_SW_MSAA:
 232    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 233    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 234    case PIPE_CAP_DRAW_INDIRECT:
 235    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 236    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 237    case PIPE_CAP_VERTEXID_NOBASE:
 238    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 239    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 240    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 241    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 242    case PIPE_CAP_DRAW_PARAMETERS:
 243    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 244    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 245    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 246    case PIPE_CAP_GENERATE_MIPMAP:
 247    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 248    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 249    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 250    case PIPE_CAP_QUERY_MEMORY_INFO:
 251    case PIPE_CAP_PCI_GROUP:
 252    case PIPE_CAP_PCI_BUS:
 253    case PIPE_CAP_PCI_DEVICE:
 254    case PIPE_CAP_PCI_FUNCTION:
 255    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 256    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 257    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 258    case PIPE_CAP_TGSI_VOTE:
 259    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 260    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 261    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 262    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 263    case PIPE_CAP_NATIVE_FENCE_FD:
 264    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 265    case PIPE_CAP_TGSI_FS_FBFETCH:
 266    case PIPE_CAP_DOUBLES:
 267    case PIPE_CAP_INT64:
 268    case PIPE_CAP_INT64_DIVMOD:
 269    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 270    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 271    case PIPE_CAP_TGSI_BALLOT:
 272    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 273    case PIPE_CAP_POST_DEPTH_COVERAGE:
 274    case PIPE_CAP_BINDLESS_TEXTURE:
 275    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 276    case PIPE_CAP_QUERY_SO_OVERFLOW:
 277    case PIPE_CAP_MEMOBJ:
 278    case PIPE_CAP_LOAD_CONSTBUF:
 279       return 0;
 280
 281    case PIPE_CAP_VENDOR_ID:
 282       return 0x10de;
 283    case PIPE_CAP_DEVICE_ID: {
 284       uint64_t device_id;
 285       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 286          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 287          return -1;
 288       }
 289       return device_id;
 290    }
 291    case PIPE_CAP_ACCELERATED:
 292       return 1;
 293    case PIPE_CAP_VIDEO_MEMORY:
 294       return dev->vram_size >> 20;
 295    case PIPE_CAP_UMA:
 296       return 0;
 297    }
 298
 299    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 300    return 0;
 301 }
 302
 303 static int
 304 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 305                              enum pipe_shader_type shader,
 306                              enum pipe_shader_cap param)
 307 {
 308    switch (shader) {
 309    case PIPE_SHADER_VERTEX:
 310    case PIPE_SHADER_GEOMETRY:
 311    case PIPE_SHADER_FRAGMENT:
 312       break;
 313    case PIPE_SHADER_COMPUTE:
 314    default:
 315       return 0;
 316    }
 317
 318    switch (param) {
 319    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 320    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 321    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 322    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 323       return 16384;
 324    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 325       return 4;
 326    case PIPE_SHADER_CAP_MAX_INPUTS:
 327       if (shader == PIPE_SHADER_VERTEX)
 328          return 32;
 329       return 15;
 330    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 331       return 16;
 332    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 333       return 65536;
 334    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 335       return NV50_MAX_PIPE_CONSTBUFS;
 336    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 337       return shader != PIPE_SHADER_FRAGMENT;
 338    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 339    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 340    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 341       return 1;
 342    case PIPE_SHADER_CAP_MAX_TEMPS:
 343       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 344    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 345       return 1;
 346    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 347       return 1;
 348    case PIPE_SHADER_CAP_FP16:
 349    case PIPE_SHADER_CAP_SUBROUTINES:
 350       return 0; /* please inline, or provide function declarations */
 351    case PIPE_SHADER_CAP_INTEGERS:
 352       return 1;
 353    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 354       return 1;
 355    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 356       /* The chip could handle more sampler views than samplers */
 357    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 358       return MIN2(16, PIPE_MAX_SAMPLERS);
 359    case PIPE_SHADER_CAP_PREFERRED_IR:
 360       return PIPE_SHADER_IR_TGSI;
 361    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 362       return 32;
 363    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 364    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 365    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 366    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 367    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 368    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 369    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 370    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 371       return 0;
 372    default:
 373       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 374       return 0;
 375    }
 376 }
 377
 378 static float
 379 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 380 {
 381    switch (param) {
 382    case PIPE_CAPF_MAX_LINE_WIDTH:
 383    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 384       return 10.0f;
 385    case PIPE_CAPF_MAX_POINT_WIDTH:
 386    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 387       return 64.0f;
 388    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 389       return 16.0f;
 390    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 391       return 4.0f;
 392    case PIPE_CAPF_GUARD_BAND_LEFT:
 393    case PIPE_CAPF_GUARD_BAND_TOP:
 394       return 0.0f;
 395    case PIPE_CAPF_GUARD_BAND_RIGHT:
 396    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 397       return 0.0f; /* that or infinity */
 398    }
 399
 400    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 401    return 0.0f;
 402 }
 403
 404 static int
 405 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 406                               enum pipe_shader_ir ir_type,
 407                               enum pipe_compute_cap param, void *data)
 408 {
 409    struct nv50_screen *screen = nv50_screen(pscreen);
 410
 411 #define RET(x) do {                  \
 412    if (data)                         \
 413       memcpy(data, x, sizeof(x));    \
 414    return sizeof(x);                 \
 415 } while (0)
 416
 417    switch (param) {
 418    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 419       RET((uint64_t []) { 2 });
 420    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 421       RET(((uint64_t []) { 65535, 65535 }));
 422    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 423       RET(((uint64_t []) { 512, 512, 64 }));
 424    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 425       RET((uint64_t []) { 512 });
 426    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 427       RET((uint64_t []) { 1ULL << 32 });
 428    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 429       RET((uint64_t []) { 16 << 10 });
 430    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 431       RET((uint64_t []) { 16 << 10 });
 432    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 433       RET((uint64_t []) { 4096 });
 434    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 435       RET((uint32_t []) { 32 });
 436    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 437       RET((uint64_t []) { 1ULL << 40 });
 438    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 439       RET((uint32_t []) { 0 });
 440    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 441       RET((uint32_t []) { screen->mp_count });
 442    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 443       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 444    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 445       RET((uint32_t []) { 32 });
 446    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 447       RET((uint64_t []) { 0 });
 448    default:
 449       return 0;
 450    }
 451
 452 #undef RET
 453 }
 454
 455 static void
 456 nv50_screen_destroy(struct pipe_screen *pscreen)
 457 {
 458    struct nv50_screen *screen = nv50_screen(pscreen);
 459
 460    if (!nouveau_drm_screen_unref(&screen->base))
 461       return;
 462
 463    if (screen->base.fence.current) {
 464       struct nouveau_fence *current = NULL;
 465
 466       /* nouveau_fence_wait will create a new current fence, so wait on the
 467        * _current_ one, and remove both.
 468        */
 469       nouveau_fence_ref(screen->base.fence.current, &current);
 470       nouveau_fence_wait(current, NULL);
 471       nouveau_fence_ref(NULL, &current);
 472       nouveau_fence_ref(NULL, &screen->base.fence.current);
 473    }
 474    if (screen->base.pushbuf)
 475       screen->base.pushbuf->user_priv = NULL;
 476
 477    if (screen->blitter)
 478       nv50_blitter_destroy(screen);
 479    if (screen->pm.prog) {
 480       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 481       nv50_program_destroy(NULL, screen->pm.prog);
 482       FREE(screen->pm.prog);
 483    }
 484
 485    nouveau_bo_ref(NULL, &screen->code);
 486    nouveau_bo_ref(NULL, &screen->tls_bo);
 487    nouveau_bo_ref(NULL, &screen->stack_bo);
 488    nouveau_bo_ref(NULL, &screen->txc);
 489    nouveau_bo_ref(NULL, &screen->uniforms);
 490    nouveau_bo_ref(NULL, &screen->fence.bo);
 491
 492    nouveau_heap_destroy(&screen->vp_code_heap);
 493    nouveau_heap_destroy(&screen->gp_code_heap);
 494    nouveau_heap_destroy(&screen->fp_code_heap);
 495
 496    FREE(screen->tic.entries);
 497
 498    nouveau_object_del(&screen->tesla);
 499    nouveau_object_del(&screen->eng2d);
 500    nouveau_object_del(&screen->m2mf);
 501    nouveau_object_del(&screen->compute);
 502    nouveau_object_del(&screen->sync);
 503
 504    nouveau_screen_fini(&screen->base);
 505
 506    FREE(screen);
 507 }
 508
 509 static void
 510 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 511 {
 512    struct nv50_screen *screen = nv50_screen(pscreen);
 513    struct nouveau_pushbuf *push = screen->base.pushbuf;
 514
 515    /* we need to do it after possible flush in MARK_RING */
 516    *sequence = ++screen->base.fence.sequence;
 517
 518    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 519    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 520    PUSH_DATAh(push, screen->fence.bo->offset);
 521    PUSH_DATA (push, screen->fence.bo->offset);
 522    PUSH_DATA (push, *sequence);
 523    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 524                     NV50_3D_QUERY_GET_UNK4 |
 525                     NV50_3D_QUERY_GET_UNIT_CROP |
 526                     NV50_3D_QUERY_GET_TYPE_QUERY |
 527                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 528                     NV50_3D_QUERY_GET_SHORT);
 529 }
 530
 531 static u32
 532 nv50_screen_fence_update(struct pipe_screen *pscreen)
 533 {
 534    return nv50_screen(pscreen)->fence.map[0];
 535 }
 536
 537 static void
 538 nv50_screen_init_hwctx(struct nv50_screen *screen)
 539 {
 540    struct nouveau_pushbuf *push = screen->base.pushbuf;
 541    struct nv04_fifo *fifo;
 542    unsigned i;
 543
 544    fifo = (struct nv04_fifo *)screen->base.channel->data;
 545
 546    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 547    PUSH_DATA (push, screen->m2mf->handle);
 548    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 549    PUSH_DATA (push, screen->sync->handle);
 550    PUSH_DATA (push, fifo->vram);
 551    PUSH_DATA (push, fifo->vram);
 552
 553    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 554    PUSH_DATA (push, screen->eng2d->handle);
 555    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 556    PUSH_DATA (push, screen->sync->handle);
 557    PUSH_DATA (push, fifo->vram);
 558    PUSH_DATA (push, fifo->vram);
 559    PUSH_DATA (push, fifo->vram);
 560    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 561    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 562    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 563    PUSH_DATA (push, 0);
 564    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 565    PUSH_DATA (push, 0);
 566    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 567    PUSH_DATA (push, 1);
 568    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 569    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 570
 571    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 572    PUSH_DATA (push, screen->tesla->handle);
 573
 574    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 575    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 576
 577    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 578    PUSH_DATA (push, screen->sync->handle);
 579    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 580    for (i = 0; i < 11; ++i)
 581       PUSH_DATA(push, fifo->vram);
 582    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 583    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 584       PUSH_DATA(push, fifo->vram);
 585
 586    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 587    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 588    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 589    PUSH_DATA (push, 0xf);
 590
 591    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 592       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 593       PUSH_DATA (push, 0x18);
 594    }
 595
 596    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 597    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 598
 599    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 600    for (i = 0; i < 8; ++i)
 601       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 602
 603    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 604    PUSH_DATA (push, 1);
 605
 606    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 607    PUSH_DATA (push, 0);
 608    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 609    PUSH_DATA (push, 0);
 610    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 611    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 612    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 613    PUSH_DATA (push, 0);
 614    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 615    PUSH_DATA (push, 1);
 616    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 617    PUSH_DATA (push, 1);
 618
 619    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 620       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 621       PUSH_DATA (push, 0);
 622    }
 623
 624    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 625    PUSH_DATA (push, 0);
 626    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 627    PUSH_DATA (push, 0);
 628    PUSH_DATA (push, 0);
 629    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 630    PUSH_DATA (push, 0x3f);
 631
 632    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 633    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 634    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 635
 636    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 637    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 638    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 639
 640    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 641    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 642    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 643
 644    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 645    PUSH_DATAh(push, screen->tls_bo->offset);
 646    PUSH_DATA (push, screen->tls_bo->offset);
 647    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 648
 649    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 650    PUSH_DATAh(push, screen->stack_bo->offset);
 651    PUSH_DATA (push, screen->stack_bo->offset);
 652    PUSH_DATA (push, 4);
 653
 654    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 655    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 656    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 657    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 658
 659    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 660    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 661    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 662    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 663
 664    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 665    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 666    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 667    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 668
 669    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 670    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 671    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 672    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 673
 674    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 675    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 676    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 677    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 678
 679    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 680    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 681    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 682    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 683    PUSH_DATAf(push, 0.0f);
 684    PUSH_DATAf(push, 0.0f);
 685    PUSH_DATAf(push, 0.0f);
 686    PUSH_DATAf(push, 0.0f);
 687    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 688    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 689    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 690
 691    nv50_upload_ms_info(push);
 692
 693    /* max TIC (bits 4:8) & TSC bindings, per program type */
 694    for (i = 0; i < 3; ++i) {
 695       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 696       PUSH_DATA (push, 0x54);
 697    }
 698
 699    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 700    PUSH_DATAh(push, screen->txc->offset);
 701    PUSH_DATA (push, screen->txc->offset);
 702    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 703
 704    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 705    PUSH_DATAh(push, screen->txc->offset + 65536);
 706    PUSH_DATA (push, screen->txc->offset + 65536);
 707    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 708
 709    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 710    PUSH_DATA (push, 0);
 711
 712    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 713    PUSH_DATA (push, 0);
 714    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 715    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 716    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 717    for (i = 0; i < 8 * 2; ++i)
 718       PUSH_DATA(push, 0);
 719    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 720    PUSH_DATA (push, 0);
 721
 722    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 723    PUSH_DATA (push, 1);
 724    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 725       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 726       PUSH_DATAf(push, 0.0f);
 727       PUSH_DATAf(push, 1.0f);
 728       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 729       PUSH_DATA (push, 8192 << 16);
 730       PUSH_DATA (push, 8192 << 16);
 731    }
 732
 733    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 734 #ifdef NV50_SCISSORS_CLIPPING
 735    PUSH_DATA (push, 0x0000);
 736 #else
 737    PUSH_DATA (push, 0x1080);
 738 #endif
 739
 740    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 741    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 742
 743    /* We use scissors instead of exact view volume clipping,
 744     * so they're always enabled.
 745     */
 746    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 747       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 748       PUSH_DATA (push, 1);
 749       PUSH_DATA (push, 8192 << 16);
 750       PUSH_DATA (push, 8192 << 16);
 751    }
 752
 753    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 754    PUSH_DATA (push, 1);
 755    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 756    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 757    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 758    PUSH_DATA (push, 0x11111111);
 759    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 760    PUSH_DATA (push, 1);
 761
 762    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 763    PUSH_DATA (push, 0);
 764    if (screen->base.class_3d >= NV84_3D_CLASS) {
 765       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 766       PUSH_DATA (push, 0);
 767    }
 768
 769    PUSH_KICK (push);
 770 }
 771
 772 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 773       uint64_t *tls_size)
 774 {
 775    struct nouveau_device *dev = screen->base.device;
 776    int ret;
 777
 778    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 779          ONE_TEMP_SIZE;
 780    if (nouveau_mesa_debug)
 781       debug_printf("allocating space for %u temps\n",
 782             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 783    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 784          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 785
 786    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 787                         *tls_size, NULL, &screen->tls_bo);
 788    if (ret) {
 789       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 790       return ret;
 791    }
 792
 793    return 0;
 794 }
 795
 796 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 797 {
 798    struct nouveau_pushbuf *push = screen->base.pushbuf;
 799    int ret;
 800    uint64_t tls_size;
 801
 802    if (tls_space < screen->cur_tls_space)
 803       return 0;
 804    if (tls_space > screen->max_tls_space) {
 805       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 806        * LOCAL_WARPS_NO_CLAMP) */
 807       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 808             (unsigned)(tls_space / ONE_TEMP_SIZE),
 809             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 810       return -ENOMEM;
 811    }
 812
 813    nouveau_bo_ref(NULL, &screen->tls_bo);
 814    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 815    if (ret)
 816       return ret;
 817
 818    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 819    PUSH_DATAh(push, screen->tls_bo->offset);
 820    PUSH_DATA (push, screen->tls_bo->offset);
 821    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 822
 823    return 1;
 824 }
 825
 826 struct nouveau_screen *
 827 nv50_screen_create(struct nouveau_device *dev)
 828 {
 829    struct nv50_screen *screen;
 830    struct pipe_screen *pscreen;
 831    struct nouveau_object *chan;
 832    uint64_t value;
 833    uint32_t tesla_class;
 834    unsigned stack_size;
 835    int ret;
 836
 837    screen = CALLOC_STRUCT(nv50_screen);
 838    if (!screen)
 839       return NULL;
 840    pscreen = &screen->base.base;
 841    pscreen->destroy = nv50_screen_destroy;
 842
 843    ret = nouveau_screen_init(&screen->base, dev);
 844    if (ret) {
 845       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 846       goto fail;
 847    }
 848
 849    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 850     *  admit them to VRAM.
 851     */
 852    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 853       PIPE_BIND_VERTEX_BUFFER;
 854    screen->base.sysmem_bindings |=
 855       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 856
 857    screen->base.pushbuf->user_priv = screen;
 858    screen->base.pushbuf->rsvd_kick = 5;
 859
 860    chan = screen->base.channel;
 861
 862    pscreen->context_create = nv50_create;
 863    pscreen->is_format_supported = nv50_screen_is_format_supported;
 864    pscreen->get_param = nv50_screen_get_param;
 865    pscreen->get_shader_param = nv50_screen_get_shader_param;
 866    pscreen->get_paramf = nv50_screen_get_paramf;
 867    pscreen->get_compute_param = nv50_screen_get_compute_param;
 868    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 869    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 870
 871    nv50_screen_init_resource_functions(pscreen);
 872
 873    if (screen->base.device->chipset < 0x84 ||
 874        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 875       /* PMPEG */
 876       nouveau_screen_init_vdec(&screen->base);
 877    } else if (screen->base.device->chipset < 0x98 ||
 878               screen->base.device->chipset == 0xa0) {
 879       /* VP2 */
 880       screen->base.base.get_video_param = nv84_screen_get_video_param;
 881       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 882    } else {
 883       /* VP3/4 */
 884       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 885       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 886    }
 887
 888    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 889                         NULL, &screen->fence.bo);
 890    if (ret) {
 891       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 892       goto fail;
 893    }
 894
 895    nouveau_bo_map(screen->fence.bo, 0, NULL);
 896    screen->fence.map = screen->fence.bo->map;
 897    screen->base.fence.emit = nv50_screen_fence_emit;
 898    screen->base.fence.update = nv50_screen_fence_update;
 899
 900    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 901                             &(struct nv04_notify){ .length = 32 },
 902                             sizeof(struct nv04_notify), &screen->sync);
 903    if (ret) {
 904       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 905       goto fail;
 906    }
 907
 908    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 909                             NULL, 0, &screen->m2mf);
 910    if (ret) {
 911       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 912       goto fail;
 913    }
 914
 915    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 916                             NULL, 0, &screen->eng2d);
 917    if (ret) {
 918       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 919       goto fail;
 920    }
 921
 922    switch (dev->chipset & 0xf0) {
 923    case 0x50:
 924       tesla_class = NV50_3D_CLASS;
 925       break;
 926    case 0x80:
 927    case 0x90:
 928       tesla_class = NV84_3D_CLASS;
 929       break;
 930    case 0xa0:
 931       switch (dev->chipset) {
 932       case 0xa0:
 933       case 0xaa:
 934       case 0xac:
 935          tesla_class = NVA0_3D_CLASS;
 936          break;
 937       case 0xaf:
 938          tesla_class = NVAF_3D_CLASS;
 939          break;
 940       default:
 941          tesla_class = NVA3_3D_CLASS;
 942          break;
 943       }
 944       break;
 945    default:
 946       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 947       goto fail;
 948    }
 949    screen->base.class_3d = tesla_class;
 950
 951    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 952                             NULL, 0, &screen->tesla);
 953    if (ret) {
 954       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 955       goto fail;
 956    }
 957
 958    /* This over-allocates by a page. The GP, which would execute at the end of
 959     * the last page, would trigger faults. The going theory is that it
 960     * prefetches up to a certain amount.
 961     */
 962    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 963                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 964                         NULL, &screen->code);
 965    if (ret) {
 966       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 967       goto fail;
 968    }
 969
 970    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 971    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 972    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 973
 974    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 975
 976    screen->TPs = util_bitcount(value & 0xffff);
 977    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 978
 979    screen->mp_count = screen->TPs * screen->MPsInTP;
 980
 981    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 982          STACK_WARPS_ALLOC * 64 * 8;
 983
 984    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 985                         &screen->stack_bo);
 986    if (ret) {
 987       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 988       goto fail;
 989    }
 990
 991    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 992          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 993          ONE_TEMP_SIZE;
 994    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 995    screen->max_tls_space /= 2; /* half of vram */
 996
 997    /* hw can address max 64 KiB */
 998    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 999
1000    uint64_t tls_size;
1001    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1002    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1003    if (ret)
1004       goto fail;
1005
1006    if (nouveau_mesa_debug)
1007       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1008             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1009
1010    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1011                         &screen->uniforms);
1012    if (ret) {
1013       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1014       goto fail;
1015    }
1016
1017    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1018                         &screen->txc);
1019    if (ret) {
1020       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1021       goto fail;
1022    }
1023
1024    screen->tic.entries = CALLOC(4096, sizeof(void *));
1025    screen->tsc.entries = screen->tic.entries + 2048;
1026
1027    if (!nv50_blitter_create(screen))
1028       goto fail;
1029
1030    nv50_screen_init_hwctx(screen);
1031
1032    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1033    if (ret) {
1034       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1035       goto fail;
1036    }
1037
1038    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1039
1040    return &screen->base;
1041
1042 fail:
1043    screen->base.base.context_create = NULL;
1044    return &screen->base;
1045 }
1046
1047 int
1048 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1049 {
1050    int i = screen->tic.next;
1051
1052    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1053       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1054
1055    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1056
1057    if (screen->tic.entries[i])
1058       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1059
1060    screen->tic.entries[i] = entry;
1061    return i;
1062 }
1063
1064 int
1065 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1066 {
1067    int i = screen->tsc.next;
1068
1069    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1070       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1071
1072    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1073
1074    if (screen->tsc.entries[i])
1075       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1076
1077    screen->tsc.entries[i] = entry;
1078    return i;
1079 }