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825e0ba49978704e19d753a75a9c2f0a04635613
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <errno.h>
24 #include <xf86drm.h>
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nv_object.xml.h"
36
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
41
42 #define THREADS_IN_WARP 32
43
44 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
45
46 static boolean
47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
48 enum pipe_format format,
49 enum pipe_texture_target target,
50 unsigned sample_count,
51 unsigned bindings)
52 {
53 if (sample_count > 8)
54 return FALSE;
55 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
56 return FALSE;
57 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
58 return FALSE;
59
60 if (!util_format_is_supported(format, bindings))
61 return FALSE;
62
63 switch (format) {
64 case PIPE_FORMAT_Z16_UNORM:
65 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
66 return FALSE;
67 break;
68 default:
69 break;
70 }
71
72 /* transfers & shared are always supported */
73 bindings &= ~(PIPE_BIND_TRANSFER_READ |
74 PIPE_BIND_TRANSFER_WRITE |
75 PIPE_BIND_SHARED);
76
77 return (nv50_format_table[format].usage & bindings) == bindings;
78 }
79
80 static int
81 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
82 {
83 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
84 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
85
86 switch (param) {
87 /* non-boolean caps */
88 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
89 return 14;
90 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
91 return 12;
92 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
93 return 14;
94 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
95 return 512;
96 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
97 case PIPE_CAP_MIN_TEXEL_OFFSET:
98 return -8;
99 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
100 case PIPE_CAP_MAX_TEXEL_OFFSET:
101 return 7;
102 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
103 return 65536;
104 case PIPE_CAP_GLSL_FEATURE_LEVEL:
105 return 330;
106 case PIPE_CAP_MAX_RENDER_TARGETS:
107 return 8;
108 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
109 return 1;
110 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
111 return 4;
112 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
113 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
114 return 64;
115 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
116 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
117 return 1024;
118 case PIPE_CAP_MAX_VERTEX_STREAMS:
119 return 1;
120 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
121 return 2048;
122 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
123 return 256;
124 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
125 return 1; /* 256 for binding as RT, but that's not possible in GL */
126 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
127 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
128 case PIPE_CAP_MAX_VIEWPORTS:
129 return NV50_MAX_VIEWPORTS;
130 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
131 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
132 case PIPE_CAP_ENDIANNESS:
133 return PIPE_ENDIAN_LITTLE;
134 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
135 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
136
137 /* supported caps */
138 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
139 case PIPE_CAP_TEXTURE_SWIZZLE:
140 case PIPE_CAP_TEXTURE_SHADOW_MAP:
141 case PIPE_CAP_NPOT_TEXTURES:
142 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
143 case PIPE_CAP_ANISOTROPIC_FILTER:
144 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
145 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
146 case PIPE_CAP_TWO_SIDED_STENCIL:
147 case PIPE_CAP_DEPTH_CLIP_DISABLE:
148 case PIPE_CAP_POINT_SPRITE:
149 case PIPE_CAP_SM3:
150 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
151 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
152 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
153 case PIPE_CAP_QUERY_TIMESTAMP:
154 case PIPE_CAP_QUERY_TIME_ELAPSED:
155 case PIPE_CAP_OCCLUSION_QUERY:
156 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
157 case PIPE_CAP_INDEP_BLEND_ENABLE:
158 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
159 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
160 case PIPE_CAP_PRIMITIVE_RESTART:
161 case PIPE_CAP_TGSI_INSTANCEID:
162 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
163 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
164 case PIPE_CAP_CONDITIONAL_RENDER:
165 case PIPE_CAP_TEXTURE_BARRIER:
166 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
167 case PIPE_CAP_START_INSTANCE:
168 case PIPE_CAP_USER_CONSTANT_BUFFERS:
169 case PIPE_CAP_USER_INDEX_BUFFERS:
170 case PIPE_CAP_USER_VERTEX_BUFFERS:
171 case PIPE_CAP_TEXTURE_MULTISAMPLE:
172 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
173 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
174 case PIPE_CAP_SAMPLER_VIEW_TARGET:
175 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
176 return 1;
177 case PIPE_CAP_SEAMLESS_CUBE_MAP:
178 return 1; /* class_3d >= NVA0_3D_CLASS; */
179 /* supported on nva0+ */
180 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
181 return class_3d >= NVA0_3D_CLASS;
182 /* supported on nva3+ */
183 case PIPE_CAP_CUBE_MAP_ARRAY:
184 case PIPE_CAP_INDEP_BLEND_FUNC:
185 case PIPE_CAP_TEXTURE_QUERY_LOD:
186 case PIPE_CAP_SAMPLE_SHADING:
187 return class_3d >= NVA3_3D_CLASS;
188
189 /* unsupported caps */
190 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
191 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
192 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
193 case PIPE_CAP_SHADER_STENCIL_EXPORT:
194 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
195 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
196 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
197 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
198 case PIPE_CAP_TGSI_TEXCOORD:
199 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
200 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
201 case PIPE_CAP_TEXTURE_GATHER_SM5:
202 case PIPE_CAP_FAKE_SW_MSAA:
203 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
204 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
205 case PIPE_CAP_COMPUTE:
206 case PIPE_CAP_DRAW_INDIRECT:
207 case PIPE_CAP_CLIP_HALFZ:
208 return 0;
209
210 case PIPE_CAP_VENDOR_ID:
211 return 0x10de;
212 case PIPE_CAP_DEVICE_ID: {
213 uint64_t device_id;
214 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
215 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
216 return -1;
217 }
218 return device_id;
219 }
220 case PIPE_CAP_ACCELERATED:
221 return 1;
222 case PIPE_CAP_VIDEO_MEMORY:
223 return dev->vram_size >> 20;
224 case PIPE_CAP_UMA:
225 return 0;
226 }
227
228 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
229 return 0;
230 }
231
232 static int
233 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
234 enum pipe_shader_cap param)
235 {
236 switch (shader) {
237 case PIPE_SHADER_VERTEX:
238 case PIPE_SHADER_GEOMETRY:
239 case PIPE_SHADER_FRAGMENT:
240 break;
241 default:
242 return 0;
243 }
244
245 switch (param) {
246 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
247 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
248 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
249 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
250 return 16384;
251 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
252 return 4;
253 case PIPE_SHADER_CAP_MAX_INPUTS:
254 if (shader == PIPE_SHADER_VERTEX)
255 return 32;
256 return 15;
257 case PIPE_SHADER_CAP_MAX_OUTPUTS:
258 return 16;
259 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
260 return 65536;
261 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
262 return NV50_MAX_PIPE_CONSTBUFS;
263 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
264 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
265 return shader != PIPE_SHADER_FRAGMENT;
266 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
267 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
268 return 1;
269 case PIPE_SHADER_CAP_MAX_PREDS:
270 return 0;
271 case PIPE_SHADER_CAP_MAX_TEMPS:
272 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
273 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
274 return 1;
275 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
276 return 0;
277 case PIPE_SHADER_CAP_SUBROUTINES:
278 return 0; /* please inline, or provide function declarations */
279 case PIPE_SHADER_CAP_INTEGERS:
280 return 1;
281 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
282 /* The chip could handle more sampler views than samplers */
283 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
284 return MIN2(32, PIPE_MAX_SAMPLERS);
285 default:
286 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
287 return 0;
288 }
289 }
290
291 static float
292 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
293 {
294 switch (param) {
295 case PIPE_CAPF_MAX_LINE_WIDTH:
296 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
297 return 10.0f;
298 case PIPE_CAPF_MAX_POINT_WIDTH:
299 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
300 return 64.0f;
301 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
302 return 16.0f;
303 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
304 return 4.0f;
305 case PIPE_CAPF_GUARD_BAND_LEFT:
306 case PIPE_CAPF_GUARD_BAND_TOP:
307 return 0.0f;
308 case PIPE_CAPF_GUARD_BAND_RIGHT:
309 case PIPE_CAPF_GUARD_BAND_BOTTOM:
310 return 0.0f; /* that or infinity */
311 }
312
313 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
314 return 0.0f;
315 }
316
317 static void
318 nv50_screen_destroy(struct pipe_screen *pscreen)
319 {
320 struct nv50_screen *screen = nv50_screen(pscreen);
321
322 if (!nouveau_drm_screen_unref(&screen->base))
323 return;
324
325 if (screen->base.fence.current) {
326 struct nouveau_fence *current = NULL;
327
328 /* nouveau_fence_wait will create a new current fence, so wait on the
329 * _current_ one, and remove both.
330 */
331 nouveau_fence_ref(screen->base.fence.current, &current);
332 nouveau_fence_wait(current);
333 nouveau_fence_ref(NULL, &current);
334 nouveau_fence_ref(NULL, &screen->base.fence.current);
335 }
336 if (screen->base.pushbuf)
337 screen->base.pushbuf->user_priv = NULL;
338
339 if (screen->blitter)
340 nv50_blitter_destroy(screen);
341
342 nouveau_bo_ref(NULL, &screen->code);
343 nouveau_bo_ref(NULL, &screen->tls_bo);
344 nouveau_bo_ref(NULL, &screen->stack_bo);
345 nouveau_bo_ref(NULL, &screen->txc);
346 nouveau_bo_ref(NULL, &screen->uniforms);
347 nouveau_bo_ref(NULL, &screen->fence.bo);
348
349 nouveau_heap_destroy(&screen->vp_code_heap);
350 nouveau_heap_destroy(&screen->gp_code_heap);
351 nouveau_heap_destroy(&screen->fp_code_heap);
352
353 FREE(screen->tic.entries);
354
355 nouveau_object_del(&screen->tesla);
356 nouveau_object_del(&screen->eng2d);
357 nouveau_object_del(&screen->m2mf);
358 nouveau_object_del(&screen->sync);
359
360 nouveau_screen_fini(&screen->base);
361
362 FREE(screen);
363 }
364
365 static void
366 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
367 {
368 struct nv50_screen *screen = nv50_screen(pscreen);
369 struct nouveau_pushbuf *push = screen->base.pushbuf;
370
371 /* we need to do it after possible flush in MARK_RING */
372 *sequence = ++screen->base.fence.sequence;
373
374 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
375 PUSH_DATAh(push, screen->fence.bo->offset);
376 PUSH_DATA (push, screen->fence.bo->offset);
377 PUSH_DATA (push, *sequence);
378 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
379 NV50_3D_QUERY_GET_UNK4 |
380 NV50_3D_QUERY_GET_UNIT_CROP |
381 NV50_3D_QUERY_GET_TYPE_QUERY |
382 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
383 NV50_3D_QUERY_GET_SHORT);
384 }
385
386 static u32
387 nv50_screen_fence_update(struct pipe_screen *pscreen)
388 {
389 return nv50_screen(pscreen)->fence.map[0];
390 }
391
392 static void
393 nv50_screen_init_hwctx(struct nv50_screen *screen)
394 {
395 struct nouveau_pushbuf *push = screen->base.pushbuf;
396 struct nv04_fifo *fifo;
397 unsigned i;
398
399 fifo = (struct nv04_fifo *)screen->base.channel->data;
400
401 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
402 PUSH_DATA (push, screen->m2mf->handle);
403 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
404 PUSH_DATA (push, screen->sync->handle);
405 PUSH_DATA (push, fifo->vram);
406 PUSH_DATA (push, fifo->vram);
407
408 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
409 PUSH_DATA (push, screen->eng2d->handle);
410 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
411 PUSH_DATA (push, screen->sync->handle);
412 PUSH_DATA (push, fifo->vram);
413 PUSH_DATA (push, fifo->vram);
414 PUSH_DATA (push, fifo->vram);
415 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
416 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
417 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
418 PUSH_DATA (push, 0);
419 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
420 PUSH_DATA (push, 0);
421 BEGIN_NV04(push, SUBC_2D(0x0888), 1);
422 PUSH_DATA (push, 1);
423 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
424 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
425
426 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
427 PUSH_DATA (push, screen->tesla->handle);
428
429 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
430 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
431
432 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
433 PUSH_DATA (push, screen->sync->handle);
434 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
435 for (i = 0; i < 11; ++i)
436 PUSH_DATA(push, fifo->vram);
437 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
438 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
439 PUSH_DATA(push, fifo->vram);
440
441 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
442 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
443 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
444 PUSH_DATA (push, 0xf);
445
446 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
447 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
448 PUSH_DATA (push, 0x18);
449 }
450
451 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
452 PUSH_DATA (push, 1);
453
454 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
455 PUSH_DATA (push, 0);
456 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
457 PUSH_DATA (push, 0);
458 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
459 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
460 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
461 PUSH_DATA (push, 0);
462 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
463 PUSH_DATA (push, 1);
464 BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
465 PUSH_DATA (push, 0);
466 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
467 PUSH_DATA (push, 1);
468
469 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
470 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
471 PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
472 }
473
474 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
475 PUSH_DATA (push, 0);
476 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
477 PUSH_DATA (push, 0);
478 PUSH_DATA (push, 0);
479 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
480 PUSH_DATA (push, 0x3f);
481
482 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
483 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
484 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
485
486 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
487 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
488 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
489
490 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
491 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
492 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
493
494 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
495 PUSH_DATAh(push, screen->tls_bo->offset);
496 PUSH_DATA (push, screen->tls_bo->offset);
497 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
498
499 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
500 PUSH_DATAh(push, screen->stack_bo->offset);
501 PUSH_DATA (push, screen->stack_bo->offset);
502 PUSH_DATA (push, 4);
503
504 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
505 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
506 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
507 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
508
509 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
510 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
511 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
512 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
513
514 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
515 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
516 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
517 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
518
519 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
520 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
521 PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
522 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
523
524 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
525 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
526 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
527 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
528
529 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
530 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
531 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
532 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
533 PUSH_DATAf(push, 0.0f);
534 PUSH_DATAf(push, 0.0f);
535 PUSH_DATAf(push, 0.0f);
536 PUSH_DATAf(push, 0.0f);
537 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
538 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
539 PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
540
541 nv50_upload_ms_info(push);
542
543 /* max TIC (bits 4:8) & TSC bindings, per program type */
544 for (i = 0; i < 3; ++i) {
545 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
546 PUSH_DATA (push, 0x54);
547 }
548
549 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
550 PUSH_DATAh(push, screen->txc->offset);
551 PUSH_DATA (push, screen->txc->offset);
552 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
553
554 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
555 PUSH_DATAh(push, screen->txc->offset + 65536);
556 PUSH_DATA (push, screen->txc->offset + 65536);
557 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
558
559 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
560 PUSH_DATA (push, 0);
561
562 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
563 PUSH_DATA (push, 0);
564 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
565 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
566 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
567 for (i = 0; i < 8 * 2; ++i)
568 PUSH_DATA(push, 0);
569 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
570 PUSH_DATA (push, 0);
571
572 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
573 PUSH_DATA (push, 1);
574 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
575 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
576 PUSH_DATAf(push, 0.0f);
577 PUSH_DATAf(push, 1.0f);
578 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
579 PUSH_DATA (push, 8192 << 16);
580 PUSH_DATA (push, 8192 << 16);
581 }
582
583 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
584 #ifdef NV50_SCISSORS_CLIPPING
585 PUSH_DATA (push, 0x0000);
586 #else
587 PUSH_DATA (push, 0x1080);
588 #endif
589
590 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
591 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
592
593 /* We use scissors instead of exact view volume clipping,
594 * so they're always enabled.
595 */
596 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
597 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
598 PUSH_DATA (push, 1);
599 PUSH_DATA (push, 8192 << 16);
600 PUSH_DATA (push, 8192 << 16);
601 }
602
603 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
604 PUSH_DATA (push, 1);
605 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
606 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
607 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
608 PUSH_DATA (push, 0x11111111);
609 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
610 PUSH_DATA (push, 1);
611
612 PUSH_KICK (push);
613 }
614
615 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
616 uint64_t *tls_size)
617 {
618 struct nouveau_device *dev = screen->base.device;
619 int ret;
620
621 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
622 ONE_TEMP_SIZE;
623 if (nouveau_mesa_debug)
624 debug_printf("allocating space for %u temps\n",
625 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
626 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
627 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
628
629 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
630 *tls_size, NULL, &screen->tls_bo);
631 if (ret) {
632 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
633 return ret;
634 }
635
636 return 0;
637 }
638
639 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
640 {
641 struct nouveau_pushbuf *push = screen->base.pushbuf;
642 int ret;
643 uint64_t tls_size;
644
645 if (tls_space < screen->cur_tls_space)
646 return 0;
647 if (tls_space > screen->max_tls_space) {
648 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
649 * LOCAL_WARPS_NO_CLAMP) */
650 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
651 (unsigned)(tls_space / ONE_TEMP_SIZE),
652 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
653 return -ENOMEM;
654 }
655
656 nouveau_bo_ref(NULL, &screen->tls_bo);
657 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
658 if (ret)
659 return ret;
660
661 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
662 PUSH_DATAh(push, screen->tls_bo->offset);
663 PUSH_DATA (push, screen->tls_bo->offset);
664 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
665
666 return 1;
667 }
668
669 struct pipe_screen *
670 nv50_screen_create(struct nouveau_device *dev)
671 {
672 struct nv50_screen *screen;
673 struct pipe_screen *pscreen;
674 struct nouveau_object *chan;
675 uint64_t value;
676 uint32_t tesla_class;
677 unsigned stack_size;
678 int ret;
679
680 screen = CALLOC_STRUCT(nv50_screen);
681 if (!screen)
682 return NULL;
683 pscreen = &screen->base.base;
684
685 ret = nouveau_screen_init(&screen->base, dev);
686 if (ret) {
687 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
688 goto fail;
689 }
690
691 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
692 * admit them to VRAM.
693 */
694 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
695 PIPE_BIND_VERTEX_BUFFER;
696 screen->base.sysmem_bindings |=
697 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
698
699 screen->base.pushbuf->user_priv = screen;
700 screen->base.pushbuf->rsvd_kick = 5;
701
702 chan = screen->base.channel;
703
704 pscreen->destroy = nv50_screen_destroy;
705 pscreen->context_create = nv50_create;
706 pscreen->is_format_supported = nv50_screen_is_format_supported;
707 pscreen->get_param = nv50_screen_get_param;
708 pscreen->get_shader_param = nv50_screen_get_shader_param;
709 pscreen->get_paramf = nv50_screen_get_paramf;
710
711 nv50_screen_init_resource_functions(pscreen);
712
713 if (screen->base.device->chipset < 0x84 ||
714 debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
715 /* PMPEG */
716 nouveau_screen_init_vdec(&screen->base);
717 } else if (screen->base.device->chipset < 0x98 ||
718 screen->base.device->chipset == 0xa0) {
719 /* VP2 */
720 screen->base.base.get_video_param = nv84_screen_get_video_param;
721 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
722 } else {
723 /* VP3/4 */
724 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
725 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
726 }
727
728 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
729 NULL, &screen->fence.bo);
730 if (ret) {
731 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
732 goto fail;
733 }
734
735 nouveau_bo_map(screen->fence.bo, 0, NULL);
736 screen->fence.map = screen->fence.bo->map;
737 screen->base.fence.emit = nv50_screen_fence_emit;
738 screen->base.fence.update = nv50_screen_fence_update;
739
740 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
741 &(struct nv04_notify){ .length = 32 },
742 sizeof(struct nv04_notify), &screen->sync);
743 if (ret) {
744 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
745 goto fail;
746 }
747
748 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
749 NULL, 0, &screen->m2mf);
750 if (ret) {
751 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
752 goto fail;
753 }
754
755 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
756 NULL, 0, &screen->eng2d);
757 if (ret) {
758 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
759 goto fail;
760 }
761
762 switch (dev->chipset & 0xf0) {
763 case 0x50:
764 tesla_class = NV50_3D_CLASS;
765 break;
766 case 0x80:
767 case 0x90:
768 tesla_class = NV84_3D_CLASS;
769 break;
770 case 0xa0:
771 switch (dev->chipset) {
772 case 0xa0:
773 case 0xaa:
774 case 0xac:
775 tesla_class = NVA0_3D_CLASS;
776 break;
777 case 0xaf:
778 tesla_class = NVAF_3D_CLASS;
779 break;
780 default:
781 tesla_class = NVA3_3D_CLASS;
782 break;
783 }
784 break;
785 default:
786 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
787 goto fail;
788 }
789 screen->base.class_3d = tesla_class;
790
791 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
792 NULL, 0, &screen->tesla);
793 if (ret) {
794 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
795 goto fail;
796 }
797
798 /* This over-allocates by a page. The GP, which would execute at the end of
799 * the last page, would trigger faults. The going theory is that it
800 * prefetches up to a certain amount.
801 */
802 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
803 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
804 NULL, &screen->code);
805 if (ret) {
806 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
807 goto fail;
808 }
809
810 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
811 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
812 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
813
814 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
815
816 screen->TPs = util_bitcount(value & 0xffff);
817 screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
818
819 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
820 STACK_WARPS_ALLOC * 64 * 8;
821
822 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
823 &screen->stack_bo);
824 if (ret) {
825 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
826 goto fail;
827 }
828
829 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
830 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
831 ONE_TEMP_SIZE;
832 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
833 screen->max_tls_space /= 2; /* half of vram */
834
835 /* hw can address max 64 KiB */
836 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
837
838 uint64_t tls_size;
839 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
840 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
841 if (ret)
842 goto fail;
843
844 if (nouveau_mesa_debug)
845 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
846 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
847
848 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
849 &screen->uniforms);
850 if (ret) {
851 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
852 goto fail;
853 }
854
855 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
856 &screen->txc);
857 if (ret) {
858 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
859 goto fail;
860 }
861
862 screen->tic.entries = CALLOC(4096, sizeof(void *));
863 screen->tsc.entries = screen->tic.entries + 2048;
864
865 if (!nv50_blitter_create(screen))
866 goto fail;
867
868 nv50_screen_init_hwctx(screen);
869
870 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
871
872 return pscreen;
873
874 fail:
875 nv50_screen_destroy(pscreen);
876 return NULL;
877 }
878
879 int
880 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
881 {
882 int i = screen->tic.next;
883
884 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
885 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
886
887 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
888
889 if (screen->tic.entries[i])
890 nv50_tic_entry(screen->tic.entries[i])->id = -1;
891
892 screen->tic.entries[i] = entry;
893 return i;
894 }
895
896 int
897 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
898 {
899 int i = screen->tsc.next;
900
901 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
902 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
903
904 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
905
906 if (screen->tsc.entries[i])
907 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
908
909 screen->tsc.entries[i] = entry;
910 return i;
911 }