src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  45
  46 static boolean
  47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  48                                 enum pipe_format format,
  49                                 enum pipe_texture_target target,
  50                                 unsigned sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (sample_count > 8)
  54       return FALSE;
  55    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  56       return FALSE;
  57    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  58       return FALSE;
  59
  60    if (!util_format_is_supported(format, bindings))
  61       return FALSE;
  62
  63    switch (format) {
  64    case PIPE_FORMAT_Z16_UNORM:
  65       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  66          return FALSE;
  67       break;
  68    default:
  69       break;
  70    }
  71
  72    /* transfers & shared are always supported */
  73    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  74                  PIPE_BIND_TRANSFER_WRITE |
  75                  PIPE_BIND_SHARED);
  76
  77    return (nv50_format_table[format].usage & bindings) == bindings;
  78 }
  79
  80 static int
  81 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  82 {
  83    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  84    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  85
  86    switch (param) {
  87    /* non-boolean caps */
  88    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  89       return 14;
  90    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  91       return 12;
  92    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  93       return 14;
  94    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  95       return 512;
  96    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  97    case PIPE_CAP_MIN_TEXEL_OFFSET:
  98       return -8;
  99    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 100    case PIPE_CAP_MAX_TEXEL_OFFSET:
 101       return 7;
 102    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 103       return 65536;
 104    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 105       return 330;
 106    case PIPE_CAP_MAX_RENDER_TARGETS:
 107       return 8;
 108    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 109       return 1;
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 111       return 4;
 112    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 113    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 114       return 64;
 115    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 116    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 117       return 1024;
 118    case PIPE_CAP_MAX_VERTEX_STREAMS:
 119       return 1;
 120    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 121       return 2048;
 122    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 123       return 256;
 124    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 125       return 1; /* 256 for binding as RT, but that's not possible in GL */
 126    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 127       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 128    case PIPE_CAP_MAX_VIEWPORTS:
 129       return NV50_MAX_VIEWPORTS;
 130    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 131       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 132    case PIPE_CAP_ENDIANNESS:
 133       return PIPE_ENDIAN_LITTLE;
 134    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 135       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 136
 137    /* supported caps */
 138    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 139    case PIPE_CAP_TEXTURE_SWIZZLE:
 140    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 141    case PIPE_CAP_NPOT_TEXTURES:
 142    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 143    case PIPE_CAP_ANISOTROPIC_FILTER:
 144    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 145    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 146    case PIPE_CAP_TWO_SIDED_STENCIL:
 147    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 148    case PIPE_CAP_POINT_SPRITE:
 149    case PIPE_CAP_SM3:
 150    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 151    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 152    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 153    case PIPE_CAP_QUERY_TIMESTAMP:
 154    case PIPE_CAP_QUERY_TIME_ELAPSED:
 155    case PIPE_CAP_OCCLUSION_QUERY:
 156    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 157    case PIPE_CAP_INDEP_BLEND_ENABLE:
 158    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 159    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 160    case PIPE_CAP_PRIMITIVE_RESTART:
 161    case PIPE_CAP_TGSI_INSTANCEID:
 162    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 163    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 164    case PIPE_CAP_CONDITIONAL_RENDER:
 165    case PIPE_CAP_TEXTURE_BARRIER:
 166    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 167    case PIPE_CAP_START_INSTANCE:
 168    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 169    case PIPE_CAP_USER_INDEX_BUFFERS:
 170    case PIPE_CAP_USER_VERTEX_BUFFERS:
 171    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 172    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 173    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 174    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 175    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 176    case PIPE_CAP_CLIP_HALFZ:
 177    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 178    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 179       return 1;
 180    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 181       return 1; /* class_3d >= NVA0_3D_CLASS; */
 182    /* supported on nva0+ */
 183    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 184       return class_3d >= NVA0_3D_CLASS;
 185    /* supported on nva3+ */
 186    case PIPE_CAP_CUBE_MAP_ARRAY:
 187    case PIPE_CAP_INDEP_BLEND_FUNC:
 188    case PIPE_CAP_TEXTURE_QUERY_LOD:
 189    case PIPE_CAP_SAMPLE_SHADING:
 190       return class_3d >= NVA3_3D_CLASS;
 191
 192    /* unsupported caps */
 193    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 194    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 195    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 196    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 197    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 198    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 199    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 200    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 201    case PIPE_CAP_TGSI_TEXCOORD:
 202    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 203    case PIPE_CAP_TEXTURE_GATHER_SM5:
 204    case PIPE_CAP_FAKE_SW_MSAA:
 205    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 206    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 207    case PIPE_CAP_COMPUTE:
 208    case PIPE_CAP_DRAW_INDIRECT:
 209    case PIPE_CAP_VERTEXID_NOBASE:
 210    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 211    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 212       return 0;
 213
 214    case PIPE_CAP_VENDOR_ID:
 215       return 0x10de;
 216    case PIPE_CAP_DEVICE_ID: {
 217       uint64_t device_id;
 218       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 219          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 220          return -1;
 221       }
 222       return device_id;
 223    }
 224    case PIPE_CAP_ACCELERATED:
 225       return 1;
 226    case PIPE_CAP_VIDEO_MEMORY:
 227       return dev->vram_size >> 20;
 228    case PIPE_CAP_UMA:
 229       return 0;
 230    }
 231
 232    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 233    return 0;
 234 }
 235
 236 static int
 237 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 238                              enum pipe_shader_cap param)
 239 {
 240    switch (shader) {
 241    case PIPE_SHADER_VERTEX:
 242    case PIPE_SHADER_GEOMETRY:
 243    case PIPE_SHADER_FRAGMENT:
 244       break;
 245    default:
 246       return 0;
 247    }
 248
 249    switch (param) {
 250    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 251    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 252    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 253    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 254       return 16384;
 255    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 256       return 4;
 257    case PIPE_SHADER_CAP_MAX_INPUTS:
 258       if (shader == PIPE_SHADER_VERTEX)
 259          return 32;
 260       return 15;
 261    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 262       return 16;
 263    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 264       return 65536;
 265    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 266       return NV50_MAX_PIPE_CONSTBUFS;
 267    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 268    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 269       return shader != PIPE_SHADER_FRAGMENT;
 270    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 271    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 272       return 1;
 273    case PIPE_SHADER_CAP_MAX_PREDS:
 274       return 0;
 275    case PIPE_SHADER_CAP_MAX_TEMPS:
 276       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 277    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 278       return 1;
 279    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 280       return 0;
 281    case PIPE_SHADER_CAP_SUBROUTINES:
 282       return 0; /* please inline, or provide function declarations */
 283    case PIPE_SHADER_CAP_INTEGERS:
 284       return 1;
 285    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 286       /* The chip could handle more sampler views than samplers */
 287    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 288       return MIN2(32, PIPE_MAX_SAMPLERS);
 289    default:
 290       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 291       return 0;
 292    }
 293 }
 294
 295 static float
 296 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 297 {
 298    switch (param) {
 299    case PIPE_CAPF_MAX_LINE_WIDTH:
 300    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 301       return 10.0f;
 302    case PIPE_CAPF_MAX_POINT_WIDTH:
 303    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 304       return 64.0f;
 305    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 306       return 16.0f;
 307    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 308       return 4.0f;
 309    case PIPE_CAPF_GUARD_BAND_LEFT:
 310    case PIPE_CAPF_GUARD_BAND_TOP:
 311       return 0.0f;
 312    case PIPE_CAPF_GUARD_BAND_RIGHT:
 313    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 314       return 0.0f; /* that or infinity */
 315    }
 316
 317    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 318    return 0.0f;
 319 }
 320
 321 static void
 322 nv50_screen_destroy(struct pipe_screen *pscreen)
 323 {
 324    struct nv50_screen *screen = nv50_screen(pscreen);
 325
 326    if (!nouveau_drm_screen_unref(&screen->base))
 327       return;
 328
 329    if (screen->base.fence.current) {
 330       struct nouveau_fence *current = NULL;
 331
 332       /* nouveau_fence_wait will create a new current fence, so wait on the
 333        * _current_ one, and remove both.
 334        */
 335       nouveau_fence_ref(screen->base.fence.current, &current);
 336       nouveau_fence_wait(current);
 337       nouveau_fence_ref(NULL, &current);
 338       nouveau_fence_ref(NULL, &screen->base.fence.current);
 339    }
 340    if (screen->base.pushbuf)
 341       screen->base.pushbuf->user_priv = NULL;
 342
 343    if (screen->blitter)
 344       nv50_blitter_destroy(screen);
 345
 346    nouveau_bo_ref(NULL, &screen->code);
 347    nouveau_bo_ref(NULL, &screen->tls_bo);
 348    nouveau_bo_ref(NULL, &screen->stack_bo);
 349    nouveau_bo_ref(NULL, &screen->txc);
 350    nouveau_bo_ref(NULL, &screen->uniforms);
 351    nouveau_bo_ref(NULL, &screen->fence.bo);
 352
 353    nouveau_heap_destroy(&screen->vp_code_heap);
 354    nouveau_heap_destroy(&screen->gp_code_heap);
 355    nouveau_heap_destroy(&screen->fp_code_heap);
 356
 357    FREE(screen->tic.entries);
 358
 359    nouveau_object_del(&screen->tesla);
 360    nouveau_object_del(&screen->eng2d);
 361    nouveau_object_del(&screen->m2mf);
 362    nouveau_object_del(&screen->sync);
 363
 364    nouveau_screen_fini(&screen->base);
 365
 366    FREE(screen);
 367 }
 368
 369 static void
 370 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 371 {
 372    struct nv50_screen *screen = nv50_screen(pscreen);
 373    struct nouveau_pushbuf *push = screen->base.pushbuf;
 374
 375    /* we need to do it after possible flush in MARK_RING */
 376    *sequence = ++screen->base.fence.sequence;
 377
 378    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 379    PUSH_DATAh(push, screen->fence.bo->offset);
 380    PUSH_DATA (push, screen->fence.bo->offset);
 381    PUSH_DATA (push, *sequence);
 382    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 383                     NV50_3D_QUERY_GET_UNK4 |
 384                     NV50_3D_QUERY_GET_UNIT_CROP |
 385                     NV50_3D_QUERY_GET_TYPE_QUERY |
 386                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 387                     NV50_3D_QUERY_GET_SHORT);
 388 }
 389
 390 static u32
 391 nv50_screen_fence_update(struct pipe_screen *pscreen)
 392 {
 393    return nv50_screen(pscreen)->fence.map[0];
 394 }
 395
 396 static void
 397 nv50_screen_init_hwctx(struct nv50_screen *screen)
 398 {
 399    struct nouveau_pushbuf *push = screen->base.pushbuf;
 400    struct nv04_fifo *fifo;
 401    unsigned i;
 402
 403    fifo = (struct nv04_fifo *)screen->base.channel->data;
 404
 405    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 406    PUSH_DATA (push, screen->m2mf->handle);
 407    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 408    PUSH_DATA (push, screen->sync->handle);
 409    PUSH_DATA (push, fifo->vram);
 410    PUSH_DATA (push, fifo->vram);
 411
 412    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 413    PUSH_DATA (push, screen->eng2d->handle);
 414    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 415    PUSH_DATA (push, screen->sync->handle);
 416    PUSH_DATA (push, fifo->vram);
 417    PUSH_DATA (push, fifo->vram);
 418    PUSH_DATA (push, fifo->vram);
 419    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 420    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 421    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 422    PUSH_DATA (push, 0);
 423    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 424    PUSH_DATA (push, 0);
 425    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 426    PUSH_DATA (push, 1);
 427    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 428    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 429
 430    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 431    PUSH_DATA (push, screen->tesla->handle);
 432
 433    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 434    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 435
 436    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 437    PUSH_DATA (push, screen->sync->handle);
 438    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 439    for (i = 0; i < 11; ++i)
 440       PUSH_DATA(push, fifo->vram);
 441    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 442    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 443       PUSH_DATA(push, fifo->vram);
 444
 445    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 446    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 447    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 448    PUSH_DATA (push, 0xf);
 449
 450    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 451       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 452       PUSH_DATA (push, 0x18);
 453    }
 454
 455    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 456    PUSH_DATA(push, screen->base.device->drm_version >= 0x01000101);
 457
 458    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 459    for (i = 0; i < 8; ++i)
 460       PUSH_DATA(push, screen->base.device->drm_version >= 0x01000101);
 461
 462    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 463    PUSH_DATA (push, 1);
 464
 465    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 466    PUSH_DATA (push, 0);
 467    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 468    PUSH_DATA (push, 0);
 469    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 470    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 471    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 472    PUSH_DATA (push, 0);
 473    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 474    PUSH_DATA (push, 1);
 475    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 476    PUSH_DATA (push, 1);
 477
 478    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 479       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 480       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 481    }
 482
 483    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 484    PUSH_DATA (push, 0);
 485    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 486    PUSH_DATA (push, 0);
 487    PUSH_DATA (push, 0);
 488    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 489    PUSH_DATA (push, 0x3f);
 490
 491    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 492    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 493    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 494
 495    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 496    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 497    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 498
 499    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 500    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 501    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 502
 503    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 504    PUSH_DATAh(push, screen->tls_bo->offset);
 505    PUSH_DATA (push, screen->tls_bo->offset);
 506    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 507
 508    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 509    PUSH_DATAh(push, screen->stack_bo->offset);
 510    PUSH_DATA (push, screen->stack_bo->offset);
 511    PUSH_DATA (push, 4);
 512
 513    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 514    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 515    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 516    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 517
 518    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 519    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 520    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 521    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 522
 523    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 524    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 525    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 526    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 527
 528    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 529    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 530    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 531    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 532
 533    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 534    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 535    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 536    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 537
 538    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 539    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 540    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 541    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 542    PUSH_DATAf(push, 0.0f);
 543    PUSH_DATAf(push, 0.0f);
 544    PUSH_DATAf(push, 0.0f);
 545    PUSH_DATAf(push, 0.0f);
 546    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 547    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 548    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 549
 550    nv50_upload_ms_info(push);
 551
 552    /* max TIC (bits 4:8) & TSC bindings, per program type */
 553    for (i = 0; i < 3; ++i) {
 554       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 555       PUSH_DATA (push, 0x54);
 556    }
 557
 558    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 559    PUSH_DATAh(push, screen->txc->offset);
 560    PUSH_DATA (push, screen->txc->offset);
 561    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 562
 563    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 564    PUSH_DATAh(push, screen->txc->offset + 65536);
 565    PUSH_DATA (push, screen->txc->offset + 65536);
 566    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 567
 568    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 569    PUSH_DATA (push, 0);
 570
 571    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 572    PUSH_DATA (push, 0);
 573    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 574    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 575    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 576    for (i = 0; i < 8 * 2; ++i)
 577       PUSH_DATA(push, 0);
 578    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 579    PUSH_DATA (push, 0);
 580
 581    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 582    PUSH_DATA (push, 1);
 583    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 584       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 585       PUSH_DATAf(push, 0.0f);
 586       PUSH_DATAf(push, 1.0f);
 587       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 588       PUSH_DATA (push, 8192 << 16);
 589       PUSH_DATA (push, 8192 << 16);
 590    }
 591
 592    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 593 #ifdef NV50_SCISSORS_CLIPPING
 594    PUSH_DATA (push, 0x0000);
 595 #else
 596    PUSH_DATA (push, 0x1080);
 597 #endif
 598
 599    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 600    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 601
 602    /* We use scissors instead of exact view volume clipping,
 603     * so they're always enabled.
 604     */
 605    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 606       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 607       PUSH_DATA (push, 1);
 608       PUSH_DATA (push, 8192 << 16);
 609       PUSH_DATA (push, 8192 << 16);
 610    }
 611
 612    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 613    PUSH_DATA (push, 1);
 614    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 615    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 616    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 617    PUSH_DATA (push, 0x11111111);
 618    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 619    PUSH_DATA (push, 1);
 620
 621    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 622    PUSH_DATA (push, 0);
 623    if (screen->base.class_3d >= NV84_3D_CLASS) {
 624       BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
 625       PUSH_DATA (push, 0);
 626    }
 627
 628    PUSH_KICK (push);
 629 }
 630
 631 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 632       uint64_t *tls_size)
 633 {
 634    struct nouveau_device *dev = screen->base.device;
 635    int ret;
 636
 637    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 638          ONE_TEMP_SIZE;
 639    if (nouveau_mesa_debug)
 640       debug_printf("allocating space for %u temps\n",
 641             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 642    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 643          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 644
 645    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 646                         *tls_size, NULL, &screen->tls_bo);
 647    if (ret) {
 648       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 649       return ret;
 650    }
 651
 652    return 0;
 653 }
 654
 655 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 656 {
 657    struct nouveau_pushbuf *push = screen->base.pushbuf;
 658    int ret;
 659    uint64_t tls_size;
 660
 661    if (tls_space < screen->cur_tls_space)
 662       return 0;
 663    if (tls_space > screen->max_tls_space) {
 664       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 665        * LOCAL_WARPS_NO_CLAMP) */
 666       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 667             (unsigned)(tls_space / ONE_TEMP_SIZE),
 668             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 669       return -ENOMEM;
 670    }
 671
 672    nouveau_bo_ref(NULL, &screen->tls_bo);
 673    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 674    if (ret)
 675       return ret;
 676
 677    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 678    PUSH_DATAh(push, screen->tls_bo->offset);
 679    PUSH_DATA (push, screen->tls_bo->offset);
 680    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 681
 682    return 1;
 683 }
 684
 685 struct pipe_screen *
 686 nv50_screen_create(struct nouveau_device *dev)
 687 {
 688    struct nv50_screen *screen;
 689    struct pipe_screen *pscreen;
 690    struct nouveau_object *chan;
 691    uint64_t value;
 692    uint32_t tesla_class;
 693    unsigned stack_size;
 694    int ret;
 695
 696    screen = CALLOC_STRUCT(nv50_screen);
 697    if (!screen)
 698       return NULL;
 699    pscreen = &screen->base.base;
 700
 701    ret = nouveau_screen_init(&screen->base, dev);
 702    if (ret) {
 703       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 704       goto fail;
 705    }
 706
 707    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 708     *  admit them to VRAM.
 709     */
 710    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 711       PIPE_BIND_VERTEX_BUFFER;
 712    screen->base.sysmem_bindings |=
 713       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 714
 715    screen->base.pushbuf->user_priv = screen;
 716    screen->base.pushbuf->rsvd_kick = 5;
 717
 718    chan = screen->base.channel;
 719
 720    pscreen->destroy = nv50_screen_destroy;
 721    pscreen->context_create = nv50_create;
 722    pscreen->is_format_supported = nv50_screen_is_format_supported;
 723    pscreen->get_param = nv50_screen_get_param;
 724    pscreen->get_shader_param = nv50_screen_get_shader_param;
 725    pscreen->get_paramf = nv50_screen_get_paramf;
 726
 727    nv50_screen_init_resource_functions(pscreen);
 728
 729    if (screen->base.device->chipset < 0x84 ||
 730        debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
 731       /* PMPEG */
 732       nouveau_screen_init_vdec(&screen->base);
 733    } else if (screen->base.device->chipset < 0x98 ||
 734               screen->base.device->chipset == 0xa0) {
 735       /* VP2 */
 736       screen->base.base.get_video_param = nv84_screen_get_video_param;
 737       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 738    } else {
 739       /* VP3/4 */
 740       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 741       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 742    }
 743
 744    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 745                         NULL, &screen->fence.bo);
 746    if (ret) {
 747       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 748       goto fail;
 749    }
 750
 751    nouveau_bo_map(screen->fence.bo, 0, NULL);
 752    screen->fence.map = screen->fence.bo->map;
 753    screen->base.fence.emit = nv50_screen_fence_emit;
 754    screen->base.fence.update = nv50_screen_fence_update;
 755
 756    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 757                             &(struct nv04_notify){ .length = 32 },
 758                             sizeof(struct nv04_notify), &screen->sync);
 759    if (ret) {
 760       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 761       goto fail;
 762    }
 763
 764    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 765                             NULL, 0, &screen->m2mf);
 766    if (ret) {
 767       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 768       goto fail;
 769    }
 770
 771    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 772                             NULL, 0, &screen->eng2d);
 773    if (ret) {
 774       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 775       goto fail;
 776    }
 777
 778    switch (dev->chipset & 0xf0) {
 779    case 0x50:
 780       tesla_class = NV50_3D_CLASS;
 781       break;
 782    case 0x80:
 783    case 0x90:
 784       tesla_class = NV84_3D_CLASS;
 785       break;
 786    case 0xa0:
 787       switch (dev->chipset) {
 788       case 0xa0:
 789       case 0xaa:
 790       case 0xac:
 791          tesla_class = NVA0_3D_CLASS;
 792          break;
 793       case 0xaf:
 794          tesla_class = NVAF_3D_CLASS;
 795          break;
 796       default:
 797          tesla_class = NVA3_3D_CLASS;
 798          break;
 799       }
 800       break;
 801    default:
 802       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 803       goto fail;
 804    }
 805    screen->base.class_3d = tesla_class;
 806
 807    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 808                             NULL, 0, &screen->tesla);
 809    if (ret) {
 810       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 811       goto fail;
 812    }
 813
 814    /* This over-allocates by a page. The GP, which would execute at the end of
 815     * the last page, would trigger faults. The going theory is that it
 816     * prefetches up to a certain amount.
 817     */
 818    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 819                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 820                         NULL, &screen->code);
 821    if (ret) {
 822       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 823       goto fail;
 824    }
 825
 826    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 827    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 828    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 829
 830    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 831
 832    screen->TPs = util_bitcount(value & 0xffff);
 833    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 834
 835    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 836          STACK_WARPS_ALLOC * 64 * 8;
 837
 838    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 839                         &screen->stack_bo);
 840    if (ret) {
 841       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 842       goto fail;
 843    }
 844
 845    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 846          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 847          ONE_TEMP_SIZE;
 848    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 849    screen->max_tls_space /= 2; /* half of vram */
 850
 851    /* hw can address max 64 KiB */
 852    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 853
 854    uint64_t tls_size;
 855    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 856    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 857    if (ret)
 858       goto fail;
 859
 860    if (nouveau_mesa_debug)
 861       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 862             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 863
 864    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 865                         &screen->uniforms);
 866    if (ret) {
 867       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 868       goto fail;
 869    }
 870
 871    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 872                         &screen->txc);
 873    if (ret) {
 874       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 875       goto fail;
 876    }
 877
 878    screen->tic.entries = CALLOC(4096, sizeof(void *));
 879    screen->tsc.entries = screen->tic.entries + 2048;
 880
 881    if (!nv50_blitter_create(screen))
 882       goto fail;
 883
 884    nv50_screen_init_hwctx(screen);
 885
 886    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 887
 888    return pscreen;
 889
 890 fail:
 891    nv50_screen_destroy(pscreen);
 892    return NULL;
 893 }
 894
 895 int
 896 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 897 {
 898    int i = screen->tic.next;
 899
 900    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 901       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 902
 903    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 904
 905    if (screen->tic.entries[i])
 906       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 907
 908    screen->tic.entries[i] = entry;
 909    return i;
 910 }
 911
 912 int
 913 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 914 {
 915    int i = screen->tsc.next;
 916
 917    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 918       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 919
 920    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 921
 922    if (screen->tsc.entries[i])
 923       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 924
 925    screen->tsc.entries[i] = entry;
 926    return i;
 927 }