2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
33 #include "nouveau_vp3_video.h"
35 #include "nv_object.xml.h"
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
42 #define THREADS_IN_WARP 32
44 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
47 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
48 enum pipe_format format
,
49 enum pipe_texture_target target
,
50 unsigned sample_count
,
55 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
57 if (sample_count
== 8 && util_format_get_blocksizebits(format
) >= 128)
60 if (!util_format_is_supported(format
, bindings
))
64 case PIPE_FORMAT_Z16_UNORM
:
65 if (nv50_screen(pscreen
)->tesla
->oclass
< NVA0_3D_CLASS
)
72 /* transfers & shared are always supported */
73 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
74 PIPE_BIND_TRANSFER_WRITE
|
77 return (nv50_format_table
[format
].usage
& bindings
) == bindings
;
81 nv50_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
83 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
84 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
87 /* non-boolean caps */
88 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
90 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
92 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
94 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
96 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
97 case PIPE_CAP_MIN_TEXEL_OFFSET
:
99 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
100 case PIPE_CAP_MAX_TEXEL_OFFSET
:
102 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
104 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
106 case PIPE_CAP_MAX_RENDER_TARGETS
:
108 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
110 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
112 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
113 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
115 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
116 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
118 case PIPE_CAP_MAX_VERTEX_STREAMS
:
120 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
122 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
124 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
125 return 1; /* 256 for binding as RT, but that's not possible in GL */
126 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
127 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
128 case PIPE_CAP_MAX_VIEWPORTS
:
129 return NV50_MAX_VIEWPORTS
;
130 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
131 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50
;
132 case PIPE_CAP_ENDIANNESS
:
133 return PIPE_ENDIAN_LITTLE
;
134 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
135 return (class_3d
>= NVA3_3D_CLASS
) ? 4 : 0;
138 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
139 case PIPE_CAP_TEXTURE_SWIZZLE
:
140 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
141 case PIPE_CAP_NPOT_TEXTURES
:
142 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
143 case PIPE_CAP_ANISOTROPIC_FILTER
:
144 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
145 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
146 case PIPE_CAP_TWO_SIDED_STENCIL
:
147 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
148 case PIPE_CAP_POINT_SPRITE
:
150 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
151 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
152 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
153 case PIPE_CAP_QUERY_TIMESTAMP
:
154 case PIPE_CAP_QUERY_TIME_ELAPSED
:
155 case PIPE_CAP_OCCLUSION_QUERY
:
156 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
157 case PIPE_CAP_INDEP_BLEND_ENABLE
:
158 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
159 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
160 case PIPE_CAP_PRIMITIVE_RESTART
:
161 case PIPE_CAP_TGSI_INSTANCEID
:
162 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
163 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
164 case PIPE_CAP_CONDITIONAL_RENDER
:
165 case PIPE_CAP_TEXTURE_BARRIER
:
166 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
167 case PIPE_CAP_START_INSTANCE
:
168 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
169 case PIPE_CAP_USER_INDEX_BUFFERS
:
170 case PIPE_CAP_USER_VERTEX_BUFFERS
:
171 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
172 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
173 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
175 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
176 return 1; /* class_3d >= NVA0_3D_CLASS; */
177 /* supported on nva0+ */
178 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
179 return class_3d
>= NVA0_3D_CLASS
;
180 /* supported on nva3+ */
181 case PIPE_CAP_CUBE_MAP_ARRAY
:
182 case PIPE_CAP_INDEP_BLEND_FUNC
:
183 case PIPE_CAP_TEXTURE_QUERY_LOD
:
184 case PIPE_CAP_SAMPLE_SHADING
:
185 return class_3d
>= NVA3_3D_CLASS
;
187 /* unsupported caps */
188 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
189 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
190 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
191 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
192 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
193 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
194 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
195 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
196 case PIPE_CAP_TGSI_TEXCOORD
:
197 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
198 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
199 case PIPE_CAP_TEXTURE_GATHER_SM5
:
200 case PIPE_CAP_FAKE_SW_MSAA
:
201 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
202 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
203 case PIPE_CAP_COMPUTE
:
204 case PIPE_CAP_DRAW_INDIRECT
:
205 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
208 case PIPE_CAP_VENDOR_ID
:
210 case PIPE_CAP_DEVICE_ID
: {
212 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
213 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
218 case PIPE_CAP_ACCELERATED
:
220 case PIPE_CAP_VIDEO_MEMORY
:
221 return dev
->vram_size
>> 20;
226 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
231 nv50_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
232 enum pipe_shader_cap param
)
235 case PIPE_SHADER_VERTEX
:
236 case PIPE_SHADER_GEOMETRY
:
237 case PIPE_SHADER_FRAGMENT
:
244 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
245 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
246 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
247 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
249 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
251 case PIPE_SHADER_CAP_MAX_INPUTS
:
252 if (shader
== PIPE_SHADER_VERTEX
)
255 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
257 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
258 return NV50_MAX_PIPE_CONSTBUFS
;
259 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
260 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
261 return shader
!= PIPE_SHADER_FRAGMENT
;
262 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
263 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
265 case PIPE_SHADER_CAP_MAX_PREDS
:
267 case PIPE_SHADER_CAP_MAX_TEMPS
:
268 return nv50_screen(pscreen
)->max_tls_space
/ ONE_TEMP_SIZE
;
269 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
271 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
273 case PIPE_SHADER_CAP_SUBROUTINES
:
274 return 0; /* please inline, or provide function declarations */
275 case PIPE_SHADER_CAP_INTEGERS
:
277 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
278 /* The chip could handle more sampler views than samplers */
279 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
280 return MIN2(32, PIPE_MAX_SAMPLERS
);
282 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
288 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
291 case PIPE_CAPF_MAX_LINE_WIDTH
:
292 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
294 case PIPE_CAPF_MAX_POINT_WIDTH
:
295 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
297 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
299 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
301 case PIPE_CAPF_GUARD_BAND_LEFT
:
302 case PIPE_CAPF_GUARD_BAND_TOP
:
304 case PIPE_CAPF_GUARD_BAND_RIGHT
:
305 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
306 return 0.0f
; /* that or infinity */
309 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param
);
314 nv50_screen_destroy(struct pipe_screen
*pscreen
)
316 struct nv50_screen
*screen
= nv50_screen(pscreen
);
318 if (!nouveau_drm_screen_unref(&screen
->base
))
321 if (screen
->base
.fence
.current
) {
322 struct nouveau_fence
*current
= NULL
;
324 /* nouveau_fence_wait will create a new current fence, so wait on the
325 * _current_ one, and remove both.
327 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
328 nouveau_fence_wait(current
);
329 nouveau_fence_ref(NULL
, ¤t
);
330 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
332 if (screen
->base
.pushbuf
)
333 screen
->base
.pushbuf
->user_priv
= NULL
;
336 nv50_blitter_destroy(screen
);
338 nouveau_bo_ref(NULL
, &screen
->code
);
339 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
340 nouveau_bo_ref(NULL
, &screen
->stack_bo
);
341 nouveau_bo_ref(NULL
, &screen
->txc
);
342 nouveau_bo_ref(NULL
, &screen
->uniforms
);
343 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
345 nouveau_heap_destroy(&screen
->vp_code_heap
);
346 nouveau_heap_destroy(&screen
->gp_code_heap
);
347 nouveau_heap_destroy(&screen
->fp_code_heap
);
349 FREE(screen
->tic
.entries
);
351 nouveau_object_del(&screen
->tesla
);
352 nouveau_object_del(&screen
->eng2d
);
353 nouveau_object_del(&screen
->m2mf
);
354 nouveau_object_del(&screen
->sync
);
356 nouveau_screen_fini(&screen
->base
);
362 nv50_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
364 struct nv50_screen
*screen
= nv50_screen(pscreen
);
365 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
367 /* we need to do it after possible flush in MARK_RING */
368 *sequence
= ++screen
->base
.fence
.sequence
;
370 PUSH_DATA (push
, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH
), 4));
371 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
372 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
373 PUSH_DATA (push
, *sequence
);
374 PUSH_DATA (push
, NV50_3D_QUERY_GET_MODE_WRITE_UNK0
|
375 NV50_3D_QUERY_GET_UNK4
|
376 NV50_3D_QUERY_GET_UNIT_CROP
|
377 NV50_3D_QUERY_GET_TYPE_QUERY
|
378 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO
|
379 NV50_3D_QUERY_GET_SHORT
);
383 nv50_screen_fence_update(struct pipe_screen
*pscreen
)
385 return nv50_screen(pscreen
)->fence
.map
[0];
389 nv50_screen_init_hwctx(struct nv50_screen
*screen
)
391 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
392 struct nv04_fifo
*fifo
;
395 fifo
= (struct nv04_fifo
*)screen
->base
.channel
->data
;
397 BEGIN_NV04(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
398 PUSH_DATA (push
, screen
->m2mf
->handle
);
399 BEGIN_NV04(push
, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY
), 3);
400 PUSH_DATA (push
, screen
->sync
->handle
);
401 PUSH_DATA (push
, fifo
->vram
);
402 PUSH_DATA (push
, fifo
->vram
);
404 BEGIN_NV04(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
405 PUSH_DATA (push
, screen
->eng2d
->handle
);
406 BEGIN_NV04(push
, NV50_2D(DMA_NOTIFY
), 4);
407 PUSH_DATA (push
, screen
->sync
->handle
);
408 PUSH_DATA (push
, fifo
->vram
);
409 PUSH_DATA (push
, fifo
->vram
);
410 PUSH_DATA (push
, fifo
->vram
);
411 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
412 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
413 BEGIN_NV04(push
, NV50_2D(CLIP_ENABLE
), 1);
415 BEGIN_NV04(push
, NV50_2D(COLOR_KEY_ENABLE
), 1);
417 BEGIN_NV04(push
, SUBC_2D(0x0888), 1);
419 BEGIN_NV04(push
, NV50_2D(COND_MODE
), 1);
420 PUSH_DATA (push
, NV50_2D_COND_MODE_ALWAYS
);
422 BEGIN_NV04(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
423 PUSH_DATA (push
, screen
->tesla
->handle
);
425 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
426 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
428 BEGIN_NV04(push
, NV50_3D(DMA_NOTIFY
), 1);
429 PUSH_DATA (push
, screen
->sync
->handle
);
430 BEGIN_NV04(push
, NV50_3D(DMA_ZETA
), 11);
431 for (i
= 0; i
< 11; ++i
)
432 PUSH_DATA(push
, fifo
->vram
);
433 BEGIN_NV04(push
, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN
);
434 for (i
= 0; i
< NV50_3D_DMA_COLOR__LEN
; ++i
)
435 PUSH_DATA(push
, fifo
->vram
);
437 BEGIN_NV04(push
, NV50_3D(REG_MODE
), 1);
438 PUSH_DATA (push
, NV50_3D_REG_MODE_STRIPED
);
439 BEGIN_NV04(push
, NV50_3D(UNK1400_LANES
), 1);
440 PUSH_DATA (push
, 0xf);
442 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE
)) {
443 BEGIN_NV04(push
, NV50_3D(WATCHDOG_TIMER
), 1);
444 PUSH_DATA (push
, 0x18);
447 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
450 BEGIN_NV04(push
, NV50_3D(CSAA_ENABLE
), 1);
452 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_ENABLE
), 1);
454 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
455 PUSH_DATA (push
, NV50_3D_MULTISAMPLE_MODE_MS1
);
456 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_CTRL
), 1);
458 BEGIN_NV04(push
, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS
), 1);
460 BEGIN_NV04(push
, NV50_3D(LINE_LAST_PIXEL
), 1);
462 BEGIN_NV04(push
, NV50_3D(BLEND_SEPARATE_ALPHA
), 1);
465 if (screen
->tesla
->oclass
>= NVA0_3D_CLASS
) {
466 BEGIN_NV04(push
, SUBC_3D(NVA0_3D_TEX_MISC
), 1);
467 PUSH_DATA (push
, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP
);
470 BEGIN_NV04(push
, NV50_3D(SCREEN_Y_CONTROL
), 1);
472 BEGIN_NV04(push
, NV50_3D(WINDOW_OFFSET_X
), 2);
475 BEGIN_NV04(push
, NV50_3D(ZCULL_REGION
), 1);
476 PUSH_DATA (push
, 0x3f);
478 BEGIN_NV04(push
, NV50_3D(VP_ADDRESS_HIGH
), 2);
479 PUSH_DATAh(push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
480 PUSH_DATA (push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
482 BEGIN_NV04(push
, NV50_3D(FP_ADDRESS_HIGH
), 2);
483 PUSH_DATAh(push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
484 PUSH_DATA (push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
486 BEGIN_NV04(push
, NV50_3D(GP_ADDRESS_HIGH
), 2);
487 PUSH_DATAh(push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
488 PUSH_DATA (push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
490 BEGIN_NV04(push
, NV50_3D(LOCAL_ADDRESS_HIGH
), 3);
491 PUSH_DATAh(push
, screen
->tls_bo
->offset
);
492 PUSH_DATA (push
, screen
->tls_bo
->offset
);
493 PUSH_DATA (push
, util_logbase2(screen
->cur_tls_space
/ 8));
495 BEGIN_NV04(push
, NV50_3D(STACK_ADDRESS_HIGH
), 3);
496 PUSH_DATAh(push
, screen
->stack_bo
->offset
);
497 PUSH_DATA (push
, screen
->stack_bo
->offset
);
500 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
501 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (0 << 16));
502 PUSH_DATA (push
, screen
->uniforms
->offset
+ (0 << 16));
503 PUSH_DATA (push
, (NV50_CB_PVP
<< 16) | 0x0000);
505 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
506 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (1 << 16));
507 PUSH_DATA (push
, screen
->uniforms
->offset
+ (1 << 16));
508 PUSH_DATA (push
, (NV50_CB_PGP
<< 16) | 0x0000);
510 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
511 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (2 << 16));
512 PUSH_DATA (push
, screen
->uniforms
->offset
+ (2 << 16));
513 PUSH_DATA (push
, (NV50_CB_PFP
<< 16) | 0x0000);
515 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
516 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (3 << 16));
517 PUSH_DATA (push
, screen
->uniforms
->offset
+ (3 << 16));
518 PUSH_DATA (push
, (NV50_CB_AUX
<< 16) | (NV50_CB_AUX_SIZE
& 0xffff));
520 BEGIN_NI04(push
, NV50_3D(SET_PROGRAM_CB
), 3);
521 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf01);
522 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf21);
523 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf31);
525 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
526 BEGIN_NV04(push
, NV50_3D(CB_ADDR
), 1);
527 PUSH_DATA (push
, (NV50_CB_AUX_RUNOUT_OFFSET
<< (8 - 2)) | NV50_CB_AUX
);
528 BEGIN_NI04(push
, NV50_3D(CB_DATA(0)), 4);
529 PUSH_DATAf(push
, 0.0f
);
530 PUSH_DATAf(push
, 0.0f
);
531 PUSH_DATAf(push
, 0.0f
);
532 PUSH_DATAf(push
, 0.0f
);
533 BEGIN_NV04(push
, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
534 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET
);
535 PUSH_DATA (push
, screen
->uniforms
->offset
+ (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET
);
537 nv50_upload_ms_info(push
);
539 /* max TIC (bits 4:8) & TSC bindings, per program type */
540 for (i
= 0; i
< 3; ++i
) {
541 BEGIN_NV04(push
, NV50_3D(TEX_LIMITS(i
)), 1);
542 PUSH_DATA (push
, 0x54);
545 BEGIN_NV04(push
, NV50_3D(TIC_ADDRESS_HIGH
), 3);
546 PUSH_DATAh(push
, screen
->txc
->offset
);
547 PUSH_DATA (push
, screen
->txc
->offset
);
548 PUSH_DATA (push
, NV50_TIC_MAX_ENTRIES
- 1);
550 BEGIN_NV04(push
, NV50_3D(TSC_ADDRESS_HIGH
), 3);
551 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
552 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
553 PUSH_DATA (push
, NV50_TSC_MAX_ENTRIES
- 1);
555 BEGIN_NV04(push
, NV50_3D(LINKED_TSC
), 1);
558 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_EN
), 1);
560 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_MODE
), 1);
561 PUSH_DATA (push
, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
562 BEGIN_NV04(push
, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
563 for (i
= 0; i
< 8 * 2; ++i
)
565 BEGIN_NV04(push
, NV50_3D(CLIPID_ENABLE
), 1);
568 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
570 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
571 BEGIN_NV04(push
, NV50_3D(DEPTH_RANGE_NEAR(i
)), 2);
572 PUSH_DATAf(push
, 0.0f
);
573 PUSH_DATAf(push
, 1.0f
);
574 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(i
)), 2);
575 PUSH_DATA (push
, 8192 << 16);
576 PUSH_DATA (push
, 8192 << 16);
579 BEGIN_NV04(push
, NV50_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
580 #ifdef NV50_SCISSORS_CLIPPING
581 PUSH_DATA (push
, 0x0000);
583 PUSH_DATA (push
, 0x1080);
586 BEGIN_NV04(push
, NV50_3D(CLEAR_FLAGS
), 1);
587 PUSH_DATA (push
, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT
);
589 /* We use scissors instead of exact view volume clipping,
590 * so they're always enabled.
592 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
593 BEGIN_NV04(push
, NV50_3D(SCISSOR_ENABLE(i
)), 3);
595 PUSH_DATA (push
, 8192 << 16);
596 PUSH_DATA (push
, 8192 << 16);
599 BEGIN_NV04(push
, NV50_3D(RASTERIZE_ENABLE
), 1);
601 BEGIN_NV04(push
, NV50_3D(POINT_RASTER_RULES
), 1);
602 PUSH_DATA (push
, NV50_3D_POINT_RASTER_RULES_OGL
);
603 BEGIN_NV04(push
, NV50_3D(FRAG_COLOR_CLAMP_EN
), 1);
604 PUSH_DATA (push
, 0x11111111);
605 BEGIN_NV04(push
, NV50_3D(EDGEFLAG
), 1);
611 static int nv50_tls_alloc(struct nv50_screen
*screen
, unsigned tls_space
,
614 struct nouveau_device
*dev
= screen
->base
.device
;
617 screen
->cur_tls_space
= util_next_power_of_two(tls_space
/ ONE_TEMP_SIZE
) *
619 if (nouveau_mesa_debug
)
620 debug_printf("allocating space for %u temps\n",
621 util_next_power_of_two(tls_space
/ ONE_TEMP_SIZE
));
622 *tls_size
= screen
->cur_tls_space
* util_next_power_of_two(screen
->TPs
) *
623 screen
->MPsInTP
* LOCAL_WARPS_ALLOC
* THREADS_IN_WARP
;
625 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
626 *tls_size
, NULL
, &screen
->tls_bo
);
628 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret
);
635 int nv50_tls_realloc(struct nv50_screen
*screen
, unsigned tls_space
)
637 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
641 if (tls_space
< screen
->cur_tls_space
)
643 if (tls_space
> screen
->max_tls_space
) {
644 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
645 * LOCAL_WARPS_NO_CLAMP) */
646 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
647 (unsigned)(tls_space
/ ONE_TEMP_SIZE
),
648 (unsigned)(screen
->max_tls_space
/ ONE_TEMP_SIZE
));
652 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
653 ret
= nv50_tls_alloc(screen
, tls_space
, &tls_size
);
657 BEGIN_NV04(push
, NV50_3D(LOCAL_ADDRESS_HIGH
), 3);
658 PUSH_DATAh(push
, screen
->tls_bo
->offset
);
659 PUSH_DATA (push
, screen
->tls_bo
->offset
);
660 PUSH_DATA (push
, util_logbase2(screen
->cur_tls_space
/ 8));
666 nv50_screen_create(struct nouveau_device
*dev
)
668 struct nv50_screen
*screen
;
669 struct pipe_screen
*pscreen
;
670 struct nouveau_object
*chan
;
672 uint32_t tesla_class
;
676 screen
= CALLOC_STRUCT(nv50_screen
);
679 pscreen
= &screen
->base
.base
;
681 ret
= nouveau_screen_init(&screen
->base
, dev
);
683 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret
);
687 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
688 * admit them to VRAM.
690 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
691 PIPE_BIND_VERTEX_BUFFER
;
692 screen
->base
.sysmem_bindings
|=
693 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
695 screen
->base
.pushbuf
->user_priv
= screen
;
696 screen
->base
.pushbuf
->rsvd_kick
= 5;
698 chan
= screen
->base
.channel
;
700 pscreen
->destroy
= nv50_screen_destroy
;
701 pscreen
->context_create
= nv50_create
;
702 pscreen
->is_format_supported
= nv50_screen_is_format_supported
;
703 pscreen
->get_param
= nv50_screen_get_param
;
704 pscreen
->get_shader_param
= nv50_screen_get_shader_param
;
705 pscreen
->get_paramf
= nv50_screen_get_paramf
;
707 nv50_screen_init_resource_functions(pscreen
);
709 if (screen
->base
.device
->chipset
< 0x84 ||
710 debug_get_bool_option("NOUVEAU_PMPEG", FALSE
)) {
712 nouveau_screen_init_vdec(&screen
->base
);
713 } else if (screen
->base
.device
->chipset
< 0x98 ||
714 screen
->base
.device
->chipset
== 0xa0) {
716 screen
->base
.base
.get_video_param
= nv84_screen_get_video_param
;
717 screen
->base
.base
.is_video_format_supported
= nv84_screen_video_supported
;
720 screen
->base
.base
.get_video_param
= nouveau_vp3_screen_get_video_param
;
721 screen
->base
.base
.is_video_format_supported
= nouveau_vp3_screen_video_supported
;
724 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096,
725 NULL
, &screen
->fence
.bo
);
727 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret
);
731 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
732 screen
->fence
.map
= screen
->fence
.bo
->map
;
733 screen
->base
.fence
.emit
= nv50_screen_fence_emit
;
734 screen
->base
.fence
.update
= nv50_screen_fence_update
;
736 ret
= nouveau_object_new(chan
, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS
,
737 &(struct nv04_notify
){ .length
= 32 },
738 sizeof(struct nv04_notify
), &screen
->sync
);
740 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret
);
744 ret
= nouveau_object_new(chan
, 0xbeef5039, NV50_M2MF_CLASS
,
745 NULL
, 0, &screen
->m2mf
);
747 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret
);
751 ret
= nouveau_object_new(chan
, 0xbeef502d, NV50_2D_CLASS
,
752 NULL
, 0, &screen
->eng2d
);
754 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret
);
758 switch (dev
->chipset
& 0xf0) {
760 tesla_class
= NV50_3D_CLASS
;
764 tesla_class
= NV84_3D_CLASS
;
767 switch (dev
->chipset
) {
771 tesla_class
= NVA0_3D_CLASS
;
774 tesla_class
= NVAF_3D_CLASS
;
777 tesla_class
= NVA3_3D_CLASS
;
782 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev
->chipset
);
785 screen
->base
.class_3d
= tesla_class
;
787 ret
= nouveau_object_new(chan
, 0xbeef5097, tesla_class
,
788 NULL
, 0, &screen
->tesla
);
790 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret
);
794 /* This over-allocates by a page. The GP, which would execute at the end of
795 * the last page, would trigger faults. The going theory is that it
796 * prefetches up to a certain amount.
798 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
799 (3 << NV50_CODE_BO_SIZE_LOG2
) + 0x1000,
800 NULL
, &screen
->code
);
802 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret
);
806 nouveau_heap_init(&screen
->vp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
807 nouveau_heap_init(&screen
->gp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
808 nouveau_heap_init(&screen
->fp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
810 nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
812 screen
->TPs
= util_bitcount(value
& 0xffff);
813 screen
->MPsInTP
= util_bitcount((value
>> 24) & 0xf);
815 stack_size
= util_next_power_of_two(screen
->TPs
) * screen
->MPsInTP
*
816 STACK_WARPS_ALLOC
* 64 * 8;
818 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, stack_size
, NULL
,
821 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret
);
825 uint64_t size_of_one_temp
= util_next_power_of_two(screen
->TPs
) *
826 screen
->MPsInTP
* LOCAL_WARPS_ALLOC
* THREADS_IN_WARP
*
828 screen
->max_tls_space
= dev
->vram_size
/ size_of_one_temp
* ONE_TEMP_SIZE
;
829 screen
->max_tls_space
/= 2; /* half of vram */
831 /* hw can address max 64 KiB */
832 screen
->max_tls_space
= MIN2(screen
->max_tls_space
, 64 << 10);
835 unsigned tls_space
= 4/*temps*/ * ONE_TEMP_SIZE
;
836 ret
= nv50_tls_alloc(screen
, tls_space
, &tls_size
);
840 if (nouveau_mesa_debug
)
841 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64
" MiB, tls_size = %"PRIu64
" KiB\n",
842 screen
->TPs
, screen
->MPsInTP
, dev
->vram_size
>> 20, tls_size
>> 10);
844 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 4 << 16, NULL
,
847 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret
);
851 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 3 << 16, NULL
,
854 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret
);
858 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
859 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
861 if (!nv50_blitter_create(screen
))
864 nv50_screen_init_hwctx(screen
);
866 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, FALSE
);
871 nv50_screen_destroy(pscreen
);
876 nv50_screen_tic_alloc(struct nv50_screen
*screen
, void *entry
)
878 int i
= screen
->tic
.next
;
880 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
881 i
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
883 screen
->tic
.next
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
885 if (screen
->tic
.entries
[i
])
886 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
888 screen
->tic
.entries
[i
] = entry
;
893 nv50_screen_tsc_alloc(struct nv50_screen
*screen
, void *entry
)
895 int i
= screen
->tsc
.next
;
897 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
898 i
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
900 screen
->tsc
.next
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
902 if (screen
->tsc
.entries
[i
])
903 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
905 screen
->tsc
.entries
[i
] = entry
;