src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50/nv50_context.h"
  28 #include "nv50/nv50_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nv_object.xml.h"
  33 #include <errno.h>
  34
  35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  37 #endif
  38
  39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  40 #define LOCAL_WARPS_ALLOC 32
  41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  42 #define STACK_WARPS_ALLOC 32
  43
  44 #define THREADS_IN_WARP 32
  45
  46 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  47
  48 static boolean
  49 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  50                                 enum pipe_format format,
  51                                 enum pipe_texture_target target,
  52                                 unsigned sample_count,
  53                                 unsigned bindings)
  54 {
  55    if (sample_count > 8)
  56       return FALSE;
  57    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  58       return FALSE;
  59    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  60       return FALSE;
  61
  62    if (!util_format_is_supported(format, bindings))
  63       return FALSE;
  64
  65    switch (format) {
  66    case PIPE_FORMAT_Z16_UNORM:
  67       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  68          return FALSE;
  69       break;
  70    default:
  71       break;
  72    }
  73
  74    /* transfers & shared are always supported */
  75    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  76                  PIPE_BIND_TRANSFER_WRITE |
  77                  PIPE_BIND_SHARED);
  78
  79    return (nv50_format_table[format].usage & bindings) == bindings;
  80 }
  81
  82 static int
  83 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  84 {
  85    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  86
  87    switch (param) {
  88    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  89       return 64;
  90    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  91       return 14;
  92    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  93       return 12;
  94    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  97       return 512;
  98    case PIPE_CAP_MIN_TEXEL_OFFSET:
  99       return -8;
 100    case PIPE_CAP_MAX_TEXEL_OFFSET:
 101       return 7;
 102    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 103    case PIPE_CAP_TEXTURE_SWIZZLE:
 104    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 105    case PIPE_CAP_NPOT_TEXTURES:
 106    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 107    case PIPE_CAP_ANISOTROPIC_FILTER:
 108    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 109       return 1;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 65536;
 112    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 113       return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS;
 114    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 115       return 0;
 116    case PIPE_CAP_CUBE_MAP_ARRAY:
 117       return 0;
 118       /*
 119       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 120       */
 121    case PIPE_CAP_TWO_SIDED_STENCIL:
 122    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 123    case PIPE_CAP_POINT_SPRITE:
 124       return 1;
 125    case PIPE_CAP_SM3:
 126       return 1;
 127    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 128       return 140;
 129    case PIPE_CAP_MAX_RENDER_TARGETS:
 130       return 8;
 131    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 132       return 1;
 133    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 134    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 135    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 136       return 1;
 137    case PIPE_CAP_QUERY_TIMESTAMP:
 138    case PIPE_CAP_QUERY_TIME_ELAPSED:
 139    case PIPE_CAP_OCCLUSION_QUERY:
 140       return 1;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 142       return 4;
 143    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 145       return 64;
 146    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 147       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 148    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 149    case PIPE_CAP_INDEP_BLEND_ENABLE:
 150       return 1;
 151    case PIPE_CAP_INDEP_BLEND_FUNC:
 152       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 153    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 154    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 155       return 1;
 156    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 157    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 158       return 0;
 159    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 160       return 0;
 161    case PIPE_CAP_PRIMITIVE_RESTART:
 162    case PIPE_CAP_TGSI_INSTANCEID:
 163    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 164    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 165    case PIPE_CAP_CONDITIONAL_RENDER:
 166    case PIPE_CAP_TEXTURE_BARRIER:
 167    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 168    case PIPE_CAP_START_INSTANCE:
 169       return 1;
 170    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 171       return 0; /* state trackers will know better */
 172    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 173    case PIPE_CAP_USER_INDEX_BUFFERS:
 174    case PIPE_CAP_USER_VERTEX_BUFFERS:
 175       return 1;
 176    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 177       return 256;
 178    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 179       return 1; /* 256 for binding as RT, but that's not possible in GL */
 180    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 181       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 182    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 183    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 184    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 185    case PIPE_CAP_TGSI_TEXCOORD:
 186    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 187       return 0;
 188    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 189       return 1;
 190    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 191       return 0;
 192    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 193       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 194    case PIPE_CAP_ENDIANNESS:
 195       return PIPE_ENDIAN_LITTLE;
 196    case PIPE_CAP_TGSI_VS_LAYER:
 197       return 0;
 198    default:
 199       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 200       return 0;
 201    }
 202 }
 203
 204 static int
 205 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 206                              enum pipe_shader_cap param)
 207 {
 208    switch (shader) {
 209    case PIPE_SHADER_VERTEX:
 210    case PIPE_SHADER_GEOMETRY:
 211    case PIPE_SHADER_FRAGMENT:
 212       break;
 213    default:
 214       return 0;
 215    }
 216
 217    switch (param) {
 218    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 219    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 220    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 221    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 222       return 16384;
 223    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 224       return 4;
 225    case PIPE_SHADER_CAP_MAX_INPUTS:
 226       if (shader == PIPE_SHADER_VERTEX)
 227          return 32;
 228       return 15;
 229    case PIPE_SHADER_CAP_MAX_CONSTS:
 230       return 65536 / 16;
 231    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 232       return NV50_MAX_PIPE_CONSTBUFS;
 233    case PIPE_SHADER_CAP_MAX_ADDRS:
 234       return 1;
 235    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 236    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 237       return shader != PIPE_SHADER_FRAGMENT;
 238    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 239    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 240       return 1;
 241    case PIPE_SHADER_CAP_MAX_PREDS:
 242       return 0;
 243    case PIPE_SHADER_CAP_MAX_TEMPS:
 244       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 245    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 246       return 1;
 247    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 248       return 0;
 249    case PIPE_SHADER_CAP_SUBROUTINES:
 250       return 0; /* please inline, or provide function declarations */
 251    case PIPE_SHADER_CAP_INTEGERS:
 252       return 1;
 253    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 254       /* The chip could handle more sampler views than samplers */
 255    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 256       return MIN2(32, PIPE_MAX_SAMPLERS);
 257    default:
 258       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 259       return 0;
 260    }
 261 }
 262
 263 static float
 264 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 265 {
 266    switch (param) {
 267    case PIPE_CAPF_MAX_LINE_WIDTH:
 268    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 269       return 10.0f;
 270    case PIPE_CAPF_MAX_POINT_WIDTH:
 271    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 272       return 64.0f;
 273    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 274       return 16.0f;
 275    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 276       return 4.0f;
 277    default:
 278       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 279       return 0.0f;
 280    }
 281 }
 282
 283 static void
 284 nv50_screen_destroy(struct pipe_screen *pscreen)
 285 {
 286    struct nv50_screen *screen = nv50_screen(pscreen);
 287
 288    if (screen->base.fence.current) {
 289       nouveau_fence_wait(screen->base.fence.current);
 290       nouveau_fence_ref (NULL, &screen->base.fence.current);
 291    }
 292    if (screen->base.pushbuf)
 293       screen->base.pushbuf->user_priv = NULL;
 294
 295    if (screen->blitter)
 296       nv50_blitter_destroy(screen);
 297
 298    nouveau_bo_ref(NULL, &screen->code);
 299    nouveau_bo_ref(NULL, &screen->tls_bo);
 300    nouveau_bo_ref(NULL, &screen->stack_bo);
 301    nouveau_bo_ref(NULL, &screen->txc);
 302    nouveau_bo_ref(NULL, &screen->uniforms);
 303    nouveau_bo_ref(NULL, &screen->fence.bo);
 304
 305    nouveau_heap_destroy(&screen->vp_code_heap);
 306    nouveau_heap_destroy(&screen->gp_code_heap);
 307    nouveau_heap_destroy(&screen->fp_code_heap);
 308
 309    FREE(screen->tic.entries);
 310
 311    nouveau_object_del(&screen->tesla);
 312    nouveau_object_del(&screen->eng2d);
 313    nouveau_object_del(&screen->m2mf);
 314    nouveau_object_del(&screen->sync);
 315
 316    nouveau_screen_fini(&screen->base);
 317
 318    FREE(screen);
 319 }
 320
 321 static void
 322 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 323 {
 324    struct nv50_screen *screen = nv50_screen(pscreen);
 325    struct nouveau_pushbuf *push = screen->base.pushbuf;
 326
 327    /* we need to do it after possible flush in MARK_RING */
 328    *sequence = ++screen->base.fence.sequence;
 329
 330    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 331    PUSH_DATAh(push, screen->fence.bo->offset);
 332    PUSH_DATA (push, screen->fence.bo->offset);
 333    PUSH_DATA (push, *sequence);
 334    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 335                     NV50_3D_QUERY_GET_UNK4 |
 336                     NV50_3D_QUERY_GET_UNIT_CROP |
 337                     NV50_3D_QUERY_GET_TYPE_QUERY |
 338                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 339                     NV50_3D_QUERY_GET_SHORT);
 340 }
 341
 342 static u32
 343 nv50_screen_fence_update(struct pipe_screen *pscreen)
 344 {
 345    return nv50_screen(pscreen)->fence.map[0];
 346 }
 347
 348 static void
 349 nv50_screen_init_hwctx(struct nv50_screen *screen)
 350 {
 351    struct nouveau_pushbuf *push = screen->base.pushbuf;
 352    struct nv04_fifo *fifo;
 353    unsigned i;
 354
 355    fifo = (struct nv04_fifo *)screen->base.channel->data;
 356
 357    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 358    PUSH_DATA (push, screen->m2mf->handle);
 359    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 360    PUSH_DATA (push, screen->sync->handle);
 361    PUSH_DATA (push, fifo->vram);
 362    PUSH_DATA (push, fifo->vram);
 363
 364    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 365    PUSH_DATA (push, screen->eng2d->handle);
 366    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 367    PUSH_DATA (push, screen->sync->handle);
 368    PUSH_DATA (push, fifo->vram);
 369    PUSH_DATA (push, fifo->vram);
 370    PUSH_DATA (push, fifo->vram);
 371    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 372    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 373    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 374    PUSH_DATA (push, 0);
 375    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 376    PUSH_DATA (push, 0);
 377    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 378    PUSH_DATA (push, 1);
 379
 380    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 381    PUSH_DATA (push, screen->tesla->handle);
 382
 383    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 384    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 385
 386    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 387    PUSH_DATA (push, screen->sync->handle);
 388    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 389    for (i = 0; i < 11; ++i)
 390       PUSH_DATA(push, fifo->vram);
 391    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 392    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 393       PUSH_DATA(push, fifo->vram);
 394
 395    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 396    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 397    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 398    PUSH_DATA (push, 0xf);
 399
 400    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 401       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 402       PUSH_DATA (push, 0x18);
 403    }
 404
 405    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 406    PUSH_DATA (push, 1);
 407
 408    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 409    PUSH_DATA (push, 0);
 410    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 411    PUSH_DATA (push, 0);
 412    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 413    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 414    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 415    PUSH_DATA (push, 0);
 416    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 417    PUSH_DATA (push, 0);
 418    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 419    PUSH_DATA (push, 1);
 420
 421    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 422       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 423       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 424    }
 425
 426    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 427    PUSH_DATA (push, 0);
 428    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 429    PUSH_DATA (push, 0);
 430    PUSH_DATA (push, 0);
 431    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 432    PUSH_DATA (push, 0x3f);
 433
 434    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 435    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 436    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 437
 438    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 439    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 440    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 441
 442    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 443    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 444    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 445
 446    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 447    PUSH_DATAh(push, screen->tls_bo->offset);
 448    PUSH_DATA (push, screen->tls_bo->offset);
 449    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 450
 451    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 452    PUSH_DATAh(push, screen->stack_bo->offset);
 453    PUSH_DATA (push, screen->stack_bo->offset);
 454    PUSH_DATA (push, 4);
 455
 456    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 457    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 458    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 459    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 460
 461    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 462    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 463    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 464    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 465
 466    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 467    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 468    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 469    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 470
 471    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 472    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 473    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 474    PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200);
 475
 476    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 477    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 478    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 479    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 480
 481    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 482    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 483    PUSH_DATA (push, ((1 << 9) << 6) | NV50_CB_AUX);
 484    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 485    PUSH_DATAf(push, 0.0f);
 486    PUSH_DATAf(push, 0.0f);
 487    PUSH_DATAf(push, 0.0f);
 488    PUSH_DATAf(push, 0.0f);
 489    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 490    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + (1 << 9));
 491    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + (1 << 9));
 492
 493    /* max TIC (bits 4:8) & TSC bindings, per program type */
 494    for (i = 0; i < 3; ++i) {
 495       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 496       PUSH_DATA (push, 0x54);
 497    }
 498
 499    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 500    PUSH_DATAh(push, screen->txc->offset);
 501    PUSH_DATA (push, screen->txc->offset);
 502    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 503
 504    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 505    PUSH_DATAh(push, screen->txc->offset + 65536);
 506    PUSH_DATA (push, screen->txc->offset + 65536);
 507    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 508
 509    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 510    PUSH_DATA (push, 0);
 511
 512    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 513    PUSH_DATA (push, 0);
 514    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 515    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 516    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 517    for (i = 0; i < 8 * 2; ++i)
 518       PUSH_DATA(push, 0);
 519    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 520    PUSH_DATA (push, 0);
 521
 522    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 523    PUSH_DATA (push, 1);
 524    BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
 525    PUSH_DATAf(push, 0.0f);
 526    PUSH_DATAf(push, 1.0f);
 527
 528    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 529 #ifdef NV50_SCISSORS_CLIPPING
 530    PUSH_DATA (push, 0x0000);
 531 #else
 532    PUSH_DATA (push, 0x1080);
 533 #endif
 534
 535    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 536    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 537
 538    /* We use scissors instead of exact view volume clipping,
 539     * so they're always enabled.
 540     */
 541    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
 542    PUSH_DATA (push, 1);
 543    PUSH_DATA (push, 8192 << 16);
 544    PUSH_DATA (push, 8192 << 16);
 545
 546    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 547    PUSH_DATA (push, 1);
 548    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 549    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 550    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 551    PUSH_DATA (push, 0x11111111);
 552    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 553    PUSH_DATA (push, 1);
 554
 555    PUSH_KICK (push);
 556 }
 557
 558 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 559       uint64_t *tls_size)
 560 {
 561    struct nouveau_device *dev = screen->base.device;
 562    int ret;
 563
 564    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 565          ONE_TEMP_SIZE;
 566    if (nouveau_mesa_debug)
 567       debug_printf("allocating space for %u temps\n",
 568             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 569    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 570          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 571
 572    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 573                         *tls_size, NULL, &screen->tls_bo);
 574    if (ret) {
 575       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 576       return ret;
 577    }
 578
 579    return 0;
 580 }
 581
 582 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 583 {
 584    struct nouveau_pushbuf *push = screen->base.pushbuf;
 585    int ret;
 586    uint64_t tls_size;
 587
 588    if (tls_space < screen->cur_tls_space)
 589       return 0;
 590    if (tls_space > screen->max_tls_space) {
 591       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 592        * LOCAL_WARPS_NO_CLAMP) */
 593       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 594             (unsigned)(tls_space / ONE_TEMP_SIZE),
 595             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 596       return -ENOMEM;
 597    }
 598
 599    nouveau_bo_ref(NULL, &screen->tls_bo);
 600    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 601    if (ret)
 602       return ret;
 603
 604    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 605    PUSH_DATAh(push, screen->tls_bo->offset);
 606    PUSH_DATA (push, screen->tls_bo->offset);
 607    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 608
 609    return 1;
 610 }
 611
 612 struct pipe_screen *
 613 nv50_screen_create(struct nouveau_device *dev)
 614 {
 615    struct nv50_screen *screen;
 616    struct pipe_screen *pscreen;
 617    struct nouveau_object *chan;
 618    uint64_t value;
 619    uint32_t tesla_class;
 620    unsigned stack_size;
 621    int ret;
 622
 623    screen = CALLOC_STRUCT(nv50_screen);
 624    if (!screen)
 625       return NULL;
 626    pscreen = &screen->base.base;
 627
 628    ret = nouveau_screen_init(&screen->base, dev);
 629    if (ret) {
 630       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 631       goto fail;
 632    }
 633
 634    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 635     *  admit them to VRAM.
 636     */
 637    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 638       PIPE_BIND_VERTEX_BUFFER;
 639    screen->base.sysmem_bindings |=
 640       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 641
 642    screen->base.pushbuf->user_priv = screen;
 643    screen->base.pushbuf->rsvd_kick = 5;
 644
 645    chan = screen->base.channel;
 646
 647    pscreen->destroy = nv50_screen_destroy;
 648    pscreen->context_create = nv50_create;
 649    pscreen->is_format_supported = nv50_screen_is_format_supported;
 650    pscreen->get_param = nv50_screen_get_param;
 651    pscreen->get_shader_param = nv50_screen_get_shader_param;
 652    pscreen->get_paramf = nv50_screen_get_paramf;
 653
 654    nv50_screen_init_resource_functions(pscreen);
 655
 656    if (screen->base.device->chipset < 0x84 ||
 657        debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
 658       /* PMPEG */
 659       nouveau_screen_init_vdec(&screen->base);
 660    } else if (screen->base.device->chipset < 0x98 ||
 661               screen->base.device->chipset == 0xa0) {
 662       /* VP2 */
 663       screen->base.base.get_video_param = nv84_screen_get_video_param;
 664       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 665    } else {
 666       /* VP3/4 */
 667       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 668       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 669    }
 670
 671    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 672                         NULL, &screen->fence.bo);
 673    if (ret) {
 674       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 675       goto fail;
 676    }
 677
 678    nouveau_bo_map(screen->fence.bo, 0, NULL);
 679    screen->fence.map = screen->fence.bo->map;
 680    screen->base.fence.emit = nv50_screen_fence_emit;
 681    screen->base.fence.update = nv50_screen_fence_update;
 682
 683    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 684                             &(struct nv04_notify){ .length = 32 },
 685                             sizeof(struct nv04_notify), &screen->sync);
 686    if (ret) {
 687       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 688       goto fail;
 689    }
 690
 691    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 692                             NULL, 0, &screen->m2mf);
 693    if (ret) {
 694       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 695       goto fail;
 696    }
 697
 698    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 699                             NULL, 0, &screen->eng2d);
 700    if (ret) {
 701       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 702       goto fail;
 703    }
 704
 705    switch (dev->chipset & 0xf0) {
 706    case 0x50:
 707       tesla_class = NV50_3D_CLASS;
 708       break;
 709    case 0x80:
 710    case 0x90:
 711       tesla_class = NV84_3D_CLASS;
 712       break;
 713    case 0xa0:
 714       switch (dev->chipset) {
 715       case 0xa0:
 716       case 0xaa:
 717       case 0xac:
 718          tesla_class = NVA0_3D_CLASS;
 719          break;
 720       case 0xaf:
 721          tesla_class = NVAF_3D_CLASS;
 722          break;
 723       default:
 724          tesla_class = NVA3_3D_CLASS;
 725          break;
 726       }
 727       break;
 728    default:
 729       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 730       goto fail;
 731    }
 732    screen->base.class_3d = tesla_class;
 733
 734    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 735                             NULL, 0, &screen->tesla);
 736    if (ret) {
 737       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 738       goto fail;
 739    }
 740
 741    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 742                         3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code);
 743    if (ret) {
 744       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 745       goto fail;
 746    }
 747
 748    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 749    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 750    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 751
 752    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 753
 754    screen->TPs = util_bitcount(value & 0xffff);
 755    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 756
 757    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 758          STACK_WARPS_ALLOC * 64 * 8;
 759
 760    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 761                         &screen->stack_bo);
 762    if (ret) {
 763       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 764       goto fail;
 765    }
 766
 767    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 768          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 769          ONE_TEMP_SIZE;
 770    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 771    screen->max_tls_space /= 2; /* half of vram */
 772
 773    /* hw can address max 64 KiB */
 774    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 775
 776    uint64_t tls_size;
 777    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 778    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 779    if (ret)
 780       goto fail;
 781
 782    if (nouveau_mesa_debug)
 783       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 784             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 785
 786    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 787                         &screen->uniforms);
 788    if (ret) {
 789       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 790       goto fail;
 791    }
 792
 793    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 794                         &screen->txc);
 795    if (ret) {
 796       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 797       goto fail;
 798    }
 799
 800    screen->tic.entries = CALLOC(4096, sizeof(void *));
 801    screen->tsc.entries = screen->tic.entries + 2048;
 802
 803    if (!nv50_blitter_create(screen))
 804       goto fail;
 805
 806    nv50_screen_init_hwctx(screen);
 807
 808    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 809
 810    return pscreen;
 811
 812 fail:
 813    nv50_screen_destroy(pscreen);
 814    return NULL;
 815 }
 816
 817 int
 818 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 819 {
 820    int i = screen->tic.next;
 821
 822    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 823       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 824
 825    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 826
 827    if (screen->tic.entries[i])
 828       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 829
 830    screen->tic.entries[i] = entry;
 831    return i;
 832 }
 833
 834 int
 835 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 836 {
 837    int i = screen->tsc.next;
 838
 839    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 840       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 841
 842    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 843
 844    if (screen->tsc.entries[i])
 845       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 846
 847    screen->tsc.entries[i] = entry;
 848    return i;
 849 }