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[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <errno.h>
24 #include <xf86drm.h>
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nv_object.xml.h"
36
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
41
42 #define THREADS_IN_WARP 32
43
44 static boolean
45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
46 enum pipe_format format,
47 enum pipe_texture_target target,
48 unsigned sample_count,
49 unsigned bindings)
50 {
51 if (sample_count > 8)
52 return false;
53 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
54 return false;
55 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
56 return false;
57
58 if (!util_format_is_supported(format, bindings))
59 return false;
60
61 switch (format) {
62 case PIPE_FORMAT_Z16_UNORM:
63 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
64 return false;
65 break;
66 default:
67 break;
68 }
69
70 if (bindings & PIPE_BIND_LINEAR)
71 if (util_format_is_depth_or_stencil(format) ||
72 (target != PIPE_TEXTURE_1D &&
73 target != PIPE_TEXTURE_2D &&
74 target != PIPE_TEXTURE_RECT) ||
75 sample_count > 1)
76 return false;
77
78 /* transfers & shared are always supported */
79 bindings &= ~(PIPE_BIND_TRANSFER_READ |
80 PIPE_BIND_TRANSFER_WRITE |
81 PIPE_BIND_LINEAR |
82 PIPE_BIND_SHARED);
83
84 return (( nv50_format_table[format].usage |
85 nv50_vertex_format[format].usage) & bindings) == bindings;
86 }
87
88 static int
89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
90 {
91 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
92 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
93
94 switch (param) {
95 /* non-boolean caps */
96 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
97 return 14;
98 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
99 return 12;
100 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
101 return 14;
102 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
103 return 512;
104 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
105 case PIPE_CAP_MIN_TEXEL_OFFSET:
106 return -8;
107 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
108 case PIPE_CAP_MAX_TEXEL_OFFSET:
109 return 7;
110 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
111 return 128 * 1024 * 1024;
112 case PIPE_CAP_GLSL_FEATURE_LEVEL:
113 return 330;
114 case PIPE_CAP_MAX_RENDER_TARGETS:
115 return 8;
116 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
117 return 1;
118 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
119 return 4;
120 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
121 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
122 return 64;
123 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
124 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
125 return 1024;
126 case PIPE_CAP_MAX_VERTEX_STREAMS:
127 return 1;
128 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
129 return 2048;
130 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
131 return 256;
132 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
133 return 16; /* 256 for binding as RT, but that's not possible in GL */
134 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
135 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
136 case PIPE_CAP_MAX_VIEWPORTS:
137 return NV50_MAX_VIEWPORTS;
138 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
139 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
140 case PIPE_CAP_ENDIANNESS:
141 return PIPE_ENDIAN_LITTLE;
142 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
143 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
144
145 /* supported caps */
146 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
147 case PIPE_CAP_TEXTURE_SWIZZLE:
148 case PIPE_CAP_TEXTURE_SHADOW_MAP:
149 case PIPE_CAP_NPOT_TEXTURES:
150 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
151 case PIPE_CAP_ANISOTROPIC_FILTER:
152 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
153 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
154 case PIPE_CAP_TWO_SIDED_STENCIL:
155 case PIPE_CAP_DEPTH_CLIP_DISABLE:
156 case PIPE_CAP_POINT_SPRITE:
157 case PIPE_CAP_SM3:
158 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
159 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
160 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
161 case PIPE_CAP_QUERY_TIMESTAMP:
162 case PIPE_CAP_QUERY_TIME_ELAPSED:
163 case PIPE_CAP_OCCLUSION_QUERY:
164 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
165 case PIPE_CAP_INDEP_BLEND_ENABLE:
166 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
167 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
168 case PIPE_CAP_PRIMITIVE_RESTART:
169 case PIPE_CAP_TGSI_INSTANCEID:
170 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
171 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
172 case PIPE_CAP_CONDITIONAL_RENDER:
173 case PIPE_CAP_TEXTURE_BARRIER:
174 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
175 case PIPE_CAP_START_INSTANCE:
176 case PIPE_CAP_USER_CONSTANT_BUFFERS:
177 case PIPE_CAP_USER_INDEX_BUFFERS:
178 case PIPE_CAP_USER_VERTEX_BUFFERS:
179 case PIPE_CAP_TEXTURE_MULTISAMPLE:
180 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
181 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
182 case PIPE_CAP_SAMPLER_VIEW_TARGET:
183 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
184 case PIPE_CAP_CLIP_HALFZ:
185 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
186 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
187 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
188 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
189 case PIPE_CAP_DEPTH_BOUNDS_TEST:
190 case PIPE_CAP_TGSI_TXQS:
191 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
192 case PIPE_CAP_SHAREABLE_SHADERS:
193 case PIPE_CAP_CLEAR_TEXTURE:
194 case PIPE_CAP_COMPUTE:
195 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
196 case PIPE_CAP_INVALIDATE_BUFFER:
197 case PIPE_CAP_STRING_MARKER:
198 case PIPE_CAP_CULL_DISTANCE:
199 return 1;
200 case PIPE_CAP_SEAMLESS_CUBE_MAP:
201 return 1; /* class_3d >= NVA0_3D_CLASS; */
202 /* supported on nva0+ */
203 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
204 return class_3d >= NVA0_3D_CLASS;
205 /* supported on nva3+ */
206 case PIPE_CAP_CUBE_MAP_ARRAY:
207 case PIPE_CAP_INDEP_BLEND_FUNC:
208 case PIPE_CAP_TEXTURE_QUERY_LOD:
209 case PIPE_CAP_SAMPLE_SHADING:
210 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
211 return class_3d >= NVA3_3D_CLASS;
212
213 /* unsupported caps */
214 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
215 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
216 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
217 case PIPE_CAP_SHADER_STENCIL_EXPORT:
218 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
219 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
220 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
221 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
222 case PIPE_CAP_TGSI_TEXCOORD:
223 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
224 case PIPE_CAP_TEXTURE_GATHER_SM5:
225 case PIPE_CAP_FAKE_SW_MSAA:
226 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
227 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
228 case PIPE_CAP_DRAW_INDIRECT:
229 case PIPE_CAP_MULTI_DRAW_INDIRECT:
230 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
231 case PIPE_CAP_VERTEXID_NOBASE:
232 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
233 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
234 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
235 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
236 case PIPE_CAP_DRAW_PARAMETERS:
237 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
238 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
239 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
240 case PIPE_CAP_GENERATE_MIPMAP:
241 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
242 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
243 case PIPE_CAP_QUERY_BUFFER_OBJECT:
244 case PIPE_CAP_QUERY_MEMORY_INFO:
245 case PIPE_CAP_PCI_GROUP:
246 case PIPE_CAP_PCI_BUS:
247 case PIPE_CAP_PCI_DEVICE:
248 case PIPE_CAP_PCI_FUNCTION:
249 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
250 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
251 return 0;
252
253 case PIPE_CAP_VENDOR_ID:
254 return 0x10de;
255 case PIPE_CAP_DEVICE_ID: {
256 uint64_t device_id;
257 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
258 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
259 return -1;
260 }
261 return device_id;
262 }
263 case PIPE_CAP_ACCELERATED:
264 return 1;
265 case PIPE_CAP_VIDEO_MEMORY:
266 return dev->vram_size >> 20;
267 case PIPE_CAP_UMA:
268 return 0;
269 }
270
271 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
272 return 0;
273 }
274
275 static int
276 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
277 enum pipe_shader_cap param)
278 {
279 switch (shader) {
280 case PIPE_SHADER_VERTEX:
281 case PIPE_SHADER_GEOMETRY:
282 case PIPE_SHADER_FRAGMENT:
283 break;
284 case PIPE_SHADER_COMPUTE:
285 default:
286 return 0;
287 }
288
289 switch (param) {
290 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
291 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
292 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
293 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
294 return 16384;
295 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
296 return 4;
297 case PIPE_SHADER_CAP_MAX_INPUTS:
298 if (shader == PIPE_SHADER_VERTEX)
299 return 32;
300 return 15;
301 case PIPE_SHADER_CAP_MAX_OUTPUTS:
302 return 16;
303 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
304 return 65536;
305 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
306 return NV50_MAX_PIPE_CONSTBUFS;
307 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
308 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
309 return shader != PIPE_SHADER_FRAGMENT;
310 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
311 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
312 return 1;
313 case PIPE_SHADER_CAP_MAX_PREDS:
314 return 0;
315 case PIPE_SHADER_CAP_MAX_TEMPS:
316 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
317 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
318 return 1;
319 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
320 return 1;
321 case PIPE_SHADER_CAP_SUBROUTINES:
322 return 0; /* please inline, or provide function declarations */
323 case PIPE_SHADER_CAP_INTEGERS:
324 return 1;
325 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
326 /* The chip could handle more sampler views than samplers */
327 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
328 return MIN2(16, PIPE_MAX_SAMPLERS);
329 case PIPE_SHADER_CAP_PREFERRED_IR:
330 return PIPE_SHADER_IR_TGSI;
331 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
332 return 32;
333 case PIPE_SHADER_CAP_DOUBLES:
334 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
335 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
336 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
337 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
338 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
339 case PIPE_SHADER_CAP_SUPPORTED_IRS:
340 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
341 return 0;
342 default:
343 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
344 return 0;
345 }
346 }
347
348 static float
349 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
350 {
351 switch (param) {
352 case PIPE_CAPF_MAX_LINE_WIDTH:
353 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
354 return 10.0f;
355 case PIPE_CAPF_MAX_POINT_WIDTH:
356 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
357 return 64.0f;
358 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
359 return 16.0f;
360 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
361 return 4.0f;
362 case PIPE_CAPF_GUARD_BAND_LEFT:
363 case PIPE_CAPF_GUARD_BAND_TOP:
364 return 0.0f;
365 case PIPE_CAPF_GUARD_BAND_RIGHT:
366 case PIPE_CAPF_GUARD_BAND_BOTTOM:
367 return 0.0f; /* that or infinity */
368 }
369
370 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
371 return 0.0f;
372 }
373
374 static int
375 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
376 enum pipe_shader_ir ir_type,
377 enum pipe_compute_cap param, void *data)
378 {
379 struct nv50_screen *screen = nv50_screen(pscreen);
380
381 #define RET(x) do { \
382 if (data) \
383 memcpy(data, x, sizeof(x)); \
384 return sizeof(x); \
385 } while (0)
386
387 switch (param) {
388 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
389 RET((uint64_t []) { 2 });
390 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
391 RET(((uint64_t []) { 65535, 65535 }));
392 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
393 RET(((uint64_t []) { 512, 512, 64 }));
394 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
395 RET((uint64_t []) { 512 });
396 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
397 RET((uint64_t []) { 1ULL << 32 });
398 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
399 RET((uint64_t []) { 16 << 10 });
400 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
401 RET((uint64_t []) { 16 << 10 });
402 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
403 RET((uint64_t []) { 4096 });
404 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
405 RET((uint32_t []) { 32 });
406 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
407 RET((uint64_t []) { 1ULL << 40 });
408 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
409 RET((uint32_t []) { 0 });
410 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
411 RET((uint32_t []) { screen->mp_count });
412 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
413 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
414 default:
415 return 0;
416 }
417
418 #undef RET
419 }
420
421 static void
422 nv50_screen_destroy(struct pipe_screen *pscreen)
423 {
424 struct nv50_screen *screen = nv50_screen(pscreen);
425
426 if (!nouveau_drm_screen_unref(&screen->base))
427 return;
428
429 if (screen->base.fence.current) {
430 struct nouveau_fence *current = NULL;
431
432 /* nouveau_fence_wait will create a new current fence, so wait on the
433 * _current_ one, and remove both.
434 */
435 nouveau_fence_ref(screen->base.fence.current, &current);
436 nouveau_fence_wait(current, NULL);
437 nouveau_fence_ref(NULL, &current);
438 nouveau_fence_ref(NULL, &screen->base.fence.current);
439 }
440 if (screen->base.pushbuf)
441 screen->base.pushbuf->user_priv = NULL;
442
443 if (screen->blitter)
444 nv50_blitter_destroy(screen);
445 if (screen->pm.prog) {
446 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
447 nv50_program_destroy(NULL, screen->pm.prog);
448 FREE(screen->pm.prog);
449 }
450
451 nouveau_bo_ref(NULL, &screen->code);
452 nouveau_bo_ref(NULL, &screen->tls_bo);
453 nouveau_bo_ref(NULL, &screen->stack_bo);
454 nouveau_bo_ref(NULL, &screen->txc);
455 nouveau_bo_ref(NULL, &screen->uniforms);
456 nouveau_bo_ref(NULL, &screen->fence.bo);
457
458 nouveau_heap_destroy(&screen->vp_code_heap);
459 nouveau_heap_destroy(&screen->gp_code_heap);
460 nouveau_heap_destroy(&screen->fp_code_heap);
461
462 FREE(screen->tic.entries);
463
464 nouveau_object_del(&screen->tesla);
465 nouveau_object_del(&screen->eng2d);
466 nouveau_object_del(&screen->m2mf);
467 nouveau_object_del(&screen->compute);
468 nouveau_object_del(&screen->sync);
469
470 nouveau_screen_fini(&screen->base);
471
472 FREE(screen);
473 }
474
475 static void
476 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
477 {
478 struct nv50_screen *screen = nv50_screen(pscreen);
479 struct nouveau_pushbuf *push = screen->base.pushbuf;
480
481 /* we need to do it after possible flush in MARK_RING */
482 *sequence = ++screen->base.fence.sequence;
483
484 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
485 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
486 PUSH_DATAh(push, screen->fence.bo->offset);
487 PUSH_DATA (push, screen->fence.bo->offset);
488 PUSH_DATA (push, *sequence);
489 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
490 NV50_3D_QUERY_GET_UNK4 |
491 NV50_3D_QUERY_GET_UNIT_CROP |
492 NV50_3D_QUERY_GET_TYPE_QUERY |
493 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
494 NV50_3D_QUERY_GET_SHORT);
495 }
496
497 static u32
498 nv50_screen_fence_update(struct pipe_screen *pscreen)
499 {
500 return nv50_screen(pscreen)->fence.map[0];
501 }
502
503 static void
504 nv50_screen_init_hwctx(struct nv50_screen *screen)
505 {
506 struct nouveau_pushbuf *push = screen->base.pushbuf;
507 struct nv04_fifo *fifo;
508 unsigned i;
509
510 fifo = (struct nv04_fifo *)screen->base.channel->data;
511
512 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
513 PUSH_DATA (push, screen->m2mf->handle);
514 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
515 PUSH_DATA (push, screen->sync->handle);
516 PUSH_DATA (push, fifo->vram);
517 PUSH_DATA (push, fifo->vram);
518
519 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
520 PUSH_DATA (push, screen->eng2d->handle);
521 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
522 PUSH_DATA (push, screen->sync->handle);
523 PUSH_DATA (push, fifo->vram);
524 PUSH_DATA (push, fifo->vram);
525 PUSH_DATA (push, fifo->vram);
526 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
527 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
528 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
529 PUSH_DATA (push, 0);
530 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
531 PUSH_DATA (push, 0);
532 BEGIN_NV04(push, SUBC_2D(0x0888), 1);
533 PUSH_DATA (push, 1);
534 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
535 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
536
537 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
538 PUSH_DATA (push, screen->tesla->handle);
539
540 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
541 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
542
543 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
544 PUSH_DATA (push, screen->sync->handle);
545 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
546 for (i = 0; i < 11; ++i)
547 PUSH_DATA(push, fifo->vram);
548 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
549 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
550 PUSH_DATA(push, fifo->vram);
551
552 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
553 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
554 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
555 PUSH_DATA (push, 0xf);
556
557 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
558 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
559 PUSH_DATA (push, 0x18);
560 }
561
562 BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
563 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
564
565 BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
566 for (i = 0; i < 8; ++i)
567 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
568
569 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
570 PUSH_DATA (push, 1);
571
572 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
573 PUSH_DATA (push, 0);
574 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
575 PUSH_DATA (push, 0);
576 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
577 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
578 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
579 PUSH_DATA (push, 0);
580 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
581 PUSH_DATA (push, 1);
582 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
583 PUSH_DATA (push, 1);
584
585 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
586 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
587 PUSH_DATA (push, 0);
588 }
589
590 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
591 PUSH_DATA (push, 0);
592 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
593 PUSH_DATA (push, 0);
594 PUSH_DATA (push, 0);
595 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
596 PUSH_DATA (push, 0x3f);
597
598 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
599 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
600 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
601
602 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
603 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
604 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
605
606 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
607 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
608 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
609
610 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
611 PUSH_DATAh(push, screen->tls_bo->offset);
612 PUSH_DATA (push, screen->tls_bo->offset);
613 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
614
615 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
616 PUSH_DATAh(push, screen->stack_bo->offset);
617 PUSH_DATA (push, screen->stack_bo->offset);
618 PUSH_DATA (push, 4);
619
620 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
621 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
622 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
623 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
624
625 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
626 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
627 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
628 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
629
630 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
631 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
632 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
633 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
634
635 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
636 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
637 PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
638 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
639
640 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
641 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
642 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
643 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
644
645 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
646 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
647 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
648 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
649 PUSH_DATAf(push, 0.0f);
650 PUSH_DATAf(push, 0.0f);
651 PUSH_DATAf(push, 0.0f);
652 PUSH_DATAf(push, 0.0f);
653 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
654 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
655 PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
656
657 nv50_upload_ms_info(push);
658
659 /* max TIC (bits 4:8) & TSC bindings, per program type */
660 for (i = 0; i < 3; ++i) {
661 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
662 PUSH_DATA (push, 0x54);
663 }
664
665 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
666 PUSH_DATAh(push, screen->txc->offset);
667 PUSH_DATA (push, screen->txc->offset);
668 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
669
670 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
671 PUSH_DATAh(push, screen->txc->offset + 65536);
672 PUSH_DATA (push, screen->txc->offset + 65536);
673 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
674
675 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
676 PUSH_DATA (push, 0);
677
678 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
679 PUSH_DATA (push, 0);
680 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
681 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
682 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
683 for (i = 0; i < 8 * 2; ++i)
684 PUSH_DATA(push, 0);
685 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
686 PUSH_DATA (push, 0);
687
688 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
689 PUSH_DATA (push, 1);
690 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
691 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
692 PUSH_DATAf(push, 0.0f);
693 PUSH_DATAf(push, 1.0f);
694 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
695 PUSH_DATA (push, 8192 << 16);
696 PUSH_DATA (push, 8192 << 16);
697 }
698
699 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
700 #ifdef NV50_SCISSORS_CLIPPING
701 PUSH_DATA (push, 0x0000);
702 #else
703 PUSH_DATA (push, 0x1080);
704 #endif
705
706 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
707 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
708
709 /* We use scissors instead of exact view volume clipping,
710 * so they're always enabled.
711 */
712 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
713 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
714 PUSH_DATA (push, 1);
715 PUSH_DATA (push, 8192 << 16);
716 PUSH_DATA (push, 8192 << 16);
717 }
718
719 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
720 PUSH_DATA (push, 1);
721 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
722 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
723 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
724 PUSH_DATA (push, 0x11111111);
725 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
726 PUSH_DATA (push, 1);
727
728 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
729 PUSH_DATA (push, 0);
730 if (screen->base.class_3d >= NV84_3D_CLASS) {
731 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
732 PUSH_DATA (push, 0);
733 }
734
735 PUSH_KICK (push);
736 }
737
738 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
739 uint64_t *tls_size)
740 {
741 struct nouveau_device *dev = screen->base.device;
742 int ret;
743
744 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
745 ONE_TEMP_SIZE;
746 if (nouveau_mesa_debug)
747 debug_printf("allocating space for %u temps\n",
748 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
749 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
750 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
751
752 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
753 *tls_size, NULL, &screen->tls_bo);
754 if (ret) {
755 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
756 return ret;
757 }
758
759 return 0;
760 }
761
762 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
763 {
764 struct nouveau_pushbuf *push = screen->base.pushbuf;
765 int ret;
766 uint64_t tls_size;
767
768 if (tls_space < screen->cur_tls_space)
769 return 0;
770 if (tls_space > screen->max_tls_space) {
771 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
772 * LOCAL_WARPS_NO_CLAMP) */
773 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
774 (unsigned)(tls_space / ONE_TEMP_SIZE),
775 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
776 return -ENOMEM;
777 }
778
779 nouveau_bo_ref(NULL, &screen->tls_bo);
780 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
781 if (ret)
782 return ret;
783
784 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
785 PUSH_DATAh(push, screen->tls_bo->offset);
786 PUSH_DATA (push, screen->tls_bo->offset);
787 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
788
789 return 1;
790 }
791
792 struct nouveau_screen *
793 nv50_screen_create(struct nouveau_device *dev)
794 {
795 struct nv50_screen *screen;
796 struct pipe_screen *pscreen;
797 struct nouveau_object *chan;
798 uint64_t value;
799 uint32_t tesla_class;
800 unsigned stack_size;
801 int ret;
802
803 screen = CALLOC_STRUCT(nv50_screen);
804 if (!screen)
805 return NULL;
806 pscreen = &screen->base.base;
807 pscreen->destroy = nv50_screen_destroy;
808
809 ret = nouveau_screen_init(&screen->base, dev);
810 if (ret) {
811 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
812 goto fail;
813 }
814
815 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
816 * admit them to VRAM.
817 */
818 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
819 PIPE_BIND_VERTEX_BUFFER;
820 screen->base.sysmem_bindings |=
821 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
822
823 screen->base.pushbuf->user_priv = screen;
824 screen->base.pushbuf->rsvd_kick = 5;
825
826 chan = screen->base.channel;
827
828 pscreen->context_create = nv50_create;
829 pscreen->is_format_supported = nv50_screen_is_format_supported;
830 pscreen->get_param = nv50_screen_get_param;
831 pscreen->get_shader_param = nv50_screen_get_shader_param;
832 pscreen->get_paramf = nv50_screen_get_paramf;
833 pscreen->get_compute_param = nv50_screen_get_compute_param;
834 pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
835 pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
836
837 nv50_screen_init_resource_functions(pscreen);
838
839 if (screen->base.device->chipset < 0x84 ||
840 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
841 /* PMPEG */
842 nouveau_screen_init_vdec(&screen->base);
843 } else if (screen->base.device->chipset < 0x98 ||
844 screen->base.device->chipset == 0xa0) {
845 /* VP2 */
846 screen->base.base.get_video_param = nv84_screen_get_video_param;
847 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
848 } else {
849 /* VP3/4 */
850 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
851 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
852 }
853
854 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
855 NULL, &screen->fence.bo);
856 if (ret) {
857 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
858 goto fail;
859 }
860
861 nouveau_bo_map(screen->fence.bo, 0, NULL);
862 screen->fence.map = screen->fence.bo->map;
863 screen->base.fence.emit = nv50_screen_fence_emit;
864 screen->base.fence.update = nv50_screen_fence_update;
865
866 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
867 &(struct nv04_notify){ .length = 32 },
868 sizeof(struct nv04_notify), &screen->sync);
869 if (ret) {
870 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
871 goto fail;
872 }
873
874 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
875 NULL, 0, &screen->m2mf);
876 if (ret) {
877 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
878 goto fail;
879 }
880
881 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
882 NULL, 0, &screen->eng2d);
883 if (ret) {
884 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
885 goto fail;
886 }
887
888 switch (dev->chipset & 0xf0) {
889 case 0x50:
890 tesla_class = NV50_3D_CLASS;
891 break;
892 case 0x80:
893 case 0x90:
894 tesla_class = NV84_3D_CLASS;
895 break;
896 case 0xa0:
897 switch (dev->chipset) {
898 case 0xa0:
899 case 0xaa:
900 case 0xac:
901 tesla_class = NVA0_3D_CLASS;
902 break;
903 case 0xaf:
904 tesla_class = NVAF_3D_CLASS;
905 break;
906 default:
907 tesla_class = NVA3_3D_CLASS;
908 break;
909 }
910 break;
911 default:
912 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
913 goto fail;
914 }
915 screen->base.class_3d = tesla_class;
916
917 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
918 NULL, 0, &screen->tesla);
919 if (ret) {
920 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
921 goto fail;
922 }
923
924 /* This over-allocates by a page. The GP, which would execute at the end of
925 * the last page, would trigger faults. The going theory is that it
926 * prefetches up to a certain amount.
927 */
928 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
929 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
930 NULL, &screen->code);
931 if (ret) {
932 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
933 goto fail;
934 }
935
936 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
937 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
938 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
939
940 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
941
942 screen->TPs = util_bitcount(value & 0xffff);
943 screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
944
945 screen->mp_count = screen->TPs * screen->MPsInTP;
946
947 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
948 STACK_WARPS_ALLOC * 64 * 8;
949
950 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
951 &screen->stack_bo);
952 if (ret) {
953 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
954 goto fail;
955 }
956
957 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
958 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
959 ONE_TEMP_SIZE;
960 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
961 screen->max_tls_space /= 2; /* half of vram */
962
963 /* hw can address max 64 KiB */
964 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
965
966 uint64_t tls_size;
967 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
968 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
969 if (ret)
970 goto fail;
971
972 if (nouveau_mesa_debug)
973 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
974 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
975
976 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
977 &screen->uniforms);
978 if (ret) {
979 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
980 goto fail;
981 }
982
983 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
984 &screen->txc);
985 if (ret) {
986 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
987 goto fail;
988 }
989
990 screen->tic.entries = CALLOC(4096, sizeof(void *));
991 screen->tsc.entries = screen->tic.entries + 2048;
992
993 if (!nv50_blitter_create(screen))
994 goto fail;
995
996 nv50_screen_init_hwctx(screen);
997
998 ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
999 if (ret) {
1000 NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1001 goto fail;
1002 }
1003
1004 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1005
1006 return &screen->base;
1007
1008 fail:
1009 screen->base.base.context_create = NULL;
1010 return &screen->base;
1011 }
1012
1013 int
1014 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1015 {
1016 int i = screen->tic.next;
1017
1018 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1019 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1020
1021 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1022
1023 if (screen->tic.entries[i])
1024 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1025
1026 screen->tic.entries[i] = entry;
1027 return i;
1028 }
1029
1030 int
1031 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1032 {
1033 int i = screen->tsc.next;
1034
1035 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1036 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1037
1038 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1039
1040 if (screen->tsc.entries[i])
1041 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1042
1043 screen->tsc.entries[i] = entry;
1044 return i;
1045 }