2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
33 #include "nouveau_vp3_video.h"
35 #include "nv_object.xml.h"
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
42 #define THREADS_IN_WARP 32
45 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
46 enum pipe_format format
,
47 enum pipe_texture_target target
,
48 unsigned sample_count
,
53 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
55 if (sample_count
== 8 && util_format_get_blocksizebits(format
) >= 128)
58 if (!util_format_is_supported(format
, bindings
))
62 case PIPE_FORMAT_Z16_UNORM
:
63 if (nv50_screen(pscreen
)->tesla
->oclass
< NVA0_3D_CLASS
)
70 /* transfers & shared are always supported */
71 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
72 PIPE_BIND_TRANSFER_WRITE
|
75 return (nv50_format_table
[format
].usage
& bindings
) == bindings
;
79 nv50_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
81 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
82 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
85 /* non-boolean caps */
86 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
88 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
90 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
92 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
94 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
95 case PIPE_CAP_MIN_TEXEL_OFFSET
:
97 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
98 case PIPE_CAP_MAX_TEXEL_OFFSET
:
100 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
101 return 128 * 1024 * 1024;
102 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
104 case PIPE_CAP_MAX_RENDER_TARGETS
:
106 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
108 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
110 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
111 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
113 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
114 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
116 case PIPE_CAP_MAX_VERTEX_STREAMS
:
118 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
120 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
122 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
123 return 1; /* 256 for binding as RT, but that's not possible in GL */
124 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
125 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
126 case PIPE_CAP_MAX_VIEWPORTS
:
127 return NV50_MAX_VIEWPORTS
;
128 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
129 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50
;
130 case PIPE_CAP_ENDIANNESS
:
131 return PIPE_ENDIAN_LITTLE
;
132 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
133 return (class_3d
>= NVA3_3D_CLASS
) ? 4 : 0;
136 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
137 case PIPE_CAP_TEXTURE_SWIZZLE
:
138 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
139 case PIPE_CAP_NPOT_TEXTURES
:
140 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
141 case PIPE_CAP_ANISOTROPIC_FILTER
:
142 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
143 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
144 case PIPE_CAP_TWO_SIDED_STENCIL
:
145 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
146 case PIPE_CAP_POINT_SPRITE
:
148 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
149 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
150 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
151 case PIPE_CAP_QUERY_TIMESTAMP
:
152 case PIPE_CAP_QUERY_TIME_ELAPSED
:
153 case PIPE_CAP_OCCLUSION_QUERY
:
154 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
155 case PIPE_CAP_INDEP_BLEND_ENABLE
:
156 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
157 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
158 case PIPE_CAP_PRIMITIVE_RESTART
:
159 case PIPE_CAP_TGSI_INSTANCEID
:
160 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
161 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
162 case PIPE_CAP_CONDITIONAL_RENDER
:
163 case PIPE_CAP_TEXTURE_BARRIER
:
164 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
165 case PIPE_CAP_START_INSTANCE
:
166 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
167 case PIPE_CAP_USER_INDEX_BUFFERS
:
168 case PIPE_CAP_USER_VERTEX_BUFFERS
:
169 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
170 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
171 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
172 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
173 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
174 case PIPE_CAP_CLIP_HALFZ
:
175 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
176 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
177 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
178 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
179 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
180 case PIPE_CAP_TGSI_TXQS
:
181 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
182 case PIPE_CAP_SHAREABLE_SHADERS
:
183 case PIPE_CAP_CLEAR_TEXTURE
:
184 case PIPE_CAP_COMPUTE
:
186 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
187 return 1; /* class_3d >= NVA0_3D_CLASS; */
188 /* supported on nva0+ */
189 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
190 return class_3d
>= NVA0_3D_CLASS
;
191 /* supported on nva3+ */
192 case PIPE_CAP_CUBE_MAP_ARRAY
:
193 case PIPE_CAP_INDEP_BLEND_FUNC
:
194 case PIPE_CAP_TEXTURE_QUERY_LOD
:
195 case PIPE_CAP_SAMPLE_SHADING
:
196 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
197 return class_3d
>= NVA3_3D_CLASS
;
199 /* unsupported caps */
200 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
201 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
202 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
203 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
204 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
205 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
206 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
207 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
208 case PIPE_CAP_TGSI_TEXCOORD
:
209 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
210 case PIPE_CAP_TEXTURE_GATHER_SM5
:
211 case PIPE_CAP_FAKE_SW_MSAA
:
212 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
213 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
214 case PIPE_CAP_DRAW_INDIRECT
:
215 case PIPE_CAP_VERTEXID_NOBASE
:
216 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
: /* potentially supported on some hw */
217 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
218 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
219 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
222 case PIPE_CAP_VENDOR_ID
:
224 case PIPE_CAP_DEVICE_ID
: {
226 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
227 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
232 case PIPE_CAP_ACCELERATED
:
234 case PIPE_CAP_VIDEO_MEMORY
:
235 return dev
->vram_size
>> 20;
240 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
245 nv50_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
246 enum pipe_shader_cap param
)
249 case PIPE_SHADER_VERTEX
:
250 case PIPE_SHADER_GEOMETRY
:
251 case PIPE_SHADER_FRAGMENT
:
252 case PIPE_SHADER_COMPUTE
:
259 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
260 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
261 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
262 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
264 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
266 case PIPE_SHADER_CAP_MAX_INPUTS
:
267 if (shader
== PIPE_SHADER_VERTEX
)
270 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
272 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
274 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
275 return NV50_MAX_PIPE_CONSTBUFS
;
276 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
277 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
278 return shader
!= PIPE_SHADER_FRAGMENT
;
279 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
280 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
282 case PIPE_SHADER_CAP_MAX_PREDS
:
284 case PIPE_SHADER_CAP_MAX_TEMPS
:
285 return nv50_screen(pscreen
)->max_tls_space
/ ONE_TEMP_SIZE
;
286 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
288 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
290 case PIPE_SHADER_CAP_SUBROUTINES
:
291 return 0; /* please inline, or provide function declarations */
292 case PIPE_SHADER_CAP_INTEGERS
:
294 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
295 /* The chip could handle more sampler views than samplers */
296 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
297 return MIN2(16, PIPE_MAX_SAMPLERS
);
298 case PIPE_SHADER_CAP_DOUBLES
:
299 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
300 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
301 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
302 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
304 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
307 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
313 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
316 case PIPE_CAPF_MAX_LINE_WIDTH
:
317 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
319 case PIPE_CAPF_MAX_POINT_WIDTH
:
320 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
322 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
324 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
326 case PIPE_CAPF_GUARD_BAND_LEFT
:
327 case PIPE_CAPF_GUARD_BAND_TOP
:
329 case PIPE_CAPF_GUARD_BAND_RIGHT
:
330 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
331 return 0.0f
; /* that or infinity */
334 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param
);
339 nv50_screen_get_compute_param(struct pipe_screen
*pscreen
,
340 enum pipe_compute_cap param
, void *data
)
342 struct nv50_screen
*screen
= nv50_screen(pscreen
);
344 #define RET(x) do { \
346 memcpy(data, x, sizeof(x)); \
351 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
352 RET((uint64_t []) { 2 });
353 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
354 RET(((uint64_t []) { 65535, 65535 }));
355 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
356 RET(((uint64_t []) { 512, 512, 64 }));
357 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
358 RET((uint64_t []) { 512 });
359 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
: /* g0-15[] */
360 RET((uint64_t []) { 1ULL << 32 });
361 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
: /* s[] */
362 RET((uint64_t []) { 16 << 10 });
363 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
: /* l[] */
364 RET((uint64_t []) { 16 << 10 });
365 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
: /* c[], arbitrary limit */
366 RET((uint64_t []) { 4096 });
367 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
368 RET((uint32_t []) { 32 });
369 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
370 RET((uint64_t []) { 1ULL << 40 });
371 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
372 RET((uint32_t []) { 0 });
373 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
374 RET((uint32_t []) { screen
->mp_count
});
375 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
376 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
385 nv50_screen_destroy(struct pipe_screen
*pscreen
)
387 struct nv50_screen
*screen
= nv50_screen(pscreen
);
389 if (!nouveau_drm_screen_unref(&screen
->base
))
392 if (screen
->base
.fence
.current
) {
393 struct nouveau_fence
*current
= NULL
;
395 /* nouveau_fence_wait will create a new current fence, so wait on the
396 * _current_ one, and remove both.
398 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
399 nouveau_fence_wait(current
, NULL
);
400 nouveau_fence_ref(NULL
, ¤t
);
401 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
403 if (screen
->base
.pushbuf
)
404 screen
->base
.pushbuf
->user_priv
= NULL
;
407 nv50_blitter_destroy(screen
);
409 nouveau_bo_ref(NULL
, &screen
->code
);
410 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
411 nouveau_bo_ref(NULL
, &screen
->stack_bo
);
412 nouveau_bo_ref(NULL
, &screen
->txc
);
413 nouveau_bo_ref(NULL
, &screen
->uniforms
);
414 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
416 nouveau_heap_destroy(&screen
->vp_code_heap
);
417 nouveau_heap_destroy(&screen
->gp_code_heap
);
418 nouveau_heap_destroy(&screen
->fp_code_heap
);
420 FREE(screen
->tic
.entries
);
422 nouveau_object_del(&screen
->tesla
);
423 nouveau_object_del(&screen
->eng2d
);
424 nouveau_object_del(&screen
->m2mf
);
425 nouveau_object_del(&screen
->compute
);
426 nouveau_object_del(&screen
->sync
);
428 nouveau_screen_fini(&screen
->base
);
434 nv50_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
436 struct nv50_screen
*screen
= nv50_screen(pscreen
);
437 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
439 /* we need to do it after possible flush in MARK_RING */
440 *sequence
= ++screen
->base
.fence
.sequence
;
442 assert(PUSH_AVAIL(push
) + push
->rsvd_kick
>= 5);
443 PUSH_DATA (push
, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH
), 4));
444 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
445 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
446 PUSH_DATA (push
, *sequence
);
447 PUSH_DATA (push
, NV50_3D_QUERY_GET_MODE_WRITE_UNK0
|
448 NV50_3D_QUERY_GET_UNK4
|
449 NV50_3D_QUERY_GET_UNIT_CROP
|
450 NV50_3D_QUERY_GET_TYPE_QUERY
|
451 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO
|
452 NV50_3D_QUERY_GET_SHORT
);
456 nv50_screen_fence_update(struct pipe_screen
*pscreen
)
458 return nv50_screen(pscreen
)->fence
.map
[0];
462 nv50_screen_init_hwctx(struct nv50_screen
*screen
)
464 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
465 struct nv04_fifo
*fifo
;
468 fifo
= (struct nv04_fifo
*)screen
->base
.channel
->data
;
470 BEGIN_NV04(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
471 PUSH_DATA (push
, screen
->m2mf
->handle
);
472 BEGIN_NV04(push
, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY
), 3);
473 PUSH_DATA (push
, screen
->sync
->handle
);
474 PUSH_DATA (push
, fifo
->vram
);
475 PUSH_DATA (push
, fifo
->vram
);
477 BEGIN_NV04(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
478 PUSH_DATA (push
, screen
->eng2d
->handle
);
479 BEGIN_NV04(push
, NV50_2D(DMA_NOTIFY
), 4);
480 PUSH_DATA (push
, screen
->sync
->handle
);
481 PUSH_DATA (push
, fifo
->vram
);
482 PUSH_DATA (push
, fifo
->vram
);
483 PUSH_DATA (push
, fifo
->vram
);
484 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
485 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
486 BEGIN_NV04(push
, NV50_2D(CLIP_ENABLE
), 1);
488 BEGIN_NV04(push
, NV50_2D(COLOR_KEY_ENABLE
), 1);
490 BEGIN_NV04(push
, SUBC_2D(0x0888), 1);
492 BEGIN_NV04(push
, NV50_2D(COND_MODE
), 1);
493 PUSH_DATA (push
, NV50_2D_COND_MODE_ALWAYS
);
495 BEGIN_NV04(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
496 PUSH_DATA (push
, screen
->tesla
->handle
);
498 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
499 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
501 BEGIN_NV04(push
, NV50_3D(DMA_NOTIFY
), 1);
502 PUSH_DATA (push
, screen
->sync
->handle
);
503 BEGIN_NV04(push
, NV50_3D(DMA_ZETA
), 11);
504 for (i
= 0; i
< 11; ++i
)
505 PUSH_DATA(push
, fifo
->vram
);
506 BEGIN_NV04(push
, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN
);
507 for (i
= 0; i
< NV50_3D_DMA_COLOR__LEN
; ++i
)
508 PUSH_DATA(push
, fifo
->vram
);
510 BEGIN_NV04(push
, NV50_3D(REG_MODE
), 1);
511 PUSH_DATA (push
, NV50_3D_REG_MODE_STRIPED
);
512 BEGIN_NV04(push
, NV50_3D(UNK1400_LANES
), 1);
513 PUSH_DATA (push
, 0xf);
515 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
516 BEGIN_NV04(push
, NV50_3D(WATCHDOG_TIMER
), 1);
517 PUSH_DATA (push
, 0x18);
520 BEGIN_NV04(push
, NV50_3D(ZETA_COMP_ENABLE
), 1);
521 PUSH_DATA(push
, screen
->base
.device
->drm_version
>= 0x01000101);
523 BEGIN_NV04(push
, NV50_3D(RT_COMP_ENABLE(0)), 8);
524 for (i
= 0; i
< 8; ++i
)
525 PUSH_DATA(push
, screen
->base
.device
->drm_version
>= 0x01000101);
527 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
530 BEGIN_NV04(push
, NV50_3D(CSAA_ENABLE
), 1);
532 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_ENABLE
), 1);
534 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
535 PUSH_DATA (push
, NV50_3D_MULTISAMPLE_MODE_MS1
);
536 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_CTRL
), 1);
538 BEGIN_NV04(push
, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS
), 1);
540 BEGIN_NV04(push
, NV50_3D(BLEND_SEPARATE_ALPHA
), 1);
543 if (screen
->tesla
->oclass
>= NVA0_3D_CLASS
) {
544 BEGIN_NV04(push
, SUBC_3D(NVA0_3D_TEX_MISC
), 1);
545 PUSH_DATA (push
, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP
);
548 BEGIN_NV04(push
, NV50_3D(SCREEN_Y_CONTROL
), 1);
550 BEGIN_NV04(push
, NV50_3D(WINDOW_OFFSET_X
), 2);
553 BEGIN_NV04(push
, NV50_3D(ZCULL_REGION
), 1);
554 PUSH_DATA (push
, 0x3f);
556 BEGIN_NV04(push
, NV50_3D(VP_ADDRESS_HIGH
), 2);
557 PUSH_DATAh(push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
558 PUSH_DATA (push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
560 BEGIN_NV04(push
, NV50_3D(FP_ADDRESS_HIGH
), 2);
561 PUSH_DATAh(push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
562 PUSH_DATA (push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
564 BEGIN_NV04(push
, NV50_3D(GP_ADDRESS_HIGH
), 2);
565 PUSH_DATAh(push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
566 PUSH_DATA (push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
568 BEGIN_NV04(push
, NV50_3D(LOCAL_ADDRESS_HIGH
), 3);
569 PUSH_DATAh(push
, screen
->tls_bo
->offset
);
570 PUSH_DATA (push
, screen
->tls_bo
->offset
);
571 PUSH_DATA (push
, util_logbase2(screen
->cur_tls_space
/ 8));
573 BEGIN_NV04(push
, NV50_3D(STACK_ADDRESS_HIGH
), 3);
574 PUSH_DATAh(push
, screen
->stack_bo
->offset
);
575 PUSH_DATA (push
, screen
->stack_bo
->offset
);
578 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
579 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (0 << 16));
580 PUSH_DATA (push
, screen
->uniforms
->offset
+ (0 << 16));
581 PUSH_DATA (push
, (NV50_CB_PVP
<< 16) | 0x0000);
583 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
584 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (1 << 16));
585 PUSH_DATA (push
, screen
->uniforms
->offset
+ (1 << 16));
586 PUSH_DATA (push
, (NV50_CB_PGP
<< 16) | 0x0000);
588 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
589 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (2 << 16));
590 PUSH_DATA (push
, screen
->uniforms
->offset
+ (2 << 16));
591 PUSH_DATA (push
, (NV50_CB_PFP
<< 16) | 0x0000);
593 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
594 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (3 << 16));
595 PUSH_DATA (push
, screen
->uniforms
->offset
+ (3 << 16));
596 PUSH_DATA (push
, (NV50_CB_AUX
<< 16) | (NV50_CB_AUX_SIZE
& 0xffff));
598 BEGIN_NI04(push
, NV50_3D(SET_PROGRAM_CB
), 3);
599 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf01);
600 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf21);
601 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf31);
603 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
604 BEGIN_NV04(push
, NV50_3D(CB_ADDR
), 1);
605 PUSH_DATA (push
, (NV50_CB_AUX_RUNOUT_OFFSET
<< (8 - 2)) | NV50_CB_AUX
);
606 BEGIN_NI04(push
, NV50_3D(CB_DATA(0)), 4);
607 PUSH_DATAf(push
, 0.0f
);
608 PUSH_DATAf(push
, 0.0f
);
609 PUSH_DATAf(push
, 0.0f
);
610 PUSH_DATAf(push
, 0.0f
);
611 BEGIN_NV04(push
, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
612 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET
);
613 PUSH_DATA (push
, screen
->uniforms
->offset
+ (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET
);
615 nv50_upload_ms_info(push
);
617 /* max TIC (bits 4:8) & TSC bindings, per program type */
618 for (i
= 0; i
< 3; ++i
) {
619 BEGIN_NV04(push
, NV50_3D(TEX_LIMITS(i
)), 1);
620 PUSH_DATA (push
, 0x54);
623 BEGIN_NV04(push
, NV50_3D(TIC_ADDRESS_HIGH
), 3);
624 PUSH_DATAh(push
, screen
->txc
->offset
);
625 PUSH_DATA (push
, screen
->txc
->offset
);
626 PUSH_DATA (push
, NV50_TIC_MAX_ENTRIES
- 1);
628 BEGIN_NV04(push
, NV50_3D(TSC_ADDRESS_HIGH
), 3);
629 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
630 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
631 PUSH_DATA (push
, NV50_TSC_MAX_ENTRIES
- 1);
633 BEGIN_NV04(push
, NV50_3D(LINKED_TSC
), 1);
636 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_EN
), 1);
638 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_MODE
), 1);
639 PUSH_DATA (push
, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
640 BEGIN_NV04(push
, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
641 for (i
= 0; i
< 8 * 2; ++i
)
643 BEGIN_NV04(push
, NV50_3D(CLIPID_ENABLE
), 1);
646 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
648 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
649 BEGIN_NV04(push
, NV50_3D(DEPTH_RANGE_NEAR(i
)), 2);
650 PUSH_DATAf(push
, 0.0f
);
651 PUSH_DATAf(push
, 1.0f
);
652 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(i
)), 2);
653 PUSH_DATA (push
, 8192 << 16);
654 PUSH_DATA (push
, 8192 << 16);
657 BEGIN_NV04(push
, NV50_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
658 #ifdef NV50_SCISSORS_CLIPPING
659 PUSH_DATA (push
, 0x0000);
661 PUSH_DATA (push
, 0x1080);
664 BEGIN_NV04(push
, NV50_3D(CLEAR_FLAGS
), 1);
665 PUSH_DATA (push
, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT
);
667 /* We use scissors instead of exact view volume clipping,
668 * so they're always enabled.
670 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
671 BEGIN_NV04(push
, NV50_3D(SCISSOR_ENABLE(i
)), 3);
673 PUSH_DATA (push
, 8192 << 16);
674 PUSH_DATA (push
, 8192 << 16);
677 BEGIN_NV04(push
, NV50_3D(RASTERIZE_ENABLE
), 1);
679 BEGIN_NV04(push
, NV50_3D(POINT_RASTER_RULES
), 1);
680 PUSH_DATA (push
, NV50_3D_POINT_RASTER_RULES_OGL
);
681 BEGIN_NV04(push
, NV50_3D(FRAG_COLOR_CLAMP_EN
), 1);
682 PUSH_DATA (push
, 0x11111111);
683 BEGIN_NV04(push
, NV50_3D(EDGEFLAG
), 1);
686 BEGIN_NV04(push
, NV50_3D(VB_ELEMENT_BASE
), 1);
688 if (screen
->base
.class_3d
>= NV84_3D_CLASS
) {
689 BEGIN_NV04(push
, NV84_3D(VERTEX_ID_BASE
), 1);
696 static int nv50_tls_alloc(struct nv50_screen
*screen
, unsigned tls_space
,
699 struct nouveau_device
*dev
= screen
->base
.device
;
702 screen
->cur_tls_space
= util_next_power_of_two(tls_space
/ ONE_TEMP_SIZE
) *
704 if (nouveau_mesa_debug
)
705 debug_printf("allocating space for %u temps\n",
706 util_next_power_of_two(tls_space
/ ONE_TEMP_SIZE
));
707 *tls_size
= screen
->cur_tls_space
* util_next_power_of_two(screen
->TPs
) *
708 screen
->MPsInTP
* LOCAL_WARPS_ALLOC
* THREADS_IN_WARP
;
710 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
711 *tls_size
, NULL
, &screen
->tls_bo
);
713 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret
);
720 int nv50_tls_realloc(struct nv50_screen
*screen
, unsigned tls_space
)
722 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
726 if (tls_space
< screen
->cur_tls_space
)
728 if (tls_space
> screen
->max_tls_space
) {
729 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
730 * LOCAL_WARPS_NO_CLAMP) */
731 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
732 (unsigned)(tls_space
/ ONE_TEMP_SIZE
),
733 (unsigned)(screen
->max_tls_space
/ ONE_TEMP_SIZE
));
737 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
738 ret
= nv50_tls_alloc(screen
, tls_space
, &tls_size
);
742 BEGIN_NV04(push
, NV50_3D(LOCAL_ADDRESS_HIGH
), 3);
743 PUSH_DATAh(push
, screen
->tls_bo
->offset
);
744 PUSH_DATA (push
, screen
->tls_bo
->offset
);
745 PUSH_DATA (push
, util_logbase2(screen
->cur_tls_space
/ 8));
751 nv50_screen_create(struct nouveau_device
*dev
)
753 struct nv50_screen
*screen
;
754 struct pipe_screen
*pscreen
;
755 struct nouveau_object
*chan
;
757 uint32_t tesla_class
;
761 screen
= CALLOC_STRUCT(nv50_screen
);
764 pscreen
= &screen
->base
.base
;
766 ret
= nouveau_screen_init(&screen
->base
, dev
);
768 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret
);
772 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
773 * admit them to VRAM.
775 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
776 PIPE_BIND_VERTEX_BUFFER
;
777 screen
->base
.sysmem_bindings
|=
778 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
780 screen
->base
.pushbuf
->user_priv
= screen
;
781 screen
->base
.pushbuf
->rsvd_kick
= 5;
783 chan
= screen
->base
.channel
;
785 pscreen
->destroy
= nv50_screen_destroy
;
786 pscreen
->context_create
= nv50_create
;
787 pscreen
->is_format_supported
= nv50_screen_is_format_supported
;
788 pscreen
->get_param
= nv50_screen_get_param
;
789 pscreen
->get_shader_param
= nv50_screen_get_shader_param
;
790 pscreen
->get_paramf
= nv50_screen_get_paramf
;
791 pscreen
->get_compute_param
= nv50_screen_get_compute_param
;
792 pscreen
->get_driver_query_info
= nv50_screen_get_driver_query_info
;
794 nv50_screen_init_resource_functions(pscreen
);
796 if (screen
->base
.device
->chipset
< 0x84 ||
797 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
799 nouveau_screen_init_vdec(&screen
->base
);
800 } else if (screen
->base
.device
->chipset
< 0x98 ||
801 screen
->base
.device
->chipset
== 0xa0) {
803 screen
->base
.base
.get_video_param
= nv84_screen_get_video_param
;
804 screen
->base
.base
.is_video_format_supported
= nv84_screen_video_supported
;
807 screen
->base
.base
.get_video_param
= nouveau_vp3_screen_get_video_param
;
808 screen
->base
.base
.is_video_format_supported
= nouveau_vp3_screen_video_supported
;
811 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096,
812 NULL
, &screen
->fence
.bo
);
814 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret
);
818 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
819 screen
->fence
.map
= screen
->fence
.bo
->map
;
820 screen
->base
.fence
.emit
= nv50_screen_fence_emit
;
821 screen
->base
.fence
.update
= nv50_screen_fence_update
;
823 ret
= nouveau_object_new(chan
, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS
,
824 &(struct nv04_notify
){ .length
= 32 },
825 sizeof(struct nv04_notify
), &screen
->sync
);
827 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret
);
831 ret
= nouveau_object_new(chan
, 0xbeef5039, NV50_M2MF_CLASS
,
832 NULL
, 0, &screen
->m2mf
);
834 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret
);
838 ret
= nouveau_object_new(chan
, 0xbeef502d, NV50_2D_CLASS
,
839 NULL
, 0, &screen
->eng2d
);
841 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret
);
845 switch (dev
->chipset
& 0xf0) {
847 tesla_class
= NV50_3D_CLASS
;
851 tesla_class
= NV84_3D_CLASS
;
854 switch (dev
->chipset
) {
858 tesla_class
= NVA0_3D_CLASS
;
861 tesla_class
= NVAF_3D_CLASS
;
864 tesla_class
= NVA3_3D_CLASS
;
869 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev
->chipset
);
872 screen
->base
.class_3d
= tesla_class
;
874 ret
= nouveau_object_new(chan
, 0xbeef5097, tesla_class
,
875 NULL
, 0, &screen
->tesla
);
877 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret
);
881 /* This over-allocates by a page. The GP, which would execute at the end of
882 * the last page, would trigger faults. The going theory is that it
883 * prefetches up to a certain amount.
885 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
886 (3 << NV50_CODE_BO_SIZE_LOG2
) + 0x1000,
887 NULL
, &screen
->code
);
889 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret
);
893 nouveau_heap_init(&screen
->vp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
894 nouveau_heap_init(&screen
->gp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
895 nouveau_heap_init(&screen
->fp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
897 nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
899 screen
->TPs
= util_bitcount(value
& 0xffff);
900 screen
->MPsInTP
= util_bitcount((value
>> 24) & 0xf);
902 screen
->mp_count
= screen
->TPs
* screen
->MPsInTP
;
904 stack_size
= util_next_power_of_two(screen
->TPs
) * screen
->MPsInTP
*
905 STACK_WARPS_ALLOC
* 64 * 8;
907 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, stack_size
, NULL
,
910 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret
);
914 uint64_t size_of_one_temp
= util_next_power_of_two(screen
->TPs
) *
915 screen
->MPsInTP
* LOCAL_WARPS_ALLOC
* THREADS_IN_WARP
*
917 screen
->max_tls_space
= dev
->vram_size
/ size_of_one_temp
* ONE_TEMP_SIZE
;
918 screen
->max_tls_space
/= 2; /* half of vram */
920 /* hw can address max 64 KiB */
921 screen
->max_tls_space
= MIN2(screen
->max_tls_space
, 64 << 10);
924 unsigned tls_space
= 4/*temps*/ * ONE_TEMP_SIZE
;
925 ret
= nv50_tls_alloc(screen
, tls_space
, &tls_size
);
929 if (nouveau_mesa_debug
)
930 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64
" MiB, tls_size = %"PRIu64
" KiB\n",
931 screen
->TPs
, screen
->MPsInTP
, dev
->vram_size
>> 20, tls_size
>> 10);
933 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 4 << 16, NULL
,
936 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret
);
940 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 3 << 16, NULL
,
943 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret
);
947 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
948 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
950 if (!nv50_blitter_create(screen
))
953 nv50_screen_init_hwctx(screen
);
955 ret
= nv50_screen_compute_setup(screen
, screen
->base
.pushbuf
);
957 NOUVEAU_ERR("Failed to init compute context: %d\n", ret
);
961 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, false);
966 nv50_screen_destroy(pscreen
);
971 nv50_screen_tic_alloc(struct nv50_screen
*screen
, void *entry
)
973 int i
= screen
->tic
.next
;
975 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
976 i
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
978 screen
->tic
.next
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
980 if (screen
->tic
.entries
[i
])
981 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
983 screen
->tic
.entries
[i
] = entry
;
988 nv50_screen_tsc_alloc(struct nv50_screen
*screen
, void *entry
)
990 int i
= screen
->tsc
.next
;
992 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
993 i
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
995 screen
->tsc
.next
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
997 if (screen
->tsc
.entries
[i
])
998 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
1000 screen
->tsc
.entries
[i
] = entry
;