src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50/nv50_context.h"
  28 #include "nv50/nv50_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nv_object.xml.h"
  33 #include <errno.h>
  34
  35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  37 #endif
  38
  39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  40 #define LOCAL_WARPS_ALLOC 32
  41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  42 #define STACK_WARPS_ALLOC 32
  43
  44 #define THREADS_IN_WARP 32
  45
  46 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  47
  48 static boolean
  49 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  50                                 enum pipe_format format,
  51                                 enum pipe_texture_target target,
  52                                 unsigned sample_count,
  53                                 unsigned bindings)
  54 {
  55    if (sample_count > 8)
  56       return FALSE;
  57    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  58       return FALSE;
  59    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  60       return FALSE;
  61
  62    if (!util_format_is_supported(format, bindings))
  63       return FALSE;
  64
  65    switch (format) {
  66    case PIPE_FORMAT_Z16_UNORM:
  67       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  68          return FALSE;
  69       break;
  70    default:
  71       break;
  72    }
  73
  74    /* transfers & shared are always supported */
  75    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  76                  PIPE_BIND_TRANSFER_WRITE |
  77                  PIPE_BIND_SHARED);
  78
  79    return (nv50_format_table[format].usage & bindings) == bindings;
  80 }
  81
  82 static int
  83 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  84 {
  85    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  86
  87    switch (param) {
  88    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  89       return 14;
  90    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  91       return 12;
  92    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  93       return 14;
  94    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  95       return 512;
  96    case PIPE_CAP_MIN_TEXEL_OFFSET:
  97       return -8;
  98    case PIPE_CAP_MAX_TEXEL_OFFSET:
  99       return 7;
 100    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 101    case PIPE_CAP_TEXTURE_SWIZZLE:
 102    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 103    case PIPE_CAP_NPOT_TEXTURES:
 104    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 105    case PIPE_CAP_ANISOTROPIC_FILTER:
 106    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 107       return 1;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 65536;
 110    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 111       return 1; /* nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS; */
 112    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 113       return 0;
 114    case PIPE_CAP_CUBE_MAP_ARRAY:
 115       return 0;
 116       /*
 117       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 118       */
 119    case PIPE_CAP_TWO_SIDED_STENCIL:
 120    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 121    case PIPE_CAP_POINT_SPRITE:
 122       return 1;
 123    case PIPE_CAP_SM3:
 124       return 1;
 125    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 126       return 330;
 127    case PIPE_CAP_MAX_RENDER_TARGETS:
 128       return 8;
 129    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 130       return 1;
 131    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 132    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 133    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 134       return 1;
 135    case PIPE_CAP_QUERY_TIMESTAMP:
 136    case PIPE_CAP_QUERY_TIME_ELAPSED:
 137    case PIPE_CAP_OCCLUSION_QUERY:
 138       return 1;
 139    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 140       return 4;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 142    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 143       return 64;
 144    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 145    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 146       return 1024;
 147    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 148       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 149    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 150    case PIPE_CAP_INDEP_BLEND_ENABLE:
 151       return 1;
 152    case PIPE_CAP_INDEP_BLEND_FUNC:
 153       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 154    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 155    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 156       return 1;
 157    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 158    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 159       return 0;
 160    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 161       return 0;
 162    case PIPE_CAP_PRIMITIVE_RESTART:
 163    case PIPE_CAP_TGSI_INSTANCEID:
 164    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 165    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 166    case PIPE_CAP_CONDITIONAL_RENDER:
 167    case PIPE_CAP_TEXTURE_BARRIER:
 168    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 169    case PIPE_CAP_START_INSTANCE:
 170       return 1;
 171    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 172       return 0; /* state trackers will know better */
 173    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 174    case PIPE_CAP_USER_INDEX_BUFFERS:
 175    case PIPE_CAP_USER_VERTEX_BUFFERS:
 176       return 1;
 177    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 178       return 256;
 179    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 180       return 1; /* 256 for binding as RT, but that's not possible in GL */
 181    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 182       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 183    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 184    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 185    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 186    case PIPE_CAP_TGSI_TEXCOORD:
 187       return 0;
 188    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 189       return 1;
 190    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 191       return 1;
 192    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 193       return 0;
 194    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 195       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 196    case PIPE_CAP_ENDIANNESS:
 197       return PIPE_ENDIAN_LITTLE;
 198    case PIPE_CAP_TGSI_VS_LAYER:
 199       return 0;
 200    default:
 201       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 202       return 0;
 203    }
 204 }
 205
 206 static int
 207 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 208                              enum pipe_shader_cap param)
 209 {
 210    switch (shader) {
 211    case PIPE_SHADER_VERTEX:
 212    case PIPE_SHADER_GEOMETRY:
 213    case PIPE_SHADER_FRAGMENT:
 214       break;
 215    default:
 216       return 0;
 217    }
 218
 219    switch (param) {
 220    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 221    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 222    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 223    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 224       return 16384;
 225    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 226       return 4;
 227    case PIPE_SHADER_CAP_MAX_INPUTS:
 228       if (shader == PIPE_SHADER_VERTEX)
 229          return 32;
 230       return 15;
 231    case PIPE_SHADER_CAP_MAX_CONSTS:
 232       return 65536 / 16;
 233    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 234       return NV50_MAX_PIPE_CONSTBUFS;
 235    case PIPE_SHADER_CAP_MAX_ADDRS:
 236       return 1;
 237    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 238    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 239       return shader != PIPE_SHADER_FRAGMENT;
 240    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 241    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 242       return 1;
 243    case PIPE_SHADER_CAP_MAX_PREDS:
 244       return 0;
 245    case PIPE_SHADER_CAP_MAX_TEMPS:
 246       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 247    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 248       return 1;
 249    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 250       return 0;
 251    case PIPE_SHADER_CAP_SUBROUTINES:
 252       return 0; /* please inline, or provide function declarations */
 253    case PIPE_SHADER_CAP_INTEGERS:
 254       return 1;
 255    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 256       /* The chip could handle more sampler views than samplers */
 257    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 258       return MIN2(32, PIPE_MAX_SAMPLERS);
 259    default:
 260       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 261       return 0;
 262    }
 263 }
 264
 265 static float
 266 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 267 {
 268    switch (param) {
 269    case PIPE_CAPF_MAX_LINE_WIDTH:
 270    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 271       return 10.0f;
 272    case PIPE_CAPF_MAX_POINT_WIDTH:
 273    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 274       return 64.0f;
 275    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 276       return 16.0f;
 277    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 278       return 4.0f;
 279    default:
 280       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 281       return 0.0f;
 282    }
 283 }
 284
 285 static void
 286 nv50_screen_destroy(struct pipe_screen *pscreen)
 287 {
 288    struct nv50_screen *screen = nv50_screen(pscreen);
 289
 290    if (!nouveau_drm_screen_unref(&screen->base))
 291       return;
 292
 293    if (screen->base.fence.current) {
 294       nouveau_fence_wait(screen->base.fence.current);
 295       nouveau_fence_ref (NULL, &screen->base.fence.current);
 296    }
 297    if (screen->base.pushbuf)
 298       screen->base.pushbuf->user_priv = NULL;
 299
 300    if (screen->blitter)
 301       nv50_blitter_destroy(screen);
 302
 303    nouveau_bo_ref(NULL, &screen->code);
 304    nouveau_bo_ref(NULL, &screen->tls_bo);
 305    nouveau_bo_ref(NULL, &screen->stack_bo);
 306    nouveau_bo_ref(NULL, &screen->txc);
 307    nouveau_bo_ref(NULL, &screen->uniforms);
 308    nouveau_bo_ref(NULL, &screen->fence.bo);
 309
 310    nouveau_heap_destroy(&screen->vp_code_heap);
 311    nouveau_heap_destroy(&screen->gp_code_heap);
 312    nouveau_heap_destroy(&screen->fp_code_heap);
 313
 314    FREE(screen->tic.entries);
 315
 316    nouveau_object_del(&screen->tesla);
 317    nouveau_object_del(&screen->eng2d);
 318    nouveau_object_del(&screen->m2mf);
 319    nouveau_object_del(&screen->sync);
 320
 321    nouveau_screen_fini(&screen->base);
 322
 323    FREE(screen);
 324 }
 325
 326 static void
 327 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 328 {
 329    struct nv50_screen *screen = nv50_screen(pscreen);
 330    struct nouveau_pushbuf *push = screen->base.pushbuf;
 331
 332    /* we need to do it after possible flush in MARK_RING */
 333    *sequence = ++screen->base.fence.sequence;
 334
 335    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 336    PUSH_DATAh(push, screen->fence.bo->offset);
 337    PUSH_DATA (push, screen->fence.bo->offset);
 338    PUSH_DATA (push, *sequence);
 339    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 340                     NV50_3D_QUERY_GET_UNK4 |
 341                     NV50_3D_QUERY_GET_UNIT_CROP |
 342                     NV50_3D_QUERY_GET_TYPE_QUERY |
 343                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 344                     NV50_3D_QUERY_GET_SHORT);
 345 }
 346
 347 static u32
 348 nv50_screen_fence_update(struct pipe_screen *pscreen)
 349 {
 350    return nv50_screen(pscreen)->fence.map[0];
 351 }
 352
 353 static void
 354 nv50_screen_init_hwctx(struct nv50_screen *screen)
 355 {
 356    struct nouveau_pushbuf *push = screen->base.pushbuf;
 357    struct nv04_fifo *fifo;
 358    unsigned i;
 359
 360    fifo = (struct nv04_fifo *)screen->base.channel->data;
 361
 362    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 363    PUSH_DATA (push, screen->m2mf->handle);
 364    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 365    PUSH_DATA (push, screen->sync->handle);
 366    PUSH_DATA (push, fifo->vram);
 367    PUSH_DATA (push, fifo->vram);
 368
 369    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 370    PUSH_DATA (push, screen->eng2d->handle);
 371    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 372    PUSH_DATA (push, screen->sync->handle);
 373    PUSH_DATA (push, fifo->vram);
 374    PUSH_DATA (push, fifo->vram);
 375    PUSH_DATA (push, fifo->vram);
 376    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 377    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 378    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 379    PUSH_DATA (push, 0);
 380    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 381    PUSH_DATA (push, 0);
 382    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 383    PUSH_DATA (push, 1);
 384
 385    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 386    PUSH_DATA (push, screen->tesla->handle);
 387
 388    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 389    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 390
 391    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 392    PUSH_DATA (push, screen->sync->handle);
 393    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 394    for (i = 0; i < 11; ++i)
 395       PUSH_DATA(push, fifo->vram);
 396    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 397    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 398       PUSH_DATA(push, fifo->vram);
 399
 400    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 401    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 402    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 403    PUSH_DATA (push, 0xf);
 404
 405    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 406       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 407       PUSH_DATA (push, 0x18);
 408    }
 409
 410    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 411    PUSH_DATA (push, 1);
 412
 413    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 414    PUSH_DATA (push, 0);
 415    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 416    PUSH_DATA (push, 0);
 417    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 418    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 419    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 420    PUSH_DATA (push, 0);
 421    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 422    PUSH_DATA (push, 0);
 423    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 424    PUSH_DATA (push, 1);
 425
 426    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 427       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 428       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 429    }
 430
 431    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 432    PUSH_DATA (push, 0);
 433    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 434    PUSH_DATA (push, 0);
 435    PUSH_DATA (push, 0);
 436    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 437    PUSH_DATA (push, 0x3f);
 438
 439    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 440    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 441    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 442
 443    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 444    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 445    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 446
 447    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 448    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 449    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 450
 451    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 452    PUSH_DATAh(push, screen->tls_bo->offset);
 453    PUSH_DATA (push, screen->tls_bo->offset);
 454    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 455
 456    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 457    PUSH_DATAh(push, screen->stack_bo->offset);
 458    PUSH_DATA (push, screen->stack_bo->offset);
 459    PUSH_DATA (push, 4);
 460
 461    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 462    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 463    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 464    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 465
 466    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 467    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 468    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 469    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 470
 471    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 472    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 473    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 474    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 475
 476    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 477    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 478    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 479    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 480
 481    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 482    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 483    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 484    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 485
 486    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 487    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 488    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 489    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 490    PUSH_DATAf(push, 0.0f);
 491    PUSH_DATAf(push, 0.0f);
 492    PUSH_DATAf(push, 0.0f);
 493    PUSH_DATAf(push, 0.0f);
 494    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 495    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 496    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 497
 498    nv50_upload_ms_info(push);
 499
 500    /* max TIC (bits 4:8) & TSC bindings, per program type */
 501    for (i = 0; i < 3; ++i) {
 502       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 503       PUSH_DATA (push, 0x54);
 504    }
 505
 506    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 507    PUSH_DATAh(push, screen->txc->offset);
 508    PUSH_DATA (push, screen->txc->offset);
 509    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 510
 511    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 512    PUSH_DATAh(push, screen->txc->offset + 65536);
 513    PUSH_DATA (push, screen->txc->offset + 65536);
 514    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 515
 516    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 517    PUSH_DATA (push, 0);
 518
 519    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 520    PUSH_DATA (push, 0);
 521    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 522    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 523    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 524    for (i = 0; i < 8 * 2; ++i)
 525       PUSH_DATA(push, 0);
 526    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 527    PUSH_DATA (push, 0);
 528
 529    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 530    PUSH_DATA (push, 1);
 531    BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
 532    PUSH_DATAf(push, 0.0f);
 533    PUSH_DATAf(push, 1.0f);
 534
 535    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 536 #ifdef NV50_SCISSORS_CLIPPING
 537    PUSH_DATA (push, 0x0000);
 538 #else
 539    PUSH_DATA (push, 0x1080);
 540 #endif
 541
 542    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 543    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 544
 545    /* We use scissors instead of exact view volume clipping,
 546     * so they're always enabled.
 547     */
 548    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
 549    PUSH_DATA (push, 1);
 550    PUSH_DATA (push, 8192 << 16);
 551    PUSH_DATA (push, 8192 << 16);
 552
 553    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 554    PUSH_DATA (push, 1);
 555    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 556    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 557    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 558    PUSH_DATA (push, 0x11111111);
 559    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 560    PUSH_DATA (push, 1);
 561
 562    PUSH_KICK (push);
 563 }
 564
 565 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 566       uint64_t *tls_size)
 567 {
 568    struct nouveau_device *dev = screen->base.device;
 569    int ret;
 570
 571    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 572          ONE_TEMP_SIZE;
 573    if (nouveau_mesa_debug)
 574       debug_printf("allocating space for %u temps\n",
 575             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 576    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 577          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 578
 579    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 580                         *tls_size, NULL, &screen->tls_bo);
 581    if (ret) {
 582       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 583       return ret;
 584    }
 585
 586    return 0;
 587 }
 588
 589 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 590 {
 591    struct nouveau_pushbuf *push = screen->base.pushbuf;
 592    int ret;
 593    uint64_t tls_size;
 594
 595    if (tls_space < screen->cur_tls_space)
 596       return 0;
 597    if (tls_space > screen->max_tls_space) {
 598       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 599        * LOCAL_WARPS_NO_CLAMP) */
 600       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 601             (unsigned)(tls_space / ONE_TEMP_SIZE),
 602             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 603       return -ENOMEM;
 604    }
 605
 606    nouveau_bo_ref(NULL, &screen->tls_bo);
 607    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 608    if (ret)
 609       return ret;
 610
 611    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 612    PUSH_DATAh(push, screen->tls_bo->offset);
 613    PUSH_DATA (push, screen->tls_bo->offset);
 614    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 615
 616    return 1;
 617 }
 618
 619 struct pipe_screen *
 620 nv50_screen_create(struct nouveau_device *dev)
 621 {
 622    struct nv50_screen *screen;
 623    struct pipe_screen *pscreen;
 624    struct nouveau_object *chan;
 625    uint64_t value;
 626    uint32_t tesla_class;
 627    unsigned stack_size;
 628    int ret;
 629
 630    screen = CALLOC_STRUCT(nv50_screen);
 631    if (!screen)
 632       return NULL;
 633    pscreen = &screen->base.base;
 634
 635    ret = nouveau_screen_init(&screen->base, dev);
 636    if (ret) {
 637       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 638       goto fail;
 639    }
 640
 641    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 642     *  admit them to VRAM.
 643     */
 644    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 645       PIPE_BIND_VERTEX_BUFFER;
 646    screen->base.sysmem_bindings |=
 647       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 648
 649    screen->base.pushbuf->user_priv = screen;
 650    screen->base.pushbuf->rsvd_kick = 5;
 651
 652    chan = screen->base.channel;
 653
 654    pscreen->destroy = nv50_screen_destroy;
 655    pscreen->context_create = nv50_create;
 656    pscreen->is_format_supported = nv50_screen_is_format_supported;
 657    pscreen->get_param = nv50_screen_get_param;
 658    pscreen->get_shader_param = nv50_screen_get_shader_param;
 659    pscreen->get_paramf = nv50_screen_get_paramf;
 660
 661    nv50_screen_init_resource_functions(pscreen);
 662
 663    if (screen->base.device->chipset < 0x84 ||
 664        debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
 665       /* PMPEG */
 666       nouveau_screen_init_vdec(&screen->base);
 667    } else if (screen->base.device->chipset < 0x98 ||
 668               screen->base.device->chipset == 0xa0) {
 669       /* VP2 */
 670       screen->base.base.get_video_param = nv84_screen_get_video_param;
 671       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 672    } else {
 673       /* VP3/4 */
 674       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 675       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 676    }
 677
 678    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 679                         NULL, &screen->fence.bo);
 680    if (ret) {
 681       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 682       goto fail;
 683    }
 684
 685    nouveau_bo_map(screen->fence.bo, 0, NULL);
 686    screen->fence.map = screen->fence.bo->map;
 687    screen->base.fence.emit = nv50_screen_fence_emit;
 688    screen->base.fence.update = nv50_screen_fence_update;
 689
 690    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 691                             &(struct nv04_notify){ .length = 32 },
 692                             sizeof(struct nv04_notify), &screen->sync);
 693    if (ret) {
 694       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 695       goto fail;
 696    }
 697
 698    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 699                             NULL, 0, &screen->m2mf);
 700    if (ret) {
 701       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 702       goto fail;
 703    }
 704
 705    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 706                             NULL, 0, &screen->eng2d);
 707    if (ret) {
 708       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 709       goto fail;
 710    }
 711
 712    switch (dev->chipset & 0xf0) {
 713    case 0x50:
 714       tesla_class = NV50_3D_CLASS;
 715       break;
 716    case 0x80:
 717    case 0x90:
 718       tesla_class = NV84_3D_CLASS;
 719       break;
 720    case 0xa0:
 721       switch (dev->chipset) {
 722       case 0xa0:
 723       case 0xaa:
 724       case 0xac:
 725          tesla_class = NVA0_3D_CLASS;
 726          break;
 727       case 0xaf:
 728          tesla_class = NVAF_3D_CLASS;
 729          break;
 730       default:
 731          tesla_class = NVA3_3D_CLASS;
 732          break;
 733       }
 734       break;
 735    default:
 736       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 737       goto fail;
 738    }
 739    screen->base.class_3d = tesla_class;
 740
 741    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 742                             NULL, 0, &screen->tesla);
 743    if (ret) {
 744       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 745       goto fail;
 746    }
 747
 748    /* This over-allocates by a page. The GP, which would execute at the end of
 749     * the last page, would trigger faults. The going theory is that it
 750     * prefetches up to a certain amount.
 751     */
 752    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 753                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 754                         NULL, &screen->code);
 755    if (ret) {
 756       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 757       goto fail;
 758    }
 759
 760    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 761    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 762    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 763
 764    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 765
 766    screen->TPs = util_bitcount(value & 0xffff);
 767    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 768
 769    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 770          STACK_WARPS_ALLOC * 64 * 8;
 771
 772    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 773                         &screen->stack_bo);
 774    if (ret) {
 775       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 776       goto fail;
 777    }
 778
 779    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 780          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 781          ONE_TEMP_SIZE;
 782    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 783    screen->max_tls_space /= 2; /* half of vram */
 784
 785    /* hw can address max 64 KiB */
 786    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 787
 788    uint64_t tls_size;
 789    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 790    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 791    if (ret)
 792       goto fail;
 793
 794    if (nouveau_mesa_debug)
 795       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 796             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 797
 798    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 799                         &screen->uniforms);
 800    if (ret) {
 801       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 802       goto fail;
 803    }
 804
 805    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 806                         &screen->txc);
 807    if (ret) {
 808       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 809       goto fail;
 810    }
 811
 812    screen->tic.entries = CALLOC(4096, sizeof(void *));
 813    screen->tsc.entries = screen->tic.entries + 2048;
 814
 815    if (!nv50_blitter_create(screen))
 816       goto fail;
 817
 818    nv50_screen_init_hwctx(screen);
 819
 820    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 821
 822    return pscreen;
 823
 824 fail:
 825    nv50_screen_destroy(pscreen);
 826    return NULL;
 827 }
 828
 829 int
 830 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 831 {
 832    int i = screen->tic.next;
 833
 834    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 835       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 836
 837    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 838
 839    if (screen->tic.entries[i])
 840       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 841
 842    screen->tic.entries[i] = entry;
 843    return i;
 844 }
 845
 846 int
 847 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 848 {
 849    int i = screen->tsc.next;
 850
 851    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 852       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 853
 854    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 855
 856    if (screen->tsc.entries[i])
 857       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 858
 859    screen->tsc.entries[i] = entry;
 860    return i;
 861 }