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[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "nv50/nv50_context.h"
28 #include "nv50/nv50_screen.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nv_object.xml.h"
33 #include <errno.h>
34
35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
37 #endif
38
39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
40 #define LOCAL_WARPS_ALLOC 32
41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
42 #define STACK_WARPS_ALLOC 32
43
44 #define THREADS_IN_WARP 32
45
46 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
47
48 static boolean
49 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
50 enum pipe_format format,
51 enum pipe_texture_target target,
52 unsigned sample_count,
53 unsigned bindings)
54 {
55 if (sample_count > 8)
56 return FALSE;
57 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
58 return FALSE;
59 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
60 return FALSE;
61
62 if (!util_format_is_supported(format, bindings))
63 return FALSE;
64
65 switch (format) {
66 case PIPE_FORMAT_Z16_UNORM:
67 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
68 return FALSE;
69 break;
70 default:
71 break;
72 }
73
74 /* transfers & shared are always supported */
75 bindings &= ~(PIPE_BIND_TRANSFER_READ |
76 PIPE_BIND_TRANSFER_WRITE |
77 PIPE_BIND_SHARED);
78
79 return (nv50_format_table[format].usage & bindings) == bindings;
80 }
81
82 static int
83 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
84 {
85 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
86
87 switch (param) {
88 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
89 return 14;
90 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
91 return 12;
92 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
93 return 14;
94 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
95 return 512;
96 case PIPE_CAP_MIN_TEXEL_OFFSET:
97 return -8;
98 case PIPE_CAP_MAX_TEXEL_OFFSET:
99 return 7;
100 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
101 case PIPE_CAP_TEXTURE_SWIZZLE:
102 case PIPE_CAP_TEXTURE_SHADOW_MAP:
103 case PIPE_CAP_NPOT_TEXTURES:
104 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
105 case PIPE_CAP_ANISOTROPIC_FILTER:
106 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
107 return 1;
108 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
109 return 65536;
110 case PIPE_CAP_SEAMLESS_CUBE_MAP:
111 return 1; /* nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS; */
112 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
113 return 0;
114 case PIPE_CAP_CUBE_MAP_ARRAY:
115 return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
116 case PIPE_CAP_TWO_SIDED_STENCIL:
117 case PIPE_CAP_DEPTH_CLIP_DISABLE:
118 case PIPE_CAP_POINT_SPRITE:
119 return 1;
120 case PIPE_CAP_SM3:
121 return 1;
122 case PIPE_CAP_GLSL_FEATURE_LEVEL:
123 return 330;
124 case PIPE_CAP_MAX_RENDER_TARGETS:
125 return 8;
126 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
127 return 1;
128 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
129 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
130 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
131 return 1;
132 case PIPE_CAP_QUERY_TIMESTAMP:
133 case PIPE_CAP_QUERY_TIME_ELAPSED:
134 case PIPE_CAP_OCCLUSION_QUERY:
135 return 1;
136 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
137 return 4;
138 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
139 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
140 return 64;
141 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
142 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
143 return 1024;
144 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
145 return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
146 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
147 case PIPE_CAP_INDEP_BLEND_ENABLE:
148 return 1;
149 case PIPE_CAP_INDEP_BLEND_FUNC:
150 return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
151 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
152 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
153 return 1;
154 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
155 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
156 return 0;
157 case PIPE_CAP_SHADER_STENCIL_EXPORT:
158 return 0;
159 case PIPE_CAP_PRIMITIVE_RESTART:
160 case PIPE_CAP_TGSI_INSTANCEID:
161 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
162 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
163 case PIPE_CAP_CONDITIONAL_RENDER:
164 case PIPE_CAP_TEXTURE_BARRIER:
165 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
166 case PIPE_CAP_START_INSTANCE:
167 return 1;
168 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
169 return 0; /* state trackers will know better */
170 case PIPE_CAP_USER_CONSTANT_BUFFERS:
171 case PIPE_CAP_USER_INDEX_BUFFERS:
172 case PIPE_CAP_USER_VERTEX_BUFFERS:
173 return 1;
174 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
175 return 256;
176 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
177 return 1; /* 256 for binding as RT, but that's not possible in GL */
178 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
179 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
180 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
181 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
182 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
183 case PIPE_CAP_TGSI_TEXCOORD:
184 return 0;
185 case PIPE_CAP_TEXTURE_MULTISAMPLE:
186 return 1;
187 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
188 return 1;
189 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
190 return 0;
191 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
192 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
193 case PIPE_CAP_ENDIANNESS:
194 return PIPE_ENDIAN_LITTLE;
195 case PIPE_CAP_TGSI_VS_LAYER:
196 case PIPE_CAP_TEXTURE_GATHER_SM5:
197 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
198 case PIPE_CAP_FAKE_SW_MSAA:
199 return 0;
200 case PIPE_CAP_MAX_VIEWPORTS:
201 return NV50_MAX_VIEWPORTS;
202 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
203 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
204 default:
205 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
206 return 0;
207 }
208 }
209
210 static int
211 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
212 enum pipe_shader_cap param)
213 {
214 switch (shader) {
215 case PIPE_SHADER_VERTEX:
216 case PIPE_SHADER_GEOMETRY:
217 case PIPE_SHADER_FRAGMENT:
218 break;
219 default:
220 return 0;
221 }
222
223 switch (param) {
224 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
225 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
226 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
227 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
228 return 16384;
229 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
230 return 4;
231 case PIPE_SHADER_CAP_MAX_INPUTS:
232 if (shader == PIPE_SHADER_VERTEX)
233 return 32;
234 return 15;
235 case PIPE_SHADER_CAP_MAX_CONSTS:
236 return 65536 / 16;
237 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
238 return NV50_MAX_PIPE_CONSTBUFS;
239 case PIPE_SHADER_CAP_MAX_ADDRS:
240 return 1;
241 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
242 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
243 return shader != PIPE_SHADER_FRAGMENT;
244 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
245 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
246 return 1;
247 case PIPE_SHADER_CAP_MAX_PREDS:
248 return 0;
249 case PIPE_SHADER_CAP_MAX_TEMPS:
250 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
251 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
252 return 1;
253 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
254 return 0;
255 case PIPE_SHADER_CAP_SUBROUTINES:
256 return 0; /* please inline, or provide function declarations */
257 case PIPE_SHADER_CAP_INTEGERS:
258 return 1;
259 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
260 /* The chip could handle more sampler views than samplers */
261 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
262 return MIN2(32, PIPE_MAX_SAMPLERS);
263 default:
264 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
265 return 0;
266 }
267 }
268
269 static float
270 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
271 {
272 switch (param) {
273 case PIPE_CAPF_MAX_LINE_WIDTH:
274 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
275 return 10.0f;
276 case PIPE_CAPF_MAX_POINT_WIDTH:
277 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
278 return 64.0f;
279 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
280 return 16.0f;
281 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
282 return 4.0f;
283 default:
284 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
285 return 0.0f;
286 }
287 }
288
289 static void
290 nv50_screen_destroy(struct pipe_screen *pscreen)
291 {
292 struct nv50_screen *screen = nv50_screen(pscreen);
293
294 if (!nouveau_drm_screen_unref(&screen->base))
295 return;
296
297 if (screen->base.fence.current) {
298 struct nouveau_fence *current = NULL;
299
300 /* nouveau_fence_wait will create a new current fence, so wait on the
301 * _current_ one, and remove both.
302 */
303 nouveau_fence_ref(screen->base.fence.current, &current);
304 nouveau_fence_wait(current);
305 nouveau_fence_ref(NULL, &current);
306 nouveau_fence_ref(NULL, &screen->base.fence.current);
307 }
308 if (screen->base.pushbuf)
309 screen->base.pushbuf->user_priv = NULL;
310
311 if (screen->blitter)
312 nv50_blitter_destroy(screen);
313
314 nouveau_bo_ref(NULL, &screen->code);
315 nouveau_bo_ref(NULL, &screen->tls_bo);
316 nouveau_bo_ref(NULL, &screen->stack_bo);
317 nouveau_bo_ref(NULL, &screen->txc);
318 nouveau_bo_ref(NULL, &screen->uniforms);
319 nouveau_bo_ref(NULL, &screen->fence.bo);
320
321 nouveau_heap_destroy(&screen->vp_code_heap);
322 nouveau_heap_destroy(&screen->gp_code_heap);
323 nouveau_heap_destroy(&screen->fp_code_heap);
324
325 FREE(screen->tic.entries);
326
327 nouveau_object_del(&screen->tesla);
328 nouveau_object_del(&screen->eng2d);
329 nouveau_object_del(&screen->m2mf);
330 nouveau_object_del(&screen->sync);
331
332 nouveau_screen_fini(&screen->base);
333
334 FREE(screen);
335 }
336
337 static void
338 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
339 {
340 struct nv50_screen *screen = nv50_screen(pscreen);
341 struct nouveau_pushbuf *push = screen->base.pushbuf;
342
343 /* we need to do it after possible flush in MARK_RING */
344 *sequence = ++screen->base.fence.sequence;
345
346 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
347 PUSH_DATAh(push, screen->fence.bo->offset);
348 PUSH_DATA (push, screen->fence.bo->offset);
349 PUSH_DATA (push, *sequence);
350 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
351 NV50_3D_QUERY_GET_UNK4 |
352 NV50_3D_QUERY_GET_UNIT_CROP |
353 NV50_3D_QUERY_GET_TYPE_QUERY |
354 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
355 NV50_3D_QUERY_GET_SHORT);
356 }
357
358 static u32
359 nv50_screen_fence_update(struct pipe_screen *pscreen)
360 {
361 return nv50_screen(pscreen)->fence.map[0];
362 }
363
364 static void
365 nv50_screen_init_hwctx(struct nv50_screen *screen)
366 {
367 struct nouveau_pushbuf *push = screen->base.pushbuf;
368 struct nv04_fifo *fifo;
369 unsigned i;
370
371 fifo = (struct nv04_fifo *)screen->base.channel->data;
372
373 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
374 PUSH_DATA (push, screen->m2mf->handle);
375 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
376 PUSH_DATA (push, screen->sync->handle);
377 PUSH_DATA (push, fifo->vram);
378 PUSH_DATA (push, fifo->vram);
379
380 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
381 PUSH_DATA (push, screen->eng2d->handle);
382 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
383 PUSH_DATA (push, screen->sync->handle);
384 PUSH_DATA (push, fifo->vram);
385 PUSH_DATA (push, fifo->vram);
386 PUSH_DATA (push, fifo->vram);
387 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
388 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
389 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
390 PUSH_DATA (push, 0);
391 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
392 PUSH_DATA (push, 0);
393 BEGIN_NV04(push, SUBC_2D(0x0888), 1);
394 PUSH_DATA (push, 1);
395
396 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
397 PUSH_DATA (push, screen->tesla->handle);
398
399 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
400 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
401
402 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
403 PUSH_DATA (push, screen->sync->handle);
404 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
405 for (i = 0; i < 11; ++i)
406 PUSH_DATA(push, fifo->vram);
407 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
408 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
409 PUSH_DATA(push, fifo->vram);
410
411 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
412 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
413 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
414 PUSH_DATA (push, 0xf);
415
416 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
417 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
418 PUSH_DATA (push, 0x18);
419 }
420
421 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
422 PUSH_DATA (push, 1);
423
424 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
425 PUSH_DATA (push, 0);
426 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
427 PUSH_DATA (push, 0);
428 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
429 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
430 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
431 PUSH_DATA (push, 0);
432 BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
433 PUSH_DATA (push, 0);
434 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
435 PUSH_DATA (push, 1);
436
437 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
438 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
439 PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
440 }
441
442 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
443 PUSH_DATA (push, 0);
444 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
445 PUSH_DATA (push, 0);
446 PUSH_DATA (push, 0);
447 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
448 PUSH_DATA (push, 0x3f);
449
450 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
451 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
452 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
453
454 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
455 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
456 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
457
458 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
459 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
460 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
461
462 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
463 PUSH_DATAh(push, screen->tls_bo->offset);
464 PUSH_DATA (push, screen->tls_bo->offset);
465 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
466
467 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
468 PUSH_DATAh(push, screen->stack_bo->offset);
469 PUSH_DATA (push, screen->stack_bo->offset);
470 PUSH_DATA (push, 4);
471
472 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
473 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
474 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
475 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
476
477 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
478 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
479 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
480 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
481
482 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
483 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
484 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
485 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
486
487 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
488 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
489 PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
490 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
491
492 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
493 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
494 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
495 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
496
497 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
498 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
499 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
500 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
501 PUSH_DATAf(push, 0.0f);
502 PUSH_DATAf(push, 0.0f);
503 PUSH_DATAf(push, 0.0f);
504 PUSH_DATAf(push, 0.0f);
505 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
506 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
507 PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
508
509 nv50_upload_ms_info(push);
510
511 /* max TIC (bits 4:8) & TSC bindings, per program type */
512 for (i = 0; i < 3; ++i) {
513 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
514 PUSH_DATA (push, 0x54);
515 }
516
517 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
518 PUSH_DATAh(push, screen->txc->offset);
519 PUSH_DATA (push, screen->txc->offset);
520 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
521
522 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
523 PUSH_DATAh(push, screen->txc->offset + 65536);
524 PUSH_DATA (push, screen->txc->offset + 65536);
525 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
526
527 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
528 PUSH_DATA (push, 0);
529
530 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
531 PUSH_DATA (push, 0);
532 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
533 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
534 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
535 for (i = 0; i < 8 * 2; ++i)
536 PUSH_DATA(push, 0);
537 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
538 PUSH_DATA (push, 0);
539
540 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
541 PUSH_DATA (push, 1);
542 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
543 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
544 PUSH_DATAf(push, 0.0f);
545 PUSH_DATAf(push, 1.0f);
546 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
547 PUSH_DATA (push, 8192 << 16);
548 PUSH_DATA (push, 8192 << 16);
549 }
550
551 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
552 #ifdef NV50_SCISSORS_CLIPPING
553 PUSH_DATA (push, 0x0000);
554 #else
555 PUSH_DATA (push, 0x1080);
556 #endif
557
558 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
559 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
560
561 /* We use scissors instead of exact view volume clipping,
562 * so they're always enabled.
563 */
564 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
565 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
566 PUSH_DATA (push, 1);
567 PUSH_DATA (push, 8192 << 16);
568 PUSH_DATA (push, 8192 << 16);
569 }
570
571 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
572 PUSH_DATA (push, 1);
573 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
574 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
575 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
576 PUSH_DATA (push, 0x11111111);
577 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
578 PUSH_DATA (push, 1);
579
580 PUSH_KICK (push);
581 }
582
583 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
584 uint64_t *tls_size)
585 {
586 struct nouveau_device *dev = screen->base.device;
587 int ret;
588
589 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
590 ONE_TEMP_SIZE;
591 if (nouveau_mesa_debug)
592 debug_printf("allocating space for %u temps\n",
593 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
594 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
595 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
596
597 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
598 *tls_size, NULL, &screen->tls_bo);
599 if (ret) {
600 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
601 return ret;
602 }
603
604 return 0;
605 }
606
607 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
608 {
609 struct nouveau_pushbuf *push = screen->base.pushbuf;
610 int ret;
611 uint64_t tls_size;
612
613 if (tls_space < screen->cur_tls_space)
614 return 0;
615 if (tls_space > screen->max_tls_space) {
616 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
617 * LOCAL_WARPS_NO_CLAMP) */
618 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
619 (unsigned)(tls_space / ONE_TEMP_SIZE),
620 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
621 return -ENOMEM;
622 }
623
624 nouveau_bo_ref(NULL, &screen->tls_bo);
625 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
626 if (ret)
627 return ret;
628
629 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
630 PUSH_DATAh(push, screen->tls_bo->offset);
631 PUSH_DATA (push, screen->tls_bo->offset);
632 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
633
634 return 1;
635 }
636
637 struct pipe_screen *
638 nv50_screen_create(struct nouveau_device *dev)
639 {
640 struct nv50_screen *screen;
641 struct pipe_screen *pscreen;
642 struct nouveau_object *chan;
643 uint64_t value;
644 uint32_t tesla_class;
645 unsigned stack_size;
646 int ret;
647
648 screen = CALLOC_STRUCT(nv50_screen);
649 if (!screen)
650 return NULL;
651 pscreen = &screen->base.base;
652
653 ret = nouveau_screen_init(&screen->base, dev);
654 if (ret) {
655 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
656 goto fail;
657 }
658
659 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
660 * admit them to VRAM.
661 */
662 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
663 PIPE_BIND_VERTEX_BUFFER;
664 screen->base.sysmem_bindings |=
665 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
666
667 screen->base.pushbuf->user_priv = screen;
668 screen->base.pushbuf->rsvd_kick = 5;
669
670 chan = screen->base.channel;
671
672 pscreen->destroy = nv50_screen_destroy;
673 pscreen->context_create = nv50_create;
674 pscreen->is_format_supported = nv50_screen_is_format_supported;
675 pscreen->get_param = nv50_screen_get_param;
676 pscreen->get_shader_param = nv50_screen_get_shader_param;
677 pscreen->get_paramf = nv50_screen_get_paramf;
678
679 nv50_screen_init_resource_functions(pscreen);
680
681 if (screen->base.device->chipset < 0x84 ||
682 debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
683 /* PMPEG */
684 nouveau_screen_init_vdec(&screen->base);
685 } else if (screen->base.device->chipset < 0x98 ||
686 screen->base.device->chipset == 0xa0) {
687 /* VP2 */
688 screen->base.base.get_video_param = nv84_screen_get_video_param;
689 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
690 } else {
691 /* VP3/4 */
692 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
693 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
694 }
695
696 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
697 NULL, &screen->fence.bo);
698 if (ret) {
699 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
700 goto fail;
701 }
702
703 nouveau_bo_map(screen->fence.bo, 0, NULL);
704 screen->fence.map = screen->fence.bo->map;
705 screen->base.fence.emit = nv50_screen_fence_emit;
706 screen->base.fence.update = nv50_screen_fence_update;
707
708 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
709 &(struct nv04_notify){ .length = 32 },
710 sizeof(struct nv04_notify), &screen->sync);
711 if (ret) {
712 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
713 goto fail;
714 }
715
716 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
717 NULL, 0, &screen->m2mf);
718 if (ret) {
719 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
720 goto fail;
721 }
722
723 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
724 NULL, 0, &screen->eng2d);
725 if (ret) {
726 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
727 goto fail;
728 }
729
730 switch (dev->chipset & 0xf0) {
731 case 0x50:
732 tesla_class = NV50_3D_CLASS;
733 break;
734 case 0x80:
735 case 0x90:
736 tesla_class = NV84_3D_CLASS;
737 break;
738 case 0xa0:
739 switch (dev->chipset) {
740 case 0xa0:
741 case 0xaa:
742 case 0xac:
743 tesla_class = NVA0_3D_CLASS;
744 break;
745 case 0xaf:
746 tesla_class = NVAF_3D_CLASS;
747 break;
748 default:
749 tesla_class = NVA3_3D_CLASS;
750 break;
751 }
752 break;
753 default:
754 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
755 goto fail;
756 }
757 screen->base.class_3d = tesla_class;
758
759 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
760 NULL, 0, &screen->tesla);
761 if (ret) {
762 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
763 goto fail;
764 }
765
766 /* This over-allocates by a page. The GP, which would execute at the end of
767 * the last page, would trigger faults. The going theory is that it
768 * prefetches up to a certain amount.
769 */
770 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
771 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
772 NULL, &screen->code);
773 if (ret) {
774 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
775 goto fail;
776 }
777
778 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
779 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
780 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
781
782 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
783
784 screen->TPs = util_bitcount(value & 0xffff);
785 screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
786
787 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
788 STACK_WARPS_ALLOC * 64 * 8;
789
790 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
791 &screen->stack_bo);
792 if (ret) {
793 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
794 goto fail;
795 }
796
797 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
798 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
799 ONE_TEMP_SIZE;
800 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
801 screen->max_tls_space /= 2; /* half of vram */
802
803 /* hw can address max 64 KiB */
804 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
805
806 uint64_t tls_size;
807 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
808 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
809 if (ret)
810 goto fail;
811
812 if (nouveau_mesa_debug)
813 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
814 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
815
816 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
817 &screen->uniforms);
818 if (ret) {
819 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
820 goto fail;
821 }
822
823 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
824 &screen->txc);
825 if (ret) {
826 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
827 goto fail;
828 }
829
830 screen->tic.entries = CALLOC(4096, sizeof(void *));
831 screen->tsc.entries = screen->tic.entries + 2048;
832
833 if (!nv50_blitter_create(screen))
834 goto fail;
835
836 nv50_screen_init_hwctx(screen);
837
838 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
839
840 return pscreen;
841
842 fail:
843 nv50_screen_destroy(pscreen);
844 return NULL;
845 }
846
847 int
848 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
849 {
850 int i = screen->tic.next;
851
852 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
853 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
854
855 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
856
857 if (screen->tic.entries[i])
858 nv50_tic_entry(screen->tic.entries[i])->id = -1;
859
860 screen->tic.entries[i] = entry;
861 return i;
862 }
863
864 int
865 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
866 {
867 int i = screen->tsc.next;
868
869 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
870 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
871
872 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
873
874 if (screen->tsc.entries[i])
875 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
876
877 screen->tsc.entries[i] = entry;
878 return i;
879 }