src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  45
  46 static boolean
  47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  48                                 enum pipe_format format,
  49                                 enum pipe_texture_target target,
  50                                 unsigned sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (sample_count > 8)
  54       return FALSE;
  55    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  56       return FALSE;
  57    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  58       return FALSE;
  59
  60    if (!util_format_is_supported(format, bindings))
  61       return FALSE;
  62
  63    switch (format) {
  64    case PIPE_FORMAT_Z16_UNORM:
  65       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  66          return FALSE;
  67       break;
  68    default:
  69       break;
  70    }
  71
  72    /* transfers & shared are always supported */
  73    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  74                  PIPE_BIND_TRANSFER_WRITE |
  75                  PIPE_BIND_SHARED);
  76
  77    return (nv50_format_table[format].usage & bindings) == bindings;
  78 }
  79
  80 static int
  81 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  82 {
  83    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  84    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  85
  86    switch (param) {
  87    /* non-boolean caps */
  88    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  89       return 14;
  90    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  91       return 12;
  92    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  93       return 14;
  94    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  95       return 512;
  96    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  97    case PIPE_CAP_MIN_TEXEL_OFFSET:
  98       return -8;
  99    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 100    case PIPE_CAP_MAX_TEXEL_OFFSET:
 101       return 7;
 102    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 103       return 65536;
 104    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 105       return 330;
 106    case PIPE_CAP_MAX_RENDER_TARGETS:
 107       return 8;
 108    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 109       return 1;
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 111       return 4;
 112    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 113    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 114       return 64;
 115    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 116    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 117       return 1024;
 118    case PIPE_CAP_MAX_VERTEX_STREAMS:
 119       return 1;
 120    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 121       return 2048;
 122    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 123       return 256;
 124    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 125       return 1; /* 256 for binding as RT, but that's not possible in GL */
 126    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 127       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 128    case PIPE_CAP_MAX_VIEWPORTS:
 129       return NV50_MAX_VIEWPORTS;
 130    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 131       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 132    case PIPE_CAP_ENDIANNESS:
 133       return PIPE_ENDIAN_LITTLE;
 134    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 135       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 136
 137    /* supported caps */
 138    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 139    case PIPE_CAP_TEXTURE_SWIZZLE:
 140    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 141    case PIPE_CAP_NPOT_TEXTURES:
 142    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 143    case PIPE_CAP_ANISOTROPIC_FILTER:
 144    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 145    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 146    case PIPE_CAP_TWO_SIDED_STENCIL:
 147    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 148    case PIPE_CAP_POINT_SPRITE:
 149    case PIPE_CAP_SM3:
 150    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 151    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 152    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 153    case PIPE_CAP_QUERY_TIMESTAMP:
 154    case PIPE_CAP_QUERY_TIME_ELAPSED:
 155    case PIPE_CAP_OCCLUSION_QUERY:
 156    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 157    case PIPE_CAP_INDEP_BLEND_ENABLE:
 158    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 159    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 160    case PIPE_CAP_PRIMITIVE_RESTART:
 161    case PIPE_CAP_TGSI_INSTANCEID:
 162    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 163    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 164    case PIPE_CAP_CONDITIONAL_RENDER:
 165    case PIPE_CAP_TEXTURE_BARRIER:
 166    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 167    case PIPE_CAP_START_INSTANCE:
 168    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 169    case PIPE_CAP_USER_INDEX_BUFFERS:
 170    case PIPE_CAP_USER_VERTEX_BUFFERS:
 171    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 172    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 173    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 174    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 175    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 176    case PIPE_CAP_CLIP_HALFZ:
 177       return 1;
 178    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 179       return 1; /* class_3d >= NVA0_3D_CLASS; */
 180    /* supported on nva0+ */
 181    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 182       return class_3d >= NVA0_3D_CLASS;
 183    /* supported on nva3+ */
 184    case PIPE_CAP_CUBE_MAP_ARRAY:
 185    case PIPE_CAP_INDEP_BLEND_FUNC:
 186    case PIPE_CAP_TEXTURE_QUERY_LOD:
 187    case PIPE_CAP_SAMPLE_SHADING:
 188       return class_3d >= NVA3_3D_CLASS;
 189
 190    /* unsupported caps */
 191    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 192    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 193    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 194    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 195    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 196    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 197    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 198    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 199    case PIPE_CAP_TGSI_TEXCOORD:
 200    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 201    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 202    case PIPE_CAP_TEXTURE_GATHER_SM5:
 203    case PIPE_CAP_FAKE_SW_MSAA:
 204    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 205    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 206    case PIPE_CAP_COMPUTE:
 207    case PIPE_CAP_DRAW_INDIRECT:
 208    case PIPE_CAP_VERTEXID_NOBASE:
 209       return 0;
 210
 211    case PIPE_CAP_VENDOR_ID:
 212       return 0x10de;
 213    case PIPE_CAP_DEVICE_ID: {
 214       uint64_t device_id;
 215       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 216          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 217          return -1;
 218       }
 219       return device_id;
 220    }
 221    case PIPE_CAP_ACCELERATED:
 222       return 1;
 223    case PIPE_CAP_VIDEO_MEMORY:
 224       return dev->vram_size >> 20;
 225    case PIPE_CAP_UMA:
 226       return 0;
 227    }
 228
 229    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 230    return 0;
 231 }
 232
 233 static int
 234 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 235                              enum pipe_shader_cap param)
 236 {
 237    switch (shader) {
 238    case PIPE_SHADER_VERTEX:
 239    case PIPE_SHADER_GEOMETRY:
 240    case PIPE_SHADER_FRAGMENT:
 241       break;
 242    default:
 243       return 0;
 244    }
 245
 246    switch (param) {
 247    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 248    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 249    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 250    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 251       return 16384;
 252    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 253       return 4;
 254    case PIPE_SHADER_CAP_MAX_INPUTS:
 255       if (shader == PIPE_SHADER_VERTEX)
 256          return 32;
 257       return 15;
 258    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 259       return 16;
 260    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 261       return 65536;
 262    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 263       return NV50_MAX_PIPE_CONSTBUFS;
 264    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 265    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 266       return shader != PIPE_SHADER_FRAGMENT;
 267    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 268    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 269       return 1;
 270    case PIPE_SHADER_CAP_MAX_PREDS:
 271       return 0;
 272    case PIPE_SHADER_CAP_MAX_TEMPS:
 273       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 274    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 275       return 1;
 276    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 277       return 0;
 278    case PIPE_SHADER_CAP_SUBROUTINES:
 279       return 0; /* please inline, or provide function declarations */
 280    case PIPE_SHADER_CAP_INTEGERS:
 281       return 1;
 282    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 283       /* The chip could handle more sampler views than samplers */
 284    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 285       return MIN2(32, PIPE_MAX_SAMPLERS);
 286    default:
 287       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 288       return 0;
 289    }
 290 }
 291
 292 static float
 293 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 294 {
 295    switch (param) {
 296    case PIPE_CAPF_MAX_LINE_WIDTH:
 297    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 298       return 10.0f;
 299    case PIPE_CAPF_MAX_POINT_WIDTH:
 300    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 301       return 64.0f;
 302    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 303       return 16.0f;
 304    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 305       return 4.0f;
 306    case PIPE_CAPF_GUARD_BAND_LEFT:
 307    case PIPE_CAPF_GUARD_BAND_TOP:
 308       return 0.0f;
 309    case PIPE_CAPF_GUARD_BAND_RIGHT:
 310    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 311       return 0.0f; /* that or infinity */
 312    }
 313
 314    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 315    return 0.0f;
 316 }
 317
 318 static void
 319 nv50_screen_destroy(struct pipe_screen *pscreen)
 320 {
 321    struct nv50_screen *screen = nv50_screen(pscreen);
 322
 323    if (!nouveau_drm_screen_unref(&screen->base))
 324       return;
 325
 326    if (screen->base.fence.current) {
 327       struct nouveau_fence *current = NULL;
 328
 329       /* nouveau_fence_wait will create a new current fence, so wait on the
 330        * _current_ one, and remove both.
 331        */
 332       nouveau_fence_ref(screen->base.fence.current, &current);
 333       nouveau_fence_wait(current);
 334       nouveau_fence_ref(NULL, &current);
 335       nouveau_fence_ref(NULL, &screen->base.fence.current);
 336    }
 337    if (screen->base.pushbuf)
 338       screen->base.pushbuf->user_priv = NULL;
 339
 340    if (screen->blitter)
 341       nv50_blitter_destroy(screen);
 342
 343    nouveau_bo_ref(NULL, &screen->code);
 344    nouveau_bo_ref(NULL, &screen->tls_bo);
 345    nouveau_bo_ref(NULL, &screen->stack_bo);
 346    nouveau_bo_ref(NULL, &screen->txc);
 347    nouveau_bo_ref(NULL, &screen->uniforms);
 348    nouveau_bo_ref(NULL, &screen->fence.bo);
 349
 350    nouveau_heap_destroy(&screen->vp_code_heap);
 351    nouveau_heap_destroy(&screen->gp_code_heap);
 352    nouveau_heap_destroy(&screen->fp_code_heap);
 353
 354    FREE(screen->tic.entries);
 355
 356    nouveau_object_del(&screen->tesla);
 357    nouveau_object_del(&screen->eng2d);
 358    nouveau_object_del(&screen->m2mf);
 359    nouveau_object_del(&screen->sync);
 360
 361    nouveau_screen_fini(&screen->base);
 362
 363    FREE(screen);
 364 }
 365
 366 static void
 367 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 368 {
 369    struct nv50_screen *screen = nv50_screen(pscreen);
 370    struct nouveau_pushbuf *push = screen->base.pushbuf;
 371
 372    /* we need to do it after possible flush in MARK_RING */
 373    *sequence = ++screen->base.fence.sequence;
 374
 375    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 376    PUSH_DATAh(push, screen->fence.bo->offset);
 377    PUSH_DATA (push, screen->fence.bo->offset);
 378    PUSH_DATA (push, *sequence);
 379    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 380                     NV50_3D_QUERY_GET_UNK4 |
 381                     NV50_3D_QUERY_GET_UNIT_CROP |
 382                     NV50_3D_QUERY_GET_TYPE_QUERY |
 383                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 384                     NV50_3D_QUERY_GET_SHORT);
 385 }
 386
 387 static u32
 388 nv50_screen_fence_update(struct pipe_screen *pscreen)
 389 {
 390    return nv50_screen(pscreen)->fence.map[0];
 391 }
 392
 393 static void
 394 nv50_screen_init_hwctx(struct nv50_screen *screen)
 395 {
 396    struct nouveau_pushbuf *push = screen->base.pushbuf;
 397    struct nv04_fifo *fifo;
 398    unsigned i;
 399
 400    fifo = (struct nv04_fifo *)screen->base.channel->data;
 401
 402    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 403    PUSH_DATA (push, screen->m2mf->handle);
 404    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 405    PUSH_DATA (push, screen->sync->handle);
 406    PUSH_DATA (push, fifo->vram);
 407    PUSH_DATA (push, fifo->vram);
 408
 409    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 410    PUSH_DATA (push, screen->eng2d->handle);
 411    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 412    PUSH_DATA (push, screen->sync->handle);
 413    PUSH_DATA (push, fifo->vram);
 414    PUSH_DATA (push, fifo->vram);
 415    PUSH_DATA (push, fifo->vram);
 416    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 417    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 418    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 419    PUSH_DATA (push, 0);
 420    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 421    PUSH_DATA (push, 0);
 422    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 423    PUSH_DATA (push, 1);
 424    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 425    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 426
 427    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 428    PUSH_DATA (push, screen->tesla->handle);
 429
 430    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 431    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 432
 433    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 434    PUSH_DATA (push, screen->sync->handle);
 435    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 436    for (i = 0; i < 11; ++i)
 437       PUSH_DATA(push, fifo->vram);
 438    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 439    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 440       PUSH_DATA(push, fifo->vram);
 441
 442    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 443    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 444    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 445    PUSH_DATA (push, 0xf);
 446
 447    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 448       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 449       PUSH_DATA (push, 0x18);
 450    }
 451
 452    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 453    PUSH_DATA (push, 1);
 454
 455    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 456    PUSH_DATA (push, 0);
 457    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 458    PUSH_DATA (push, 0);
 459    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 460    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 461    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 462    PUSH_DATA (push, 0);
 463    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 464    PUSH_DATA (push, 1);
 465    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 466    PUSH_DATA (push, 1);
 467
 468    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 469       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 470       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 471    }
 472
 473    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 474    PUSH_DATA (push, 0);
 475    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 476    PUSH_DATA (push, 0);
 477    PUSH_DATA (push, 0);
 478    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 479    PUSH_DATA (push, 0x3f);
 480
 481    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 482    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 483    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 484
 485    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 486    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 487    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 488
 489    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 490    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 491    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 492
 493    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 494    PUSH_DATAh(push, screen->tls_bo->offset);
 495    PUSH_DATA (push, screen->tls_bo->offset);
 496    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 497
 498    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 499    PUSH_DATAh(push, screen->stack_bo->offset);
 500    PUSH_DATA (push, screen->stack_bo->offset);
 501    PUSH_DATA (push, 4);
 502
 503    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 504    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 505    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 506    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 507
 508    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 509    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 510    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 511    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 512
 513    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 514    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 515    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 516    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 517
 518    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 519    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 520    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 521    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 522
 523    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 524    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 525    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 526    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 527
 528    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 529    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 530    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 531    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 532    PUSH_DATAf(push, 0.0f);
 533    PUSH_DATAf(push, 0.0f);
 534    PUSH_DATAf(push, 0.0f);
 535    PUSH_DATAf(push, 0.0f);
 536    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 537    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 538    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 539
 540    nv50_upload_ms_info(push);
 541
 542    /* max TIC (bits 4:8) & TSC bindings, per program type */
 543    for (i = 0; i < 3; ++i) {
 544       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 545       PUSH_DATA (push, 0x54);
 546    }
 547
 548    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 549    PUSH_DATAh(push, screen->txc->offset);
 550    PUSH_DATA (push, screen->txc->offset);
 551    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 552
 553    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 554    PUSH_DATAh(push, screen->txc->offset + 65536);
 555    PUSH_DATA (push, screen->txc->offset + 65536);
 556    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 557
 558    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 559    PUSH_DATA (push, 0);
 560
 561    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 562    PUSH_DATA (push, 0);
 563    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 564    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 565    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 566    for (i = 0; i < 8 * 2; ++i)
 567       PUSH_DATA(push, 0);
 568    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 569    PUSH_DATA (push, 0);
 570
 571    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 572    PUSH_DATA (push, 1);
 573    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 574       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 575       PUSH_DATAf(push, 0.0f);
 576       PUSH_DATAf(push, 1.0f);
 577       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 578       PUSH_DATA (push, 8192 << 16);
 579       PUSH_DATA (push, 8192 << 16);
 580    }
 581
 582    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 583 #ifdef NV50_SCISSORS_CLIPPING
 584    PUSH_DATA (push, 0x0000);
 585 #else
 586    PUSH_DATA (push, 0x1080);
 587 #endif
 588
 589    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 590    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 591
 592    /* We use scissors instead of exact view volume clipping,
 593     * so they're always enabled.
 594     */
 595    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 596       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 597       PUSH_DATA (push, 1);
 598       PUSH_DATA (push, 8192 << 16);
 599       PUSH_DATA (push, 8192 << 16);
 600    }
 601
 602    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 603    PUSH_DATA (push, 1);
 604    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 605    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 606    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 607    PUSH_DATA (push, 0x11111111);
 608    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 609    PUSH_DATA (push, 1);
 610
 611    PUSH_KICK (push);
 612 }
 613
 614 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 615       uint64_t *tls_size)
 616 {
 617    struct nouveau_device *dev = screen->base.device;
 618    int ret;
 619
 620    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 621          ONE_TEMP_SIZE;
 622    if (nouveau_mesa_debug)
 623       debug_printf("allocating space for %u temps\n",
 624             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 625    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 626          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 627
 628    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 629                         *tls_size, NULL, &screen->tls_bo);
 630    if (ret) {
 631       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 632       return ret;
 633    }
 634
 635    return 0;
 636 }
 637
 638 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 639 {
 640    struct nouveau_pushbuf *push = screen->base.pushbuf;
 641    int ret;
 642    uint64_t tls_size;
 643
 644    if (tls_space < screen->cur_tls_space)
 645       return 0;
 646    if (tls_space > screen->max_tls_space) {
 647       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 648        * LOCAL_WARPS_NO_CLAMP) */
 649       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 650             (unsigned)(tls_space / ONE_TEMP_SIZE),
 651             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 652       return -ENOMEM;
 653    }
 654
 655    nouveau_bo_ref(NULL, &screen->tls_bo);
 656    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 657    if (ret)
 658       return ret;
 659
 660    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 661    PUSH_DATAh(push, screen->tls_bo->offset);
 662    PUSH_DATA (push, screen->tls_bo->offset);
 663    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 664
 665    return 1;
 666 }
 667
 668 struct pipe_screen *
 669 nv50_screen_create(struct nouveau_device *dev)
 670 {
 671    struct nv50_screen *screen;
 672    struct pipe_screen *pscreen;
 673    struct nouveau_object *chan;
 674    uint64_t value;
 675    uint32_t tesla_class;
 676    unsigned stack_size;
 677    int ret;
 678
 679    screen = CALLOC_STRUCT(nv50_screen);
 680    if (!screen)
 681       return NULL;
 682    pscreen = &screen->base.base;
 683
 684    ret = nouveau_screen_init(&screen->base, dev);
 685    if (ret) {
 686       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 687       goto fail;
 688    }
 689
 690    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 691     *  admit them to VRAM.
 692     */
 693    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 694       PIPE_BIND_VERTEX_BUFFER;
 695    screen->base.sysmem_bindings |=
 696       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 697
 698    screen->base.pushbuf->user_priv = screen;
 699    screen->base.pushbuf->rsvd_kick = 5;
 700
 701    chan = screen->base.channel;
 702
 703    pscreen->destroy = nv50_screen_destroy;
 704    pscreen->context_create = nv50_create;
 705    pscreen->is_format_supported = nv50_screen_is_format_supported;
 706    pscreen->get_param = nv50_screen_get_param;
 707    pscreen->get_shader_param = nv50_screen_get_shader_param;
 708    pscreen->get_paramf = nv50_screen_get_paramf;
 709
 710    nv50_screen_init_resource_functions(pscreen);
 711
 712    if (screen->base.device->chipset < 0x84 ||
 713        debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
 714       /* PMPEG */
 715       nouveau_screen_init_vdec(&screen->base);
 716    } else if (screen->base.device->chipset < 0x98 ||
 717               screen->base.device->chipset == 0xa0) {
 718       /* VP2 */
 719       screen->base.base.get_video_param = nv84_screen_get_video_param;
 720       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 721    } else {
 722       /* VP3/4 */
 723       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 724       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 725    }
 726
 727    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 728                         NULL, &screen->fence.bo);
 729    if (ret) {
 730       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 731       goto fail;
 732    }
 733
 734    nouveau_bo_map(screen->fence.bo, 0, NULL);
 735    screen->fence.map = screen->fence.bo->map;
 736    screen->base.fence.emit = nv50_screen_fence_emit;
 737    screen->base.fence.update = nv50_screen_fence_update;
 738
 739    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 740                             &(struct nv04_notify){ .length = 32 },
 741                             sizeof(struct nv04_notify), &screen->sync);
 742    if (ret) {
 743       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 744       goto fail;
 745    }
 746
 747    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 748                             NULL, 0, &screen->m2mf);
 749    if (ret) {
 750       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 751       goto fail;
 752    }
 753
 754    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 755                             NULL, 0, &screen->eng2d);
 756    if (ret) {
 757       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 758       goto fail;
 759    }
 760
 761    switch (dev->chipset & 0xf0) {
 762    case 0x50:
 763       tesla_class = NV50_3D_CLASS;
 764       break;
 765    case 0x80:
 766    case 0x90:
 767       tesla_class = NV84_3D_CLASS;
 768       break;
 769    case 0xa0:
 770       switch (dev->chipset) {
 771       case 0xa0:
 772       case 0xaa:
 773       case 0xac:
 774          tesla_class = NVA0_3D_CLASS;
 775          break;
 776       case 0xaf:
 777          tesla_class = NVAF_3D_CLASS;
 778          break;
 779       default:
 780          tesla_class = NVA3_3D_CLASS;
 781          break;
 782       }
 783       break;
 784    default:
 785       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 786       goto fail;
 787    }
 788    screen->base.class_3d = tesla_class;
 789
 790    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 791                             NULL, 0, &screen->tesla);
 792    if (ret) {
 793       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 794       goto fail;
 795    }
 796
 797    /* This over-allocates by a page. The GP, which would execute at the end of
 798     * the last page, would trigger faults. The going theory is that it
 799     * prefetches up to a certain amount.
 800     */
 801    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 802                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 803                         NULL, &screen->code);
 804    if (ret) {
 805       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 806       goto fail;
 807    }
 808
 809    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 810    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 811    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 812
 813    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 814
 815    screen->TPs = util_bitcount(value & 0xffff);
 816    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 817
 818    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 819          STACK_WARPS_ALLOC * 64 * 8;
 820
 821    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 822                         &screen->stack_bo);
 823    if (ret) {
 824       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 825       goto fail;
 826    }
 827
 828    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 829          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 830          ONE_TEMP_SIZE;
 831    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 832    screen->max_tls_space /= 2; /* half of vram */
 833
 834    /* hw can address max 64 KiB */
 835    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 836
 837    uint64_t tls_size;
 838    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 839    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 840    if (ret)
 841       goto fail;
 842
 843    if (nouveau_mesa_debug)
 844       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 845             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 846
 847    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 848                         &screen->uniforms);
 849    if (ret) {
 850       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 851       goto fail;
 852    }
 853
 854    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 855                         &screen->txc);
 856    if (ret) {
 857       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 858       goto fail;
 859    }
 860
 861    screen->tic.entries = CALLOC(4096, sizeof(void *));
 862    screen->tsc.entries = screen->tic.entries + 2048;
 863
 864    if (!nv50_blitter_create(screen))
 865       goto fail;
 866
 867    nv50_screen_init_hwctx(screen);
 868
 869    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 870
 871    return pscreen;
 872
 873 fail:
 874    nv50_screen_destroy(pscreen);
 875    return NULL;
 876 }
 877
 878 int
 879 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 880 {
 881    int i = screen->tic.next;
 882
 883    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 884       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 885
 886    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 887
 888    if (screen->tic.entries[i])
 889       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 890
 891    screen->tic.entries[i] = entry;
 892    return i;
 893 }
 894
 895 int
 896 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 897 {
 898    int i = screen->tsc.next;
 899
 900    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 901       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 902
 903    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 904
 905    if (screen->tsc.entries[i])
 906       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 907
 908    screen->tsc.entries[i] = entry;
 909    return i;
 910 }