src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* shared is always supported */
  79    bindings &= ~(PIPE_BIND_LINEAR |
  80                  PIPE_BIND_SHARED);
  81
  82    return (( nv50_format_table[format].usage |
  83             nv50_vertex_format[format].usage) & bindings) == bindings;
  84 }
  85
  86 static int
  87 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  88 {
  89    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  90    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  91
  92    switch (param) {
  93    /* non-boolean caps */
  94    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  97       return 12;
  98    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  99       return 14;
 100    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 101       return 512;
 102    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 103    case PIPE_CAP_MIN_TEXEL_OFFSET:
 104       return -8;
 105    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MAX_TEXEL_OFFSET:
 107       return 7;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 128 * 1024 * 1024;
 110    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 111       return 330;
 112    case PIPE_CAP_MAX_RENDER_TARGETS:
 113       return 8;
 114    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 115       return 1;
 116    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 117       return 4;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 120       return 64;
 121    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 122    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 123       return 1024;
 124    case PIPE_CAP_MAX_VERTEX_STREAMS:
 125       return 1;
 126    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 127       return 2048;
 128    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 129       return 256;
 130    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 131       return 16; /* 256 for binding as RT, but that's not possible in GL */
 132    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 133       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 134    case PIPE_CAP_MAX_VIEWPORTS:
 135       return NV50_MAX_VIEWPORTS;
 136    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 137       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 138    case PIPE_CAP_ENDIANNESS:
 139       return PIPE_ENDIAN_LITTLE;
 140    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 141       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 142    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 143       return NV50_MAX_WINDOW_RECTANGLES;
 144
 145    /* supported caps */
 146    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 147    case PIPE_CAP_TEXTURE_SWIZZLE:
 148    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 149    case PIPE_CAP_NPOT_TEXTURES:
 150    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 152    case PIPE_CAP_ANISOTROPIC_FILTER:
 153    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 154    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 155    case PIPE_CAP_TWO_SIDED_STENCIL:
 156    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 157    case PIPE_CAP_POINT_SPRITE:
 158    case PIPE_CAP_SM3:
 159    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 160    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 161    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 162    case PIPE_CAP_QUERY_TIMESTAMP:
 163    case PIPE_CAP_QUERY_TIME_ELAPSED:
 164    case PIPE_CAP_OCCLUSION_QUERY:
 165    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 166    case PIPE_CAP_INDEP_BLEND_ENABLE:
 167    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 168    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 169    case PIPE_CAP_PRIMITIVE_RESTART:
 170    case PIPE_CAP_TGSI_INSTANCEID:
 171    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 172    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173    case PIPE_CAP_CONDITIONAL_RENDER:
 174    case PIPE_CAP_TEXTURE_BARRIER:
 175    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 176    case PIPE_CAP_START_INSTANCE:
 177    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 178    case PIPE_CAP_USER_VERTEX_BUFFERS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 181    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 182    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 183    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 184    case PIPE_CAP_CLIP_HALFZ:
 185    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 186    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 187    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 188    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 189    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 190    case PIPE_CAP_TGSI_TXQS:
 191    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 192    case PIPE_CAP_SHAREABLE_SHADERS:
 193    case PIPE_CAP_CLEAR_TEXTURE:
 194    case PIPE_CAP_COMPUTE:
 195    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 196    case PIPE_CAP_INVALIDATE_BUFFER:
 197    case PIPE_CAP_STRING_MARKER:
 198    case PIPE_CAP_CULL_DISTANCE:
 199    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 200    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 201    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 202    case PIPE_CAP_TGSI_CLOCK:
 203       return 1;
 204    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 205       return 1; /* class_3d >= NVA0_3D_CLASS; */
 206    /* supported on nva0+ */
 207    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 208       return class_3d >= NVA0_3D_CLASS;
 209    /* supported on nva3+ */
 210    case PIPE_CAP_CUBE_MAP_ARRAY:
 211    case PIPE_CAP_INDEP_BLEND_FUNC:
 212    case PIPE_CAP_TEXTURE_QUERY_LOD:
 213    case PIPE_CAP_SAMPLE_SHADING:
 214    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 215       return class_3d >= NVA3_3D_CLASS;
 216
 217    /* unsupported caps */
 218    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 219    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 220    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 221    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 222    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 223    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 224    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 225    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 226    case PIPE_CAP_TGSI_TEXCOORD:
 227    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 228    case PIPE_CAP_TEXTURE_GATHER_SM5:
 229    case PIPE_CAP_FAKE_SW_MSAA:
 230    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 231    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 232    case PIPE_CAP_DRAW_INDIRECT:
 233    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 235    case PIPE_CAP_VERTEXID_NOBASE:
 236    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 237    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 238    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 239    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 240    case PIPE_CAP_DRAW_PARAMETERS:
 241    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 242    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 243    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 244    case PIPE_CAP_GENERATE_MIPMAP:
 245    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 246    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 247    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 248    case PIPE_CAP_QUERY_MEMORY_INFO:
 249    case PIPE_CAP_PCI_GROUP:
 250    case PIPE_CAP_PCI_BUS:
 251    case PIPE_CAP_PCI_DEVICE:
 252    case PIPE_CAP_PCI_FUNCTION:
 253    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 254    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 255    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 256    case PIPE_CAP_TGSI_VOTE:
 257    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 258    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 259    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 260    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 261    case PIPE_CAP_NATIVE_FENCE_FD:
 262    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 263    case PIPE_CAP_TGSI_FS_FBFETCH:
 264    case PIPE_CAP_DOUBLES:
 265    case PIPE_CAP_INT64:
 266    case PIPE_CAP_INT64_DIVMOD:
 267    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 268    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 269    case PIPE_CAP_TGSI_BALLOT:
 270    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 271       return 0;
 272
 273    case PIPE_CAP_VENDOR_ID:
 274       return 0x10de;
 275    case PIPE_CAP_DEVICE_ID: {
 276       uint64_t device_id;
 277       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 278          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 279          return -1;
 280       }
 281       return device_id;
 282    }
 283    case PIPE_CAP_ACCELERATED:
 284       return 1;
 285    case PIPE_CAP_VIDEO_MEMORY:
 286       return dev->vram_size >> 20;
 287    case PIPE_CAP_UMA:
 288       return 0;
 289    }
 290
 291    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 292    return 0;
 293 }
 294
 295 static int
 296 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 297                              enum pipe_shader_type shader,
 298                              enum pipe_shader_cap param)
 299 {
 300    switch (shader) {
 301    case PIPE_SHADER_VERTEX:
 302    case PIPE_SHADER_GEOMETRY:
 303    case PIPE_SHADER_FRAGMENT:
 304       break;
 305    case PIPE_SHADER_COMPUTE:
 306    default:
 307       return 0;
 308    }
 309
 310    switch (param) {
 311    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 312    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 313    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 314    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 315       return 16384;
 316    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 317       return 4;
 318    case PIPE_SHADER_CAP_MAX_INPUTS:
 319       if (shader == PIPE_SHADER_VERTEX)
 320          return 32;
 321       return 15;
 322    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 323       return 16;
 324    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 325       return 65536;
 326    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 327       return NV50_MAX_PIPE_CONSTBUFS;
 328    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 329       return shader != PIPE_SHADER_FRAGMENT;
 330    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 331    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 332    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 333       return 1;
 334    case PIPE_SHADER_CAP_MAX_TEMPS:
 335       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 336    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 337       return 1;
 338    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 339       return 1;
 340    case PIPE_SHADER_CAP_SUBROUTINES:
 341       return 0; /* please inline, or provide function declarations */
 342    case PIPE_SHADER_CAP_INTEGERS:
 343       return 1;
 344    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 345       return 1;
 346    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 347       /* The chip could handle more sampler views than samplers */
 348    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 349       return MIN2(16, PIPE_MAX_SAMPLERS);
 350    case PIPE_SHADER_CAP_PREFERRED_IR:
 351       return PIPE_SHADER_IR_TGSI;
 352    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 353       return 32;
 354    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 355    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 356    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 357    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 358    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 359    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 360    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 361    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 362       return 0;
 363    default:
 364       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 365       return 0;
 366    }
 367 }
 368
 369 static float
 370 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 371 {
 372    switch (param) {
 373    case PIPE_CAPF_MAX_LINE_WIDTH:
 374    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 375       return 10.0f;
 376    case PIPE_CAPF_MAX_POINT_WIDTH:
 377    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 378       return 64.0f;
 379    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 380       return 16.0f;
 381    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 382       return 4.0f;
 383    case PIPE_CAPF_GUARD_BAND_LEFT:
 384    case PIPE_CAPF_GUARD_BAND_TOP:
 385       return 0.0f;
 386    case PIPE_CAPF_GUARD_BAND_RIGHT:
 387    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 388       return 0.0f; /* that or infinity */
 389    }
 390
 391    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 392    return 0.0f;
 393 }
 394
 395 static int
 396 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 397                               enum pipe_shader_ir ir_type,
 398                               enum pipe_compute_cap param, void *data)
 399 {
 400    struct nv50_screen *screen = nv50_screen(pscreen);
 401
 402 #define RET(x) do {                  \
 403    if (data)                         \
 404       memcpy(data, x, sizeof(x));    \
 405    return sizeof(x);                 \
 406 } while (0)
 407
 408    switch (param) {
 409    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 410       RET((uint64_t []) { 2 });
 411    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 412       RET(((uint64_t []) { 65535, 65535 }));
 413    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 414       RET(((uint64_t []) { 512, 512, 64 }));
 415    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 416       RET((uint64_t []) { 512 });
 417    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 418       RET((uint64_t []) { 1ULL << 32 });
 419    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 420       RET((uint64_t []) { 16 << 10 });
 421    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 422       RET((uint64_t []) { 16 << 10 });
 423    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 424       RET((uint64_t []) { 4096 });
 425    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 426       RET((uint32_t []) { 32 });
 427    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 428       RET((uint64_t []) { 1ULL << 40 });
 429    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 430       RET((uint32_t []) { 0 });
 431    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 432       RET((uint32_t []) { screen->mp_count });
 433    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 434       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 435    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 436       RET((uint32_t []) { 32 });
 437    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 438       RET((uint64_t []) { 0 });
 439    default:
 440       return 0;
 441    }
 442
 443 #undef RET
 444 }
 445
 446 static void
 447 nv50_screen_destroy(struct pipe_screen *pscreen)
 448 {
 449    struct nv50_screen *screen = nv50_screen(pscreen);
 450
 451    if (!nouveau_drm_screen_unref(&screen->base))
 452       return;
 453
 454    if (screen->base.fence.current) {
 455       struct nouveau_fence *current = NULL;
 456
 457       /* nouveau_fence_wait will create a new current fence, so wait on the
 458        * _current_ one, and remove both.
 459        */
 460       nouveau_fence_ref(screen->base.fence.current, &current);
 461       nouveau_fence_wait(current, NULL);
 462       nouveau_fence_ref(NULL, &current);
 463       nouveau_fence_ref(NULL, &screen->base.fence.current);
 464    }
 465    if (screen->base.pushbuf)
 466       screen->base.pushbuf->user_priv = NULL;
 467
 468    if (screen->blitter)
 469       nv50_blitter_destroy(screen);
 470    if (screen->pm.prog) {
 471       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 472       nv50_program_destroy(NULL, screen->pm.prog);
 473       FREE(screen->pm.prog);
 474    }
 475
 476    nouveau_bo_ref(NULL, &screen->code);
 477    nouveau_bo_ref(NULL, &screen->tls_bo);
 478    nouveau_bo_ref(NULL, &screen->stack_bo);
 479    nouveau_bo_ref(NULL, &screen->txc);
 480    nouveau_bo_ref(NULL, &screen->uniforms);
 481    nouveau_bo_ref(NULL, &screen->fence.bo);
 482
 483    nouveau_heap_destroy(&screen->vp_code_heap);
 484    nouveau_heap_destroy(&screen->gp_code_heap);
 485    nouveau_heap_destroy(&screen->fp_code_heap);
 486
 487    FREE(screen->tic.entries);
 488
 489    nouveau_object_del(&screen->tesla);
 490    nouveau_object_del(&screen->eng2d);
 491    nouveau_object_del(&screen->m2mf);
 492    nouveau_object_del(&screen->compute);
 493    nouveau_object_del(&screen->sync);
 494
 495    nouveau_screen_fini(&screen->base);
 496
 497    FREE(screen);
 498 }
 499
 500 static void
 501 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 502 {
 503    struct nv50_screen *screen = nv50_screen(pscreen);
 504    struct nouveau_pushbuf *push = screen->base.pushbuf;
 505
 506    /* we need to do it after possible flush in MARK_RING */
 507    *sequence = ++screen->base.fence.sequence;
 508
 509    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 510    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 511    PUSH_DATAh(push, screen->fence.bo->offset);
 512    PUSH_DATA (push, screen->fence.bo->offset);
 513    PUSH_DATA (push, *sequence);
 514    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 515                     NV50_3D_QUERY_GET_UNK4 |
 516                     NV50_3D_QUERY_GET_UNIT_CROP |
 517                     NV50_3D_QUERY_GET_TYPE_QUERY |
 518                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 519                     NV50_3D_QUERY_GET_SHORT);
 520 }
 521
 522 static u32
 523 nv50_screen_fence_update(struct pipe_screen *pscreen)
 524 {
 525    return nv50_screen(pscreen)->fence.map[0];
 526 }
 527
 528 static void
 529 nv50_screen_init_hwctx(struct nv50_screen *screen)
 530 {
 531    struct nouveau_pushbuf *push = screen->base.pushbuf;
 532    struct nv04_fifo *fifo;
 533    unsigned i;
 534
 535    fifo = (struct nv04_fifo *)screen->base.channel->data;
 536
 537    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 538    PUSH_DATA (push, screen->m2mf->handle);
 539    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 540    PUSH_DATA (push, screen->sync->handle);
 541    PUSH_DATA (push, fifo->vram);
 542    PUSH_DATA (push, fifo->vram);
 543
 544    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 545    PUSH_DATA (push, screen->eng2d->handle);
 546    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 547    PUSH_DATA (push, screen->sync->handle);
 548    PUSH_DATA (push, fifo->vram);
 549    PUSH_DATA (push, fifo->vram);
 550    PUSH_DATA (push, fifo->vram);
 551    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 552    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 553    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 554    PUSH_DATA (push, 0);
 555    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 556    PUSH_DATA (push, 0);
 557    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 558    PUSH_DATA (push, 1);
 559    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 560    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 561
 562    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 563    PUSH_DATA (push, screen->tesla->handle);
 564
 565    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 566    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 567
 568    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 569    PUSH_DATA (push, screen->sync->handle);
 570    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 571    for (i = 0; i < 11; ++i)
 572       PUSH_DATA(push, fifo->vram);
 573    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 574    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 575       PUSH_DATA(push, fifo->vram);
 576
 577    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 578    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 579    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 580    PUSH_DATA (push, 0xf);
 581
 582    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 583       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 584       PUSH_DATA (push, 0x18);
 585    }
 586
 587    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 588    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 589
 590    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 591    for (i = 0; i < 8; ++i)
 592       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 593
 594    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 595    PUSH_DATA (push, 1);
 596
 597    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 598    PUSH_DATA (push, 0);
 599    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 600    PUSH_DATA (push, 0);
 601    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 602    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 603    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 604    PUSH_DATA (push, 0);
 605    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 606    PUSH_DATA (push, 1);
 607    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 608    PUSH_DATA (push, 1);
 609
 610    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 611       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 612       PUSH_DATA (push, 0);
 613    }
 614
 615    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 616    PUSH_DATA (push, 0);
 617    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 618    PUSH_DATA (push, 0);
 619    PUSH_DATA (push, 0);
 620    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 621    PUSH_DATA (push, 0x3f);
 622
 623    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 624    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 625    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 626
 627    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 628    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 629    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 630
 631    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 632    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 633    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 634
 635    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 636    PUSH_DATAh(push, screen->tls_bo->offset);
 637    PUSH_DATA (push, screen->tls_bo->offset);
 638    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 639
 640    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 641    PUSH_DATAh(push, screen->stack_bo->offset);
 642    PUSH_DATA (push, screen->stack_bo->offset);
 643    PUSH_DATA (push, 4);
 644
 645    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 646    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 647    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 648    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 649
 650    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 651    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 652    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 653    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 654
 655    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 656    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 657    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 658    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 659
 660    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 661    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 662    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 663    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 664
 665    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 666    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 667    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 668    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 669
 670    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 671    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 672    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 673    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 674    PUSH_DATAf(push, 0.0f);
 675    PUSH_DATAf(push, 0.0f);
 676    PUSH_DATAf(push, 0.0f);
 677    PUSH_DATAf(push, 0.0f);
 678    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 679    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 680    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 681
 682    nv50_upload_ms_info(push);
 683
 684    /* max TIC (bits 4:8) & TSC bindings, per program type */
 685    for (i = 0; i < 3; ++i) {
 686       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 687       PUSH_DATA (push, 0x54);
 688    }
 689
 690    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 691    PUSH_DATAh(push, screen->txc->offset);
 692    PUSH_DATA (push, screen->txc->offset);
 693    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 694
 695    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 696    PUSH_DATAh(push, screen->txc->offset + 65536);
 697    PUSH_DATA (push, screen->txc->offset + 65536);
 698    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 699
 700    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 701    PUSH_DATA (push, 0);
 702
 703    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 704    PUSH_DATA (push, 0);
 705    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 706    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 707    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 708    for (i = 0; i < 8 * 2; ++i)
 709       PUSH_DATA(push, 0);
 710    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 711    PUSH_DATA (push, 0);
 712
 713    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 714    PUSH_DATA (push, 1);
 715    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 716       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 717       PUSH_DATAf(push, 0.0f);
 718       PUSH_DATAf(push, 1.0f);
 719       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 720       PUSH_DATA (push, 8192 << 16);
 721       PUSH_DATA (push, 8192 << 16);
 722    }
 723
 724    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 725 #ifdef NV50_SCISSORS_CLIPPING
 726    PUSH_DATA (push, 0x0000);
 727 #else
 728    PUSH_DATA (push, 0x1080);
 729 #endif
 730
 731    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 732    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 733
 734    /* We use scissors instead of exact view volume clipping,
 735     * so they're always enabled.
 736     */
 737    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 738       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 739       PUSH_DATA (push, 1);
 740       PUSH_DATA (push, 8192 << 16);
 741       PUSH_DATA (push, 8192 << 16);
 742    }
 743
 744    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 745    PUSH_DATA (push, 1);
 746    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 747    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 748    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 749    PUSH_DATA (push, 0x11111111);
 750    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 751    PUSH_DATA (push, 1);
 752
 753    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 754    PUSH_DATA (push, 0);
 755    if (screen->base.class_3d >= NV84_3D_CLASS) {
 756       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 757       PUSH_DATA (push, 0);
 758    }
 759
 760    PUSH_KICK (push);
 761 }
 762
 763 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 764       uint64_t *tls_size)
 765 {
 766    struct nouveau_device *dev = screen->base.device;
 767    int ret;
 768
 769    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 770          ONE_TEMP_SIZE;
 771    if (nouveau_mesa_debug)
 772       debug_printf("allocating space for %u temps\n",
 773             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 774    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 775          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 776
 777    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 778                         *tls_size, NULL, &screen->tls_bo);
 779    if (ret) {
 780       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 781       return ret;
 782    }
 783
 784    return 0;
 785 }
 786
 787 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 788 {
 789    struct nouveau_pushbuf *push = screen->base.pushbuf;
 790    int ret;
 791    uint64_t tls_size;
 792
 793    if (tls_space < screen->cur_tls_space)
 794       return 0;
 795    if (tls_space > screen->max_tls_space) {
 796       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 797        * LOCAL_WARPS_NO_CLAMP) */
 798       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 799             (unsigned)(tls_space / ONE_TEMP_SIZE),
 800             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 801       return -ENOMEM;
 802    }
 803
 804    nouveau_bo_ref(NULL, &screen->tls_bo);
 805    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 806    if (ret)
 807       return ret;
 808
 809    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 810    PUSH_DATAh(push, screen->tls_bo->offset);
 811    PUSH_DATA (push, screen->tls_bo->offset);
 812    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 813
 814    return 1;
 815 }
 816
 817 struct nouveau_screen *
 818 nv50_screen_create(struct nouveau_device *dev)
 819 {
 820    struct nv50_screen *screen;
 821    struct pipe_screen *pscreen;
 822    struct nouveau_object *chan;
 823    uint64_t value;
 824    uint32_t tesla_class;
 825    unsigned stack_size;
 826    int ret;
 827
 828    screen = CALLOC_STRUCT(nv50_screen);
 829    if (!screen)
 830       return NULL;
 831    pscreen = &screen->base.base;
 832    pscreen->destroy = nv50_screen_destroy;
 833
 834    ret = nouveau_screen_init(&screen->base, dev);
 835    if (ret) {
 836       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 837       goto fail;
 838    }
 839
 840    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 841     *  admit them to VRAM.
 842     */
 843    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 844       PIPE_BIND_VERTEX_BUFFER;
 845    screen->base.sysmem_bindings |=
 846       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 847
 848    screen->base.pushbuf->user_priv = screen;
 849    screen->base.pushbuf->rsvd_kick = 5;
 850
 851    chan = screen->base.channel;
 852
 853    pscreen->context_create = nv50_create;
 854    pscreen->is_format_supported = nv50_screen_is_format_supported;
 855    pscreen->get_param = nv50_screen_get_param;
 856    pscreen->get_shader_param = nv50_screen_get_shader_param;
 857    pscreen->get_paramf = nv50_screen_get_paramf;
 858    pscreen->get_compute_param = nv50_screen_get_compute_param;
 859    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 860    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 861
 862    nv50_screen_init_resource_functions(pscreen);
 863
 864    if (screen->base.device->chipset < 0x84 ||
 865        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 866       /* PMPEG */
 867       nouveau_screen_init_vdec(&screen->base);
 868    } else if (screen->base.device->chipset < 0x98 ||
 869               screen->base.device->chipset == 0xa0) {
 870       /* VP2 */
 871       screen->base.base.get_video_param = nv84_screen_get_video_param;
 872       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 873    } else {
 874       /* VP3/4 */
 875       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 876       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 877    }
 878
 879    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 880                         NULL, &screen->fence.bo);
 881    if (ret) {
 882       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 883       goto fail;
 884    }
 885
 886    nouveau_bo_map(screen->fence.bo, 0, NULL);
 887    screen->fence.map = screen->fence.bo->map;
 888    screen->base.fence.emit = nv50_screen_fence_emit;
 889    screen->base.fence.update = nv50_screen_fence_update;
 890
 891    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 892                             &(struct nv04_notify){ .length = 32 },
 893                             sizeof(struct nv04_notify), &screen->sync);
 894    if (ret) {
 895       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 896       goto fail;
 897    }
 898
 899    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 900                             NULL, 0, &screen->m2mf);
 901    if (ret) {
 902       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 903       goto fail;
 904    }
 905
 906    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 907                             NULL, 0, &screen->eng2d);
 908    if (ret) {
 909       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 910       goto fail;
 911    }
 912
 913    switch (dev->chipset & 0xf0) {
 914    case 0x50:
 915       tesla_class = NV50_3D_CLASS;
 916       break;
 917    case 0x80:
 918    case 0x90:
 919       tesla_class = NV84_3D_CLASS;
 920       break;
 921    case 0xa0:
 922       switch (dev->chipset) {
 923       case 0xa0:
 924       case 0xaa:
 925       case 0xac:
 926          tesla_class = NVA0_3D_CLASS;
 927          break;
 928       case 0xaf:
 929          tesla_class = NVAF_3D_CLASS;
 930          break;
 931       default:
 932          tesla_class = NVA3_3D_CLASS;
 933          break;
 934       }
 935       break;
 936    default:
 937       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 938       goto fail;
 939    }
 940    screen->base.class_3d = tesla_class;
 941
 942    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 943                             NULL, 0, &screen->tesla);
 944    if (ret) {
 945       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 946       goto fail;
 947    }
 948
 949    /* This over-allocates by a page. The GP, which would execute at the end of
 950     * the last page, would trigger faults. The going theory is that it
 951     * prefetches up to a certain amount.
 952     */
 953    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 954                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 955                         NULL, &screen->code);
 956    if (ret) {
 957       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 958       goto fail;
 959    }
 960
 961    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 962    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 963    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 964
 965    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 966
 967    screen->TPs = util_bitcount(value & 0xffff);
 968    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 969
 970    screen->mp_count = screen->TPs * screen->MPsInTP;
 971
 972    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 973          STACK_WARPS_ALLOC * 64 * 8;
 974
 975    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 976                         &screen->stack_bo);
 977    if (ret) {
 978       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 979       goto fail;
 980    }
 981
 982    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 983          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 984          ONE_TEMP_SIZE;
 985    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 986    screen->max_tls_space /= 2; /* half of vram */
 987
 988    /* hw can address max 64 KiB */
 989    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 990
 991    uint64_t tls_size;
 992    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 993    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 994    if (ret)
 995       goto fail;
 996
 997    if (nouveau_mesa_debug)
 998       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 999             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1000
1001    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1002                         &screen->uniforms);
1003    if (ret) {
1004       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1005       goto fail;
1006    }
1007
1008    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1009                         &screen->txc);
1010    if (ret) {
1011       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1012       goto fail;
1013    }
1014
1015    screen->tic.entries = CALLOC(4096, sizeof(void *));
1016    screen->tsc.entries = screen->tic.entries + 2048;
1017
1018    if (!nv50_blitter_create(screen))
1019       goto fail;
1020
1021    nv50_screen_init_hwctx(screen);
1022
1023    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1024    if (ret) {
1025       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1026       goto fail;
1027    }
1028
1029    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1030
1031    return &screen->base;
1032
1033 fail:
1034    screen->base.base.context_create = NULL;
1035    return &screen->base;
1036 }
1037
1038 int
1039 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1040 {
1041    int i = screen->tic.next;
1042
1043    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1044       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1045
1046    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1047
1048    if (screen->tic.entries[i])
1049       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1050
1051    screen->tic.entries[i] = entry;
1052    return i;
1053 }
1054
1055 int
1056 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1057 {
1058    int i = screen->tsc.next;
1059
1060    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1061       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1062
1063    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1064
1065    if (screen->tsc.entries[i])
1066       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1067
1068    screen->tsc.entries[i] = entry;
1069    return i;
1070 }