src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30
  31 #include "nv50/nv50_context.h"
  32 #include "nv50/nv50_screen.h"
  33
  34 #include "nouveau_vp3_video.h"
  35
  36 #include "nv_object.xml.h"
  37
  38 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  39 #define LOCAL_WARPS_ALLOC 32
  40 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  41 #define STACK_WARPS_ALLOC 32
  42
  43 #define THREADS_IN_WARP 32
  44
  45 static boolean
  46 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  47                                 enum pipe_format format,
  48                                 enum pipe_texture_target target,
  49                                 unsigned sample_count,
  50                                 unsigned storage_sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (sample_count > 8)
  54       return false;
  55    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  56       return false;
  57    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  58       return false;
  59
  60    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  61       return false;
  62
  63    switch (format) {
  64    case PIPE_FORMAT_Z16_UNORM:
  65       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  66          return false;
  67       break;
  68    default:
  69       break;
  70    }
  71
  72    if (bindings & PIPE_BIND_LINEAR)
  73       if (util_format_is_depth_or_stencil(format) ||
  74           (target != PIPE_TEXTURE_1D &&
  75            target != PIPE_TEXTURE_2D &&
  76            target != PIPE_TEXTURE_RECT) ||
  77           sample_count > 1)
  78          return false;
  79
  80    /* shared is always supported */
  81    bindings &= ~(PIPE_BIND_LINEAR |
  82                  PIPE_BIND_SHARED);
  83
  84    return (( nv50_format_table[format].usage |
  85             nv50_vertex_format[format].usage) & bindings) == bindings;
  86 }
  87
  88 static int
  89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  90 {
  91    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  92    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  93
  94    switch (param) {
  95    /* non-boolean caps */
  96    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  97       return 14;
  98    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  99       return 12;
 100    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 101       return 14;
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103       return 512;
 104    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 105    case PIPE_CAP_MIN_TEXEL_OFFSET:
 106       return -8;
 107    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109       return 7;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 128 * 1024 * 1024;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 113       return 330;
 114    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 115       return 330;
 116    case PIPE_CAP_MAX_RENDER_TARGETS:
 117       return 8;
 118    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 119       return 1;
 120    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 121    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 122       return 8;
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124       return 4;
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 127       return 64;
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130       return 1024;
 131    case PIPE_CAP_MAX_VERTEX_STREAMS:
 132       return 1;
 133    case PIPE_CAP_MAX_GS_INVOCATIONS:
 134       return 0;
 135    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 136       return 0;
 137    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 138       return 2048;
 139    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 140       return 2047;
 141    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 142       return 256;
 143    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 144       return 16; /* 256 for binding as RT, but that's not possible in GL */
 145    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 146       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 147    case PIPE_CAP_MAX_VIEWPORTS:
 148       return NV50_MAX_VIEWPORTS;
 149    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 150       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 151    case PIPE_CAP_ENDIANNESS:
 152       return PIPE_ENDIAN_LITTLE;
 153    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 154       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 155    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 156       return NV50_MAX_WINDOW_RECTANGLES;
 157
 158    /* supported caps */
 159    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 160    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 161    case PIPE_CAP_TEXTURE_SWIZZLE:
 162    case PIPE_CAP_NPOT_TEXTURES:
 163    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 164    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 165    case PIPE_CAP_ANISOTROPIC_FILTER:
 166    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 167    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 168    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 169    case PIPE_CAP_POINT_SPRITE:
 170    case PIPE_CAP_SM3:
 171    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 172    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 173    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 174    case PIPE_CAP_QUERY_TIMESTAMP:
 175    case PIPE_CAP_QUERY_TIME_ELAPSED:
 176    case PIPE_CAP_OCCLUSION_QUERY:
 177    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 178    case PIPE_CAP_INDEP_BLEND_ENABLE:
 179    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 180    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 181    case PIPE_CAP_PRIMITIVE_RESTART:
 182    case PIPE_CAP_TGSI_INSTANCEID:
 183    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 184    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 185    case PIPE_CAP_CONDITIONAL_RENDER:
 186    case PIPE_CAP_TEXTURE_BARRIER:
 187    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 188    case PIPE_CAP_START_INSTANCE:
 189    case PIPE_CAP_USER_VERTEX_BUFFERS:
 190    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 191    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 192    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 193    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 194    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 195    case PIPE_CAP_CLIP_HALFZ:
 196    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 197    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 198    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 199    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 200    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 201    case PIPE_CAP_TGSI_TXQS:
 202    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 203    case PIPE_CAP_SHAREABLE_SHADERS:
 204    case PIPE_CAP_CLEAR_TEXTURE:
 205    case PIPE_CAP_COMPUTE:
 206    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 207    case PIPE_CAP_INVALIDATE_BUFFER:
 208    case PIPE_CAP_STRING_MARKER:
 209    case PIPE_CAP_CULL_DISTANCE:
 210    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 211    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 212    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 213    case PIPE_CAP_TGSI_CLOCK:
 214    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 215    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 216       return 1;
 217    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 218       return 1; /* class_3d >= NVA0_3D_CLASS; */
 219    /* supported on nva0+ */
 220    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 221       return class_3d >= NVA0_3D_CLASS;
 222    /* supported on nva3+ */
 223    case PIPE_CAP_CUBE_MAP_ARRAY:
 224    case PIPE_CAP_INDEP_BLEND_FUNC:
 225    case PIPE_CAP_TEXTURE_QUERY_LOD:
 226    case PIPE_CAP_SAMPLE_SHADING:
 227    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 228       return class_3d >= NVA3_3D_CLASS;
 229
 230    /* unsupported caps */
 231    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 232    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 233    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 234    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 235    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 236    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 237    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 238    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 239    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 240    case PIPE_CAP_TGSI_TEXCOORD:
 241    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 242    case PIPE_CAP_TEXTURE_GATHER_SM5:
 243    case PIPE_CAP_FAKE_SW_MSAA:
 244    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 245    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 246    case PIPE_CAP_DRAW_INDIRECT:
 247    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 248    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 249    case PIPE_CAP_VERTEXID_NOBASE:
 250    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 251    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 252    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 253    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 254    case PIPE_CAP_DRAW_PARAMETERS:
 255    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 256    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 257    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 258    case PIPE_CAP_GENERATE_MIPMAP:
 259    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 260    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 261    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 262    case PIPE_CAP_QUERY_MEMORY_INFO:
 263    case PIPE_CAP_PCI_GROUP:
 264    case PIPE_CAP_PCI_BUS:
 265    case PIPE_CAP_PCI_DEVICE:
 266    case PIPE_CAP_PCI_FUNCTION:
 267    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 268    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 269    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 270    case PIPE_CAP_TGSI_VOTE:
 271    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 272    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 273    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 274    case PIPE_CAP_NATIVE_FENCE_FD:
 275    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 276    case PIPE_CAP_TGSI_FS_FBFETCH:
 277    case PIPE_CAP_DOUBLES:
 278    case PIPE_CAP_INT64:
 279    case PIPE_CAP_INT64_DIVMOD:
 280    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 281    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 282    case PIPE_CAP_TGSI_BALLOT:
 283    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 284    case PIPE_CAP_POST_DEPTH_COVERAGE:
 285    case PIPE_CAP_BINDLESS_TEXTURE:
 286    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 287    case PIPE_CAP_QUERY_SO_OVERFLOW:
 288    case PIPE_CAP_MEMOBJ:
 289    case PIPE_CAP_LOAD_CONSTBUF:
 290    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 291    case PIPE_CAP_TILE_RASTER_ORDER:
 292    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 293    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 294    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 295    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 296    case PIPE_CAP_FENCE_SIGNAL:
 297    case PIPE_CAP_CONSTBUF0_FLAGS:
 298    case PIPE_CAP_PACKED_UNIFORMS:
 299    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 300    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 301    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 302    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 303    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 304    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 305    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 306    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 307    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 308    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 309    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 310       return 0;
 311
 312    case PIPE_CAP_VENDOR_ID:
 313       return 0x10de;
 314    case PIPE_CAP_DEVICE_ID: {
 315       uint64_t device_id;
 316       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 317          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 318          return -1;
 319       }
 320       return device_id;
 321    }
 322    case PIPE_CAP_ACCELERATED:
 323       return 1;
 324    case PIPE_CAP_VIDEO_MEMORY:
 325       return dev->vram_size >> 20;
 326    case PIPE_CAP_UMA:
 327       return 0;
 328    default:
 329       debug_printf("%s: unhandled cap %d\n", __func__, param);
 330       return u_pipe_screen_get_param_defaults(pscreen, param);
 331    }
 332 }
 333
 334 static int
 335 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 336                              enum pipe_shader_type shader,
 337                              enum pipe_shader_cap param)
 338 {
 339    switch (shader) {
 340    case PIPE_SHADER_VERTEX:
 341    case PIPE_SHADER_GEOMETRY:
 342    case PIPE_SHADER_FRAGMENT:
 343       break;
 344    case PIPE_SHADER_COMPUTE:
 345    default:
 346       return 0;
 347    }
 348
 349    switch (param) {
 350    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 351    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 352    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 353    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 354       return 16384;
 355    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 356       return 4;
 357    case PIPE_SHADER_CAP_MAX_INPUTS:
 358       if (shader == PIPE_SHADER_VERTEX)
 359          return 32;
 360       return 15;
 361    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 362       return 16;
 363    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 364       return 65536;
 365    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 366       return NV50_MAX_PIPE_CONSTBUFS;
 367    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 368       return shader != PIPE_SHADER_FRAGMENT;
 369    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 370    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 371    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 372       return 1;
 373    case PIPE_SHADER_CAP_MAX_TEMPS:
 374       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 375    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 376       return 1;
 377    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 378       return 1;
 379    case PIPE_SHADER_CAP_INT64_ATOMICS:
 380    case PIPE_SHADER_CAP_FP16:
 381    case PIPE_SHADER_CAP_SUBROUTINES:
 382       return 0; /* please inline, or provide function declarations */
 383    case PIPE_SHADER_CAP_INTEGERS:
 384       return 1;
 385    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 386       return 1;
 387    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 388       /* The chip could handle more sampler views than samplers */
 389    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 390       return MIN2(16, PIPE_MAX_SAMPLERS);
 391    case PIPE_SHADER_CAP_PREFERRED_IR:
 392       return PIPE_SHADER_IR_TGSI;
 393    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 394       return 32;
 395    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 396    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 397    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 398    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 399    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 400    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 401    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 402    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 403    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 404    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 405    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 406       return 0;
 407    case PIPE_SHADER_CAP_SCALAR_ISA:
 408       return 1;
 409    default:
 410       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 411       return 0;
 412    }
 413 }
 414
 415 static float
 416 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 417 {
 418    switch (param) {
 419    case PIPE_CAPF_MAX_LINE_WIDTH:
 420    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 421       return 10.0f;
 422    case PIPE_CAPF_MAX_POINT_WIDTH:
 423    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 424       return 64.0f;
 425    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 426       return 16.0f;
 427    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 428       return 4.0f;
 429    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 430    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 431    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 432       return 0.0f;
 433    }
 434
 435    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 436    return 0.0f;
 437 }
 438
 439 static int
 440 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 441                               enum pipe_shader_ir ir_type,
 442                               enum pipe_compute_cap param, void *data)
 443 {
 444    struct nv50_screen *screen = nv50_screen(pscreen);
 445
 446 #define RET(x) do {                  \
 447    if (data)                         \
 448       memcpy(data, x, sizeof(x));    \
 449    return sizeof(x);                 \
 450 } while (0)
 451
 452    switch (param) {
 453    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 454       RET((uint64_t []) { 2 });
 455    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 456       RET(((uint64_t []) { 65535, 65535 }));
 457    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 458       RET(((uint64_t []) { 512, 512, 64 }));
 459    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 460       RET((uint64_t []) { 512 });
 461    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 462       RET((uint64_t []) { 1ULL << 32 });
 463    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 464       RET((uint64_t []) { 16 << 10 });
 465    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 466       RET((uint64_t []) { 16 << 10 });
 467    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 468       RET((uint64_t []) { 4096 });
 469    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 470       RET((uint32_t []) { 32 });
 471    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 472       RET((uint64_t []) { 1ULL << 40 });
 473    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 474       RET((uint32_t []) { 0 });
 475    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 476       RET((uint32_t []) { screen->mp_count });
 477    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 478       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 479    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 480       RET((uint32_t []) { 32 });
 481    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 482       RET((uint64_t []) { 0 });
 483    default:
 484       return 0;
 485    }
 486
 487 #undef RET
 488 }
 489
 490 static void
 491 nv50_screen_destroy(struct pipe_screen *pscreen)
 492 {
 493    struct nv50_screen *screen = nv50_screen(pscreen);
 494
 495    if (!nouveau_drm_screen_unref(&screen->base))
 496       return;
 497
 498    if (screen->base.fence.current) {
 499       struct nouveau_fence *current = NULL;
 500
 501       /* nouveau_fence_wait will create a new current fence, so wait on the
 502        * _current_ one, and remove both.
 503        */
 504       nouveau_fence_ref(screen->base.fence.current, &current);
 505       nouveau_fence_wait(current, NULL);
 506       nouveau_fence_ref(NULL, &current);
 507       nouveau_fence_ref(NULL, &screen->base.fence.current);
 508    }
 509    if (screen->base.pushbuf)
 510       screen->base.pushbuf->user_priv = NULL;
 511
 512    if (screen->blitter)
 513       nv50_blitter_destroy(screen);
 514    if (screen->pm.prog) {
 515       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 516       nv50_program_destroy(NULL, screen->pm.prog);
 517       FREE(screen->pm.prog);
 518    }
 519
 520    nouveau_bo_ref(NULL, &screen->code);
 521    nouveau_bo_ref(NULL, &screen->tls_bo);
 522    nouveau_bo_ref(NULL, &screen->stack_bo);
 523    nouveau_bo_ref(NULL, &screen->txc);
 524    nouveau_bo_ref(NULL, &screen->uniforms);
 525    nouveau_bo_ref(NULL, &screen->fence.bo);
 526
 527    nouveau_heap_destroy(&screen->vp_code_heap);
 528    nouveau_heap_destroy(&screen->gp_code_heap);
 529    nouveau_heap_destroy(&screen->fp_code_heap);
 530
 531    FREE(screen->tic.entries);
 532
 533    nouveau_object_del(&screen->tesla);
 534    nouveau_object_del(&screen->eng2d);
 535    nouveau_object_del(&screen->m2mf);
 536    nouveau_object_del(&screen->compute);
 537    nouveau_object_del(&screen->sync);
 538
 539    nouveau_screen_fini(&screen->base);
 540
 541    FREE(screen);
 542 }
 543
 544 static void
 545 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 546 {
 547    struct nv50_screen *screen = nv50_screen(pscreen);
 548    struct nouveau_pushbuf *push = screen->base.pushbuf;
 549
 550    /* we need to do it after possible flush in MARK_RING */
 551    *sequence = ++screen->base.fence.sequence;
 552
 553    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 554    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 555    PUSH_DATAh(push, screen->fence.bo->offset);
 556    PUSH_DATA (push, screen->fence.bo->offset);
 557    PUSH_DATA (push, *sequence);
 558    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 559                     NV50_3D_QUERY_GET_UNK4 |
 560                     NV50_3D_QUERY_GET_UNIT_CROP |
 561                     NV50_3D_QUERY_GET_TYPE_QUERY |
 562                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 563                     NV50_3D_QUERY_GET_SHORT);
 564 }
 565
 566 static u32
 567 nv50_screen_fence_update(struct pipe_screen *pscreen)
 568 {
 569    return nv50_screen(pscreen)->fence.map[0];
 570 }
 571
 572 static void
 573 nv50_screen_init_hwctx(struct nv50_screen *screen)
 574 {
 575    struct nouveau_pushbuf *push = screen->base.pushbuf;
 576    struct nv04_fifo *fifo;
 577    unsigned i;
 578
 579    fifo = (struct nv04_fifo *)screen->base.channel->data;
 580
 581    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 582    PUSH_DATA (push, screen->m2mf->handle);
 583    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 584    PUSH_DATA (push, screen->sync->handle);
 585    PUSH_DATA (push, fifo->vram);
 586    PUSH_DATA (push, fifo->vram);
 587
 588    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 589    PUSH_DATA (push, screen->eng2d->handle);
 590    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 591    PUSH_DATA (push, screen->sync->handle);
 592    PUSH_DATA (push, fifo->vram);
 593    PUSH_DATA (push, fifo->vram);
 594    PUSH_DATA (push, fifo->vram);
 595    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 596    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 597    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 598    PUSH_DATA (push, 0);
 599    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 600    PUSH_DATA (push, 0);
 601    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 602    PUSH_DATA (push, 1);
 603    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 604    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 605
 606    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 607    PUSH_DATA (push, screen->tesla->handle);
 608
 609    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 610    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 611
 612    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 613    PUSH_DATA (push, screen->sync->handle);
 614    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 615    for (i = 0; i < 11; ++i)
 616       PUSH_DATA(push, fifo->vram);
 617    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 618    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 619       PUSH_DATA(push, fifo->vram);
 620
 621    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 622    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 623    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 624    PUSH_DATA (push, 0xf);
 625
 626    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 627       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 628       PUSH_DATA (push, 0x18);
 629    }
 630
 631    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 632    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 633
 634    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 635    for (i = 0; i < 8; ++i)
 636       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 637
 638    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 639    PUSH_DATA (push, 1);
 640
 641    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 642    PUSH_DATA (push, 0);
 643    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 644    PUSH_DATA (push, 0);
 645    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 646    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 647    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 648    PUSH_DATA (push, 0);
 649    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 650    PUSH_DATA (push, 1);
 651    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 652    PUSH_DATA (push, 1);
 653
 654    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 655       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 656       PUSH_DATA (push, 0);
 657    }
 658
 659    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 660    PUSH_DATA (push, 0);
 661    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 662    PUSH_DATA (push, 0);
 663    PUSH_DATA (push, 0);
 664    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 665    PUSH_DATA (push, 0x3f);
 666
 667    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 668    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 669    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 670
 671    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 672    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 673    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 674
 675    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 676    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 677    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 678
 679    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 680    PUSH_DATAh(push, screen->tls_bo->offset);
 681    PUSH_DATA (push, screen->tls_bo->offset);
 682    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 683
 684    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 685    PUSH_DATAh(push, screen->stack_bo->offset);
 686    PUSH_DATA (push, screen->stack_bo->offset);
 687    PUSH_DATA (push, 4);
 688
 689    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 690    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 691    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 692    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 693
 694    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 695    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 696    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 697    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 698
 699    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 700    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 701    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 702    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 703
 704    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 705    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 706    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 707    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 708
 709    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 710    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 711    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 712    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 713
 714    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 715    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 716    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 717    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 718    PUSH_DATAf(push, 0.0f);
 719    PUSH_DATAf(push, 0.0f);
 720    PUSH_DATAf(push, 0.0f);
 721    PUSH_DATAf(push, 0.0f);
 722    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 723    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 724    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 725
 726    nv50_upload_ms_info(push);
 727
 728    /* max TIC (bits 4:8) & TSC bindings, per program type */
 729    for (i = 0; i < 3; ++i) {
 730       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 731       PUSH_DATA (push, 0x54);
 732    }
 733
 734    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 735    PUSH_DATAh(push, screen->txc->offset);
 736    PUSH_DATA (push, screen->txc->offset);
 737    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 738
 739    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 740    PUSH_DATAh(push, screen->txc->offset + 65536);
 741    PUSH_DATA (push, screen->txc->offset + 65536);
 742    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 743
 744    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 745    PUSH_DATA (push, 0);
 746
 747    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 748    PUSH_DATA (push, 0);
 749    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 750    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 751    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 752    for (i = 0; i < 8 * 2; ++i)
 753       PUSH_DATA(push, 0);
 754    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 755    PUSH_DATA (push, 0);
 756
 757    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 758    PUSH_DATA (push, 1);
 759    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 760       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 761       PUSH_DATAf(push, 0.0f);
 762       PUSH_DATAf(push, 1.0f);
 763       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 764       PUSH_DATA (push, 8192 << 16);
 765       PUSH_DATA (push, 8192 << 16);
 766    }
 767
 768    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 769 #ifdef NV50_SCISSORS_CLIPPING
 770    PUSH_DATA (push, 0x0000);
 771 #else
 772    PUSH_DATA (push, 0x1080);
 773 #endif
 774
 775    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 776    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 777
 778    /* We use scissors instead of exact view volume clipping,
 779     * so they're always enabled.
 780     */
 781    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 782       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 783       PUSH_DATA (push, 1);
 784       PUSH_DATA (push, 8192 << 16);
 785       PUSH_DATA (push, 8192 << 16);
 786    }
 787
 788    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 789    PUSH_DATA (push, 1);
 790    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 791    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 792    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 793    PUSH_DATA (push, 0x11111111);
 794    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 795    PUSH_DATA (push, 1);
 796
 797    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 798    PUSH_DATA (push, 0);
 799    if (screen->base.class_3d >= NV84_3D_CLASS) {
 800       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 801       PUSH_DATA (push, 0);
 802    }
 803
 804    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 805    PUSH_DATA (push, 1);
 806    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 807    PUSH_DATA (push, 1);
 808
 809    PUSH_KICK (push);
 810 }
 811
 812 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 813       uint64_t *tls_size)
 814 {
 815    struct nouveau_device *dev = screen->base.device;
 816    int ret;
 817
 818    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 819          ONE_TEMP_SIZE;
 820    if (nouveau_mesa_debug)
 821       debug_printf("allocating space for %u temps\n",
 822             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 823    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 824          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 825
 826    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 827                         *tls_size, NULL, &screen->tls_bo);
 828    if (ret) {
 829       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 830       return ret;
 831    }
 832
 833    return 0;
 834 }
 835
 836 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 837 {
 838    struct nouveau_pushbuf *push = screen->base.pushbuf;
 839    int ret;
 840    uint64_t tls_size;
 841
 842    if (tls_space < screen->cur_tls_space)
 843       return 0;
 844    if (tls_space > screen->max_tls_space) {
 845       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 846        * LOCAL_WARPS_NO_CLAMP) */
 847       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 848             (unsigned)(tls_space / ONE_TEMP_SIZE),
 849             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 850       return -ENOMEM;
 851    }
 852
 853    nouveau_bo_ref(NULL, &screen->tls_bo);
 854    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 855    if (ret)
 856       return ret;
 857
 858    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 859    PUSH_DATAh(push, screen->tls_bo->offset);
 860    PUSH_DATA (push, screen->tls_bo->offset);
 861    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 862
 863    return 1;
 864 }
 865
 866 struct nouveau_screen *
 867 nv50_screen_create(struct nouveau_device *dev)
 868 {
 869    struct nv50_screen *screen;
 870    struct pipe_screen *pscreen;
 871    struct nouveau_object *chan;
 872    uint64_t value;
 873    uint32_t tesla_class;
 874    unsigned stack_size;
 875    int ret;
 876
 877    screen = CALLOC_STRUCT(nv50_screen);
 878    if (!screen)
 879       return NULL;
 880    pscreen = &screen->base.base;
 881    pscreen->destroy = nv50_screen_destroy;
 882
 883    ret = nouveau_screen_init(&screen->base, dev);
 884    if (ret) {
 885       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 886       goto fail;
 887    }
 888
 889    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 890     *  admit them to VRAM.
 891     */
 892    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 893       PIPE_BIND_VERTEX_BUFFER;
 894    screen->base.sysmem_bindings |=
 895       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 896
 897    screen->base.pushbuf->user_priv = screen;
 898    screen->base.pushbuf->rsvd_kick = 5;
 899
 900    chan = screen->base.channel;
 901
 902    pscreen->context_create = nv50_create;
 903    pscreen->is_format_supported = nv50_screen_is_format_supported;
 904    pscreen->get_param = nv50_screen_get_param;
 905    pscreen->get_shader_param = nv50_screen_get_shader_param;
 906    pscreen->get_paramf = nv50_screen_get_paramf;
 907    pscreen->get_compute_param = nv50_screen_get_compute_param;
 908    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 909    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 910
 911    nv50_screen_init_resource_functions(pscreen);
 912
 913    if (screen->base.device->chipset < 0x84 ||
 914        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 915       /* PMPEG */
 916       nouveau_screen_init_vdec(&screen->base);
 917    } else if (screen->base.device->chipset < 0x98 ||
 918               screen->base.device->chipset == 0xa0) {
 919       /* VP2 */
 920       screen->base.base.get_video_param = nv84_screen_get_video_param;
 921       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 922    } else {
 923       /* VP3/4 */
 924       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 925       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 926    }
 927
 928    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 929                         NULL, &screen->fence.bo);
 930    if (ret) {
 931       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 932       goto fail;
 933    }
 934
 935    nouveau_bo_map(screen->fence.bo, 0, NULL);
 936    screen->fence.map = screen->fence.bo->map;
 937    screen->base.fence.emit = nv50_screen_fence_emit;
 938    screen->base.fence.update = nv50_screen_fence_update;
 939
 940    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 941                             &(struct nv04_notify){ .length = 32 },
 942                             sizeof(struct nv04_notify), &screen->sync);
 943    if (ret) {
 944       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 945       goto fail;
 946    }
 947
 948    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 949                             NULL, 0, &screen->m2mf);
 950    if (ret) {
 951       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 952       goto fail;
 953    }
 954
 955    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 956                             NULL, 0, &screen->eng2d);
 957    if (ret) {
 958       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 959       goto fail;
 960    }
 961
 962    switch (dev->chipset & 0xf0) {
 963    case 0x50:
 964       tesla_class = NV50_3D_CLASS;
 965       break;
 966    case 0x80:
 967    case 0x90:
 968       tesla_class = NV84_3D_CLASS;
 969       break;
 970    case 0xa0:
 971       switch (dev->chipset) {
 972       case 0xa0:
 973       case 0xaa:
 974       case 0xac:
 975          tesla_class = NVA0_3D_CLASS;
 976          break;
 977       case 0xaf:
 978          tesla_class = NVAF_3D_CLASS;
 979          break;
 980       default:
 981          tesla_class = NVA3_3D_CLASS;
 982          break;
 983       }
 984       break;
 985    default:
 986       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 987       goto fail;
 988    }
 989    screen->base.class_3d = tesla_class;
 990
 991    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 992                             NULL, 0, &screen->tesla);
 993    if (ret) {
 994       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 995       goto fail;
 996    }
 997
 998    /* This over-allocates by a page. The GP, which would execute at the end of
 999     * the last page, would trigger faults. The going theory is that it
1000     * prefetches up to a certain amount.
1001     */
1002    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
1003                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
1004                         NULL, &screen->code);
1005    if (ret) {
1006       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
1007       goto fail;
1008    }
1009
1010    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1011    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1012    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1013
1014    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1015
1016    screen->TPs = util_bitcount(value & 0xffff);
1017    screen->MPsInTP = util_bitcount(value & 0x0f000000);
1018
1019    screen->mp_count = screen->TPs * screen->MPsInTP;
1020
1021    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1022          STACK_WARPS_ALLOC * 64 * 8;
1023
1024    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1025                         &screen->stack_bo);
1026    if (ret) {
1027       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1028       goto fail;
1029    }
1030
1031    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1032          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1033          ONE_TEMP_SIZE;
1034    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1035    screen->max_tls_space /= 2; /* half of vram */
1036
1037    /* hw can address max 64 KiB */
1038    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1039
1040    uint64_t tls_size;
1041    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1042    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1043    if (ret)
1044       goto fail;
1045
1046    if (nouveau_mesa_debug)
1047       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1048             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1049
1050    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1051                         &screen->uniforms);
1052    if (ret) {
1053       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1054       goto fail;
1055    }
1056
1057    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1058                         &screen->txc);
1059    if (ret) {
1060       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1061       goto fail;
1062    }
1063
1064    screen->tic.entries = CALLOC(4096, sizeof(void *));
1065    screen->tsc.entries = screen->tic.entries + 2048;
1066
1067    if (!nv50_blitter_create(screen))
1068       goto fail;
1069
1070    nv50_screen_init_hwctx(screen);
1071
1072    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1073    if (ret) {
1074       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1075       goto fail;
1076    }
1077
1078    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1079
1080    return &screen->base;
1081
1082 fail:
1083    screen->base.base.context_create = NULL;
1084    return &screen->base;
1085 }
1086
1087 int
1088 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1089 {
1090    int i = screen->tic.next;
1091
1092    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1093       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1094
1095    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1096
1097    if (screen->tic.entries[i])
1098       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1099
1100    screen->tic.entries[i] = entry;
1101    return i;
1102 }
1103
1104 int
1105 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1106 {
1107    int i = screen->tsc.next;
1108
1109    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1110       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1111
1112    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1113
1114    if (screen->tsc.entries[i])
1115       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1116
1117    screen->tsc.entries[i] = entry;
1118    return i;
1119 }