src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* transfers & shared are always supported */
  79    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  80                  PIPE_BIND_TRANSFER_WRITE |
  81                  PIPE_BIND_LINEAR |
  82                  PIPE_BIND_SHARED);
  83
  84    return (( nv50_format_table[format].usage |
  85             nv50_vertex_format[format].usage) & bindings) == bindings;
  86 }
  87
  88 static int
  89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  90 {
  91    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  92    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  93
  94    switch (param) {
  95    /* non-boolean caps */
  96    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  97       return 14;
  98    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  99       return 12;
 100    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 101       return 14;
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103       return 512;
 104    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 105    case PIPE_CAP_MIN_TEXEL_OFFSET:
 106       return -8;
 107    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109       return 7;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 128 * 1024 * 1024;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 113       return 330;
 114    case PIPE_CAP_MAX_RENDER_TARGETS:
 115       return 8;
 116    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 117       return 1;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 119       return 4;
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122       return 64;
 123    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 124    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 125       return 1024;
 126    case PIPE_CAP_MAX_VERTEX_STREAMS:
 127       return 1;
 128    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 129       return 2048;
 130    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 131       return 256;
 132    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 133       return 16; /* 256 for binding as RT, but that's not possible in GL */
 134    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 135       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 136    case PIPE_CAP_MAX_VIEWPORTS:
 137       return NV50_MAX_VIEWPORTS;
 138    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 139       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 140    case PIPE_CAP_ENDIANNESS:
 141       return PIPE_ENDIAN_LITTLE;
 142    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 143       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 144    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 145       return NV50_MAX_WINDOW_RECTANGLES;
 146
 147    /* supported caps */
 148    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 149    case PIPE_CAP_TEXTURE_SWIZZLE:
 150    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 151    case PIPE_CAP_NPOT_TEXTURES:
 152    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 153    case PIPE_CAP_ANISOTROPIC_FILTER:
 154    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 155    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 156    case PIPE_CAP_TWO_SIDED_STENCIL:
 157    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 158    case PIPE_CAP_POINT_SPRITE:
 159    case PIPE_CAP_SM3:
 160    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 161    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 162    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 163    case PIPE_CAP_QUERY_TIMESTAMP:
 164    case PIPE_CAP_QUERY_TIME_ELAPSED:
 165    case PIPE_CAP_OCCLUSION_QUERY:
 166    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 167    case PIPE_CAP_INDEP_BLEND_ENABLE:
 168    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 169    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 170    case PIPE_CAP_PRIMITIVE_RESTART:
 171    case PIPE_CAP_TGSI_INSTANCEID:
 172    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 173    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 174    case PIPE_CAP_CONDITIONAL_RENDER:
 175    case PIPE_CAP_TEXTURE_BARRIER:
 176    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 177    case PIPE_CAP_START_INSTANCE:
 178    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 179    case PIPE_CAP_USER_INDEX_BUFFERS:
 180    case PIPE_CAP_USER_VERTEX_BUFFERS:
 181    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 182    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 183    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 184    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 185    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 186    case PIPE_CAP_CLIP_HALFZ:
 187    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 188    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 189    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 190    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 191    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 192    case PIPE_CAP_TGSI_TXQS:
 193    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 194    case PIPE_CAP_SHAREABLE_SHADERS:
 195    case PIPE_CAP_CLEAR_TEXTURE:
 196    case PIPE_CAP_COMPUTE:
 197    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 198    case PIPE_CAP_INVALIDATE_BUFFER:
 199    case PIPE_CAP_STRING_MARKER:
 200    case PIPE_CAP_CULL_DISTANCE:
 201       return 1;
 202    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 203       return 1; /* class_3d >= NVA0_3D_CLASS; */
 204    /* supported on nva0+ */
 205    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 206       return class_3d >= NVA0_3D_CLASS;
 207    /* supported on nva3+ */
 208    case PIPE_CAP_CUBE_MAP_ARRAY:
 209    case PIPE_CAP_INDEP_BLEND_FUNC:
 210    case PIPE_CAP_TEXTURE_QUERY_LOD:
 211    case PIPE_CAP_SAMPLE_SHADING:
 212    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 213       return class_3d >= NVA3_3D_CLASS;
 214
 215    /* unsupported caps */
 216    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 217    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 218    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 219    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 220    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 221    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 222    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 223    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 224    case PIPE_CAP_TGSI_TEXCOORD:
 225    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 226    case PIPE_CAP_TEXTURE_GATHER_SM5:
 227    case PIPE_CAP_FAKE_SW_MSAA:
 228    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 229    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 230    case PIPE_CAP_DRAW_INDIRECT:
 231    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 232    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 233    case PIPE_CAP_VERTEXID_NOBASE:
 234    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 235    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 236    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 237    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 238    case PIPE_CAP_DRAW_PARAMETERS:
 239    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 240    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 241    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 242    case PIPE_CAP_GENERATE_MIPMAP:
 243    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 244    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 245    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 246    case PIPE_CAP_QUERY_MEMORY_INFO:
 247    case PIPE_CAP_PCI_GROUP:
 248    case PIPE_CAP_PCI_BUS:
 249    case PIPE_CAP_PCI_DEVICE:
 250    case PIPE_CAP_PCI_FUNCTION:
 251    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 252    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 253    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 254    case PIPE_CAP_TGSI_VOTE:
 255       return 0;
 256
 257    case PIPE_CAP_VENDOR_ID:
 258       return 0x10de;
 259    case PIPE_CAP_DEVICE_ID: {
 260       uint64_t device_id;
 261       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 262          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 263          return -1;
 264       }
 265       return device_id;
 266    }
 267    case PIPE_CAP_ACCELERATED:
 268       return 1;
 269    case PIPE_CAP_VIDEO_MEMORY:
 270       return dev->vram_size >> 20;
 271    case PIPE_CAP_UMA:
 272       return 0;
 273    }
 274
 275    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 276    return 0;
 277 }
 278
 279 static int
 280 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 281                              enum pipe_shader_cap param)
 282 {
 283    switch (shader) {
 284    case PIPE_SHADER_VERTEX:
 285    case PIPE_SHADER_GEOMETRY:
 286    case PIPE_SHADER_FRAGMENT:
 287       break;
 288    case PIPE_SHADER_COMPUTE:
 289    default:
 290       return 0;
 291    }
 292
 293    switch (param) {
 294    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 295    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 296    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 297    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 298       return 16384;
 299    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 300       return 4;
 301    case PIPE_SHADER_CAP_MAX_INPUTS:
 302       if (shader == PIPE_SHADER_VERTEX)
 303          return 32;
 304       return 15;
 305    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 306       return 16;
 307    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 308       return 65536;
 309    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 310       return NV50_MAX_PIPE_CONSTBUFS;
 311    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 312       return shader != PIPE_SHADER_FRAGMENT;
 313    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 314    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 315    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 316       return 1;
 317    case PIPE_SHADER_CAP_MAX_PREDS:
 318       return 0;
 319    case PIPE_SHADER_CAP_MAX_TEMPS:
 320       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 321    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 322       return 1;
 323    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 324       return 1;
 325    case PIPE_SHADER_CAP_SUBROUTINES:
 326       return 0; /* please inline, or provide function declarations */
 327    case PIPE_SHADER_CAP_INTEGERS:
 328       return 1;
 329    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 330       /* The chip could handle more sampler views than samplers */
 331    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 332       return MIN2(16, PIPE_MAX_SAMPLERS);
 333    case PIPE_SHADER_CAP_PREFERRED_IR:
 334       return PIPE_SHADER_IR_TGSI;
 335    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 336       return 32;
 337    case PIPE_SHADER_CAP_DOUBLES:
 338    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 339    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 340    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 341    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 342    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 343    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 344    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 345       return 0;
 346    default:
 347       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 348       return 0;
 349    }
 350 }
 351
 352 static float
 353 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 354 {
 355    switch (param) {
 356    case PIPE_CAPF_MAX_LINE_WIDTH:
 357    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 358       return 10.0f;
 359    case PIPE_CAPF_MAX_POINT_WIDTH:
 360    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 361       return 64.0f;
 362    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 363       return 16.0f;
 364    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 365       return 4.0f;
 366    case PIPE_CAPF_GUARD_BAND_LEFT:
 367    case PIPE_CAPF_GUARD_BAND_TOP:
 368       return 0.0f;
 369    case PIPE_CAPF_GUARD_BAND_RIGHT:
 370    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 371       return 0.0f; /* that or infinity */
 372    }
 373
 374    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 375    return 0.0f;
 376 }
 377
 378 static int
 379 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 380                               enum pipe_shader_ir ir_type,
 381                               enum pipe_compute_cap param, void *data)
 382 {
 383    struct nv50_screen *screen = nv50_screen(pscreen);
 384
 385 #define RET(x) do {                  \
 386    if (data)                         \
 387       memcpy(data, x, sizeof(x));    \
 388    return sizeof(x);                 \
 389 } while (0)
 390
 391    switch (param) {
 392    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 393       RET((uint64_t []) { 2 });
 394    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 395       RET(((uint64_t []) { 65535, 65535 }));
 396    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 397       RET(((uint64_t []) { 512, 512, 64 }));
 398    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 399       RET((uint64_t []) { 512 });
 400    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 401       RET((uint64_t []) { 1ULL << 32 });
 402    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 403       RET((uint64_t []) { 16 << 10 });
 404    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 405       RET((uint64_t []) { 16 << 10 });
 406    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 407       RET((uint64_t []) { 4096 });
 408    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 409       RET((uint32_t []) { 32 });
 410    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 411       RET((uint64_t []) { 1ULL << 40 });
 412    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 413       RET((uint32_t []) { 0 });
 414    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 415       RET((uint32_t []) { screen->mp_count });
 416    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 417       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 418    default:
 419       return 0;
 420    }
 421
 422 #undef RET
 423 }
 424
 425 static void
 426 nv50_screen_destroy(struct pipe_screen *pscreen)
 427 {
 428    struct nv50_screen *screen = nv50_screen(pscreen);
 429
 430    if (!nouveau_drm_screen_unref(&screen->base))
 431       return;
 432
 433    if (screen->base.fence.current) {
 434       struct nouveau_fence *current = NULL;
 435
 436       /* nouveau_fence_wait will create a new current fence, so wait on the
 437        * _current_ one, and remove both.
 438        */
 439       nouveau_fence_ref(screen->base.fence.current, &current);
 440       nouveau_fence_wait(current, NULL);
 441       nouveau_fence_ref(NULL, &current);
 442       nouveau_fence_ref(NULL, &screen->base.fence.current);
 443    }
 444    if (screen->base.pushbuf)
 445       screen->base.pushbuf->user_priv = NULL;
 446
 447    if (screen->blitter)
 448       nv50_blitter_destroy(screen);
 449    if (screen->pm.prog) {
 450       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 451       nv50_program_destroy(NULL, screen->pm.prog);
 452       FREE(screen->pm.prog);
 453    }
 454
 455    nouveau_bo_ref(NULL, &screen->code);
 456    nouveau_bo_ref(NULL, &screen->tls_bo);
 457    nouveau_bo_ref(NULL, &screen->stack_bo);
 458    nouveau_bo_ref(NULL, &screen->txc);
 459    nouveau_bo_ref(NULL, &screen->uniforms);
 460    nouveau_bo_ref(NULL, &screen->fence.bo);
 461
 462    nouveau_heap_destroy(&screen->vp_code_heap);
 463    nouveau_heap_destroy(&screen->gp_code_heap);
 464    nouveau_heap_destroy(&screen->fp_code_heap);
 465
 466    FREE(screen->tic.entries);
 467
 468    nouveau_object_del(&screen->tesla);
 469    nouveau_object_del(&screen->eng2d);
 470    nouveau_object_del(&screen->m2mf);
 471    nouveau_object_del(&screen->compute);
 472    nouveau_object_del(&screen->sync);
 473
 474    nouveau_screen_fini(&screen->base);
 475
 476    FREE(screen);
 477 }
 478
 479 static void
 480 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 481 {
 482    struct nv50_screen *screen = nv50_screen(pscreen);
 483    struct nouveau_pushbuf *push = screen->base.pushbuf;
 484
 485    /* we need to do it after possible flush in MARK_RING */
 486    *sequence = ++screen->base.fence.sequence;
 487
 488    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 489    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 490    PUSH_DATAh(push, screen->fence.bo->offset);
 491    PUSH_DATA (push, screen->fence.bo->offset);
 492    PUSH_DATA (push, *sequence);
 493    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 494                     NV50_3D_QUERY_GET_UNK4 |
 495                     NV50_3D_QUERY_GET_UNIT_CROP |
 496                     NV50_3D_QUERY_GET_TYPE_QUERY |
 497                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 498                     NV50_3D_QUERY_GET_SHORT);
 499 }
 500
 501 static u32
 502 nv50_screen_fence_update(struct pipe_screen *pscreen)
 503 {
 504    return nv50_screen(pscreen)->fence.map[0];
 505 }
 506
 507 static void
 508 nv50_screen_init_hwctx(struct nv50_screen *screen)
 509 {
 510    struct nouveau_pushbuf *push = screen->base.pushbuf;
 511    struct nv04_fifo *fifo;
 512    unsigned i;
 513
 514    fifo = (struct nv04_fifo *)screen->base.channel->data;
 515
 516    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 517    PUSH_DATA (push, screen->m2mf->handle);
 518    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 519    PUSH_DATA (push, screen->sync->handle);
 520    PUSH_DATA (push, fifo->vram);
 521    PUSH_DATA (push, fifo->vram);
 522
 523    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 524    PUSH_DATA (push, screen->eng2d->handle);
 525    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 526    PUSH_DATA (push, screen->sync->handle);
 527    PUSH_DATA (push, fifo->vram);
 528    PUSH_DATA (push, fifo->vram);
 529    PUSH_DATA (push, fifo->vram);
 530    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 531    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 532    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 533    PUSH_DATA (push, 0);
 534    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 535    PUSH_DATA (push, 0);
 536    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 537    PUSH_DATA (push, 1);
 538    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 539    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 540
 541    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 542    PUSH_DATA (push, screen->tesla->handle);
 543
 544    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 545    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 546
 547    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 548    PUSH_DATA (push, screen->sync->handle);
 549    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 550    for (i = 0; i < 11; ++i)
 551       PUSH_DATA(push, fifo->vram);
 552    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 553    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 554       PUSH_DATA(push, fifo->vram);
 555
 556    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 557    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 558    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 559    PUSH_DATA (push, 0xf);
 560
 561    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 562       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 563       PUSH_DATA (push, 0x18);
 564    }
 565
 566    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 567    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 568
 569    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 570    for (i = 0; i < 8; ++i)
 571       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 572
 573    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 574    PUSH_DATA (push, 1);
 575
 576    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 577    PUSH_DATA (push, 0);
 578    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 579    PUSH_DATA (push, 0);
 580    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 581    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 582    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 583    PUSH_DATA (push, 0);
 584    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 585    PUSH_DATA (push, 1);
 586    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 587    PUSH_DATA (push, 1);
 588
 589    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 590       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 591       PUSH_DATA (push, 0);
 592    }
 593
 594    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 595    PUSH_DATA (push, 0);
 596    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 597    PUSH_DATA (push, 0);
 598    PUSH_DATA (push, 0);
 599    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 600    PUSH_DATA (push, 0x3f);
 601
 602    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 603    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 604    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 605
 606    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 607    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 608    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 609
 610    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 611    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 612    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 613
 614    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 615    PUSH_DATAh(push, screen->tls_bo->offset);
 616    PUSH_DATA (push, screen->tls_bo->offset);
 617    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 618
 619    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 620    PUSH_DATAh(push, screen->stack_bo->offset);
 621    PUSH_DATA (push, screen->stack_bo->offset);
 622    PUSH_DATA (push, 4);
 623
 624    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 625    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 626    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 627    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 628
 629    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 630    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 631    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 632    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 633
 634    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 635    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 636    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 637    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 638
 639    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 640    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 641    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 642    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 643
 644    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 645    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 646    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 647    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 648
 649    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 650    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 651    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 652    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 653    PUSH_DATAf(push, 0.0f);
 654    PUSH_DATAf(push, 0.0f);
 655    PUSH_DATAf(push, 0.0f);
 656    PUSH_DATAf(push, 0.0f);
 657    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 658    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 659    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 660
 661    nv50_upload_ms_info(push);
 662
 663    /* max TIC (bits 4:8) & TSC bindings, per program type */
 664    for (i = 0; i < 3; ++i) {
 665       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 666       PUSH_DATA (push, 0x54);
 667    }
 668
 669    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 670    PUSH_DATAh(push, screen->txc->offset);
 671    PUSH_DATA (push, screen->txc->offset);
 672    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 673
 674    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 675    PUSH_DATAh(push, screen->txc->offset + 65536);
 676    PUSH_DATA (push, screen->txc->offset + 65536);
 677    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 678
 679    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 680    PUSH_DATA (push, 0);
 681
 682    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 683    PUSH_DATA (push, 0);
 684    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 685    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 686    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 687    for (i = 0; i < 8 * 2; ++i)
 688       PUSH_DATA(push, 0);
 689    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 690    PUSH_DATA (push, 0);
 691
 692    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 693    PUSH_DATA (push, 1);
 694    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 695       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 696       PUSH_DATAf(push, 0.0f);
 697       PUSH_DATAf(push, 1.0f);
 698       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 699       PUSH_DATA (push, 8192 << 16);
 700       PUSH_DATA (push, 8192 << 16);
 701    }
 702
 703    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 704 #ifdef NV50_SCISSORS_CLIPPING
 705    PUSH_DATA (push, 0x0000);
 706 #else
 707    PUSH_DATA (push, 0x1080);
 708 #endif
 709
 710    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 711    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 712
 713    /* We use scissors instead of exact view volume clipping,
 714     * so they're always enabled.
 715     */
 716    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 717       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 718       PUSH_DATA (push, 1);
 719       PUSH_DATA (push, 8192 << 16);
 720       PUSH_DATA (push, 8192 << 16);
 721    }
 722
 723    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 724    PUSH_DATA (push, 1);
 725    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 726    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 727    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 728    PUSH_DATA (push, 0x11111111);
 729    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 730    PUSH_DATA (push, 1);
 731
 732    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 733    PUSH_DATA (push, 0);
 734    if (screen->base.class_3d >= NV84_3D_CLASS) {
 735       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 736       PUSH_DATA (push, 0);
 737    }
 738
 739    PUSH_KICK (push);
 740 }
 741
 742 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 743       uint64_t *tls_size)
 744 {
 745    struct nouveau_device *dev = screen->base.device;
 746    int ret;
 747
 748    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 749          ONE_TEMP_SIZE;
 750    if (nouveau_mesa_debug)
 751       debug_printf("allocating space for %u temps\n",
 752             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 753    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 754          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 755
 756    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 757                         *tls_size, NULL, &screen->tls_bo);
 758    if (ret) {
 759       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 760       return ret;
 761    }
 762
 763    return 0;
 764 }
 765
 766 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 767 {
 768    struct nouveau_pushbuf *push = screen->base.pushbuf;
 769    int ret;
 770    uint64_t tls_size;
 771
 772    if (tls_space < screen->cur_tls_space)
 773       return 0;
 774    if (tls_space > screen->max_tls_space) {
 775       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 776        * LOCAL_WARPS_NO_CLAMP) */
 777       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 778             (unsigned)(tls_space / ONE_TEMP_SIZE),
 779             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 780       return -ENOMEM;
 781    }
 782
 783    nouveau_bo_ref(NULL, &screen->tls_bo);
 784    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 785    if (ret)
 786       return ret;
 787
 788    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 789    PUSH_DATAh(push, screen->tls_bo->offset);
 790    PUSH_DATA (push, screen->tls_bo->offset);
 791    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 792
 793    return 1;
 794 }
 795
 796 struct nouveau_screen *
 797 nv50_screen_create(struct nouveau_device *dev)
 798 {
 799    struct nv50_screen *screen;
 800    struct pipe_screen *pscreen;
 801    struct nouveau_object *chan;
 802    uint64_t value;
 803    uint32_t tesla_class;
 804    unsigned stack_size;
 805    int ret;
 806
 807    screen = CALLOC_STRUCT(nv50_screen);
 808    if (!screen)
 809       return NULL;
 810    pscreen = &screen->base.base;
 811    pscreen->destroy = nv50_screen_destroy;
 812
 813    ret = nouveau_screen_init(&screen->base, dev);
 814    if (ret) {
 815       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 816       goto fail;
 817    }
 818
 819    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 820     *  admit them to VRAM.
 821     */
 822    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 823       PIPE_BIND_VERTEX_BUFFER;
 824    screen->base.sysmem_bindings |=
 825       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 826
 827    screen->base.pushbuf->user_priv = screen;
 828    screen->base.pushbuf->rsvd_kick = 5;
 829
 830    chan = screen->base.channel;
 831
 832    pscreen->context_create = nv50_create;
 833    pscreen->is_format_supported = nv50_screen_is_format_supported;
 834    pscreen->get_param = nv50_screen_get_param;
 835    pscreen->get_shader_param = nv50_screen_get_shader_param;
 836    pscreen->get_paramf = nv50_screen_get_paramf;
 837    pscreen->get_compute_param = nv50_screen_get_compute_param;
 838    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 839    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 840
 841    nv50_screen_init_resource_functions(pscreen);
 842
 843    if (screen->base.device->chipset < 0x84 ||
 844        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 845       /* PMPEG */
 846       nouveau_screen_init_vdec(&screen->base);
 847    } else if (screen->base.device->chipset < 0x98 ||
 848               screen->base.device->chipset == 0xa0) {
 849       /* VP2 */
 850       screen->base.base.get_video_param = nv84_screen_get_video_param;
 851       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 852    } else {
 853       /* VP3/4 */
 854       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 855       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 856    }
 857
 858    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 859                         NULL, &screen->fence.bo);
 860    if (ret) {
 861       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 862       goto fail;
 863    }
 864
 865    nouveau_bo_map(screen->fence.bo, 0, NULL);
 866    screen->fence.map = screen->fence.bo->map;
 867    screen->base.fence.emit = nv50_screen_fence_emit;
 868    screen->base.fence.update = nv50_screen_fence_update;
 869
 870    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 871                             &(struct nv04_notify){ .length = 32 },
 872                             sizeof(struct nv04_notify), &screen->sync);
 873    if (ret) {
 874       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 875       goto fail;
 876    }
 877
 878    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 879                             NULL, 0, &screen->m2mf);
 880    if (ret) {
 881       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 882       goto fail;
 883    }
 884
 885    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 886                             NULL, 0, &screen->eng2d);
 887    if (ret) {
 888       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 889       goto fail;
 890    }
 891
 892    switch (dev->chipset & 0xf0) {
 893    case 0x50:
 894       tesla_class = NV50_3D_CLASS;
 895       break;
 896    case 0x80:
 897    case 0x90:
 898       tesla_class = NV84_3D_CLASS;
 899       break;
 900    case 0xa0:
 901       switch (dev->chipset) {
 902       case 0xa0:
 903       case 0xaa:
 904       case 0xac:
 905          tesla_class = NVA0_3D_CLASS;
 906          break;
 907       case 0xaf:
 908          tesla_class = NVAF_3D_CLASS;
 909          break;
 910       default:
 911          tesla_class = NVA3_3D_CLASS;
 912          break;
 913       }
 914       break;
 915    default:
 916       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 917       goto fail;
 918    }
 919    screen->base.class_3d = tesla_class;
 920
 921    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 922                             NULL, 0, &screen->tesla);
 923    if (ret) {
 924       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 925       goto fail;
 926    }
 927
 928    /* This over-allocates by a page. The GP, which would execute at the end of
 929     * the last page, would trigger faults. The going theory is that it
 930     * prefetches up to a certain amount.
 931     */
 932    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 933                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 934                         NULL, &screen->code);
 935    if (ret) {
 936       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 937       goto fail;
 938    }
 939
 940    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 941    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 942    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 943
 944    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 945
 946    screen->TPs = util_bitcount(value & 0xffff);
 947    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 948
 949    screen->mp_count = screen->TPs * screen->MPsInTP;
 950
 951    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 952          STACK_WARPS_ALLOC * 64 * 8;
 953
 954    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 955                         &screen->stack_bo);
 956    if (ret) {
 957       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 958       goto fail;
 959    }
 960
 961    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 962          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 963          ONE_TEMP_SIZE;
 964    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 965    screen->max_tls_space /= 2; /* half of vram */
 966
 967    /* hw can address max 64 KiB */
 968    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 969
 970    uint64_t tls_size;
 971    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 972    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 973    if (ret)
 974       goto fail;
 975
 976    if (nouveau_mesa_debug)
 977       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 978             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 979
 980    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 981                         &screen->uniforms);
 982    if (ret) {
 983       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 984       goto fail;
 985    }
 986
 987    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 988                         &screen->txc);
 989    if (ret) {
 990       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 991       goto fail;
 992    }
 993
 994    screen->tic.entries = CALLOC(4096, sizeof(void *));
 995    screen->tsc.entries = screen->tic.entries + 2048;
 996
 997    if (!nv50_blitter_create(screen))
 998       goto fail;
 999
1000    nv50_screen_init_hwctx(screen);
1001
1002    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1003    if (ret) {
1004       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1005       goto fail;
1006    }
1007
1008    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1009
1010    return &screen->base;
1011
1012 fail:
1013    screen->base.base.context_create = NULL;
1014    return &screen->base;
1015 }
1016
1017 int
1018 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1019 {
1020    int i = screen->tic.next;
1021
1022    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1023       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1024
1025    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1026
1027    if (screen->tic.entries[i])
1028       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1029
1030    screen->tic.entries[i] = entry;
1031    return i;
1032 }
1033
1034 int
1035 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1036 {
1037    int i = screen->tsc.next;
1038
1039    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1040       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1041
1042    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1043
1044    if (screen->tsc.entries[i])
1045       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1046
1047    screen->tsc.entries[i] = entry;
1048    return i;
1049 }