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gallium: add PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <errno.h>
24 #include <xf86drm.h>
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nv_object.xml.h"
36
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
41
42 #define THREADS_IN_WARP 32
43
44 static boolean
45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
46 enum pipe_format format,
47 enum pipe_texture_target target,
48 unsigned sample_count,
49 unsigned bindings)
50 {
51 if (sample_count > 8)
52 return false;
53 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
54 return false;
55 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
56 return false;
57
58 if (!util_format_is_supported(format, bindings))
59 return false;
60
61 switch (format) {
62 case PIPE_FORMAT_Z16_UNORM:
63 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
64 return false;
65 break;
66 default:
67 break;
68 }
69
70 /* transfers & shared are always supported */
71 bindings &= ~(PIPE_BIND_TRANSFER_READ |
72 PIPE_BIND_TRANSFER_WRITE |
73 PIPE_BIND_SHARED);
74
75 return (nv50_format_table[format].usage & bindings) == bindings;
76 }
77
78 static int
79 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
80 {
81 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
82 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
83
84 switch (param) {
85 /* non-boolean caps */
86 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
87 return 14;
88 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
89 return 12;
90 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
91 return 14;
92 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
93 return 512;
94 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
95 case PIPE_CAP_MIN_TEXEL_OFFSET:
96 return -8;
97 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
98 case PIPE_CAP_MAX_TEXEL_OFFSET:
99 return 7;
100 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
101 return 128 * 1024 * 1024;
102 case PIPE_CAP_GLSL_FEATURE_LEVEL:
103 return 330;
104 case PIPE_CAP_MAX_RENDER_TARGETS:
105 return 8;
106 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
107 return 1;
108 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
109 return 4;
110 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
111 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
112 return 64;
113 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
114 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
115 return 1024;
116 case PIPE_CAP_MAX_VERTEX_STREAMS:
117 return 1;
118 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
119 return 2048;
120 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
121 return 256;
122 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
123 return 1; /* 256 for binding as RT, but that's not possible in GL */
124 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
125 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
126 case PIPE_CAP_MAX_VIEWPORTS:
127 return NV50_MAX_VIEWPORTS;
128 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
129 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
130 case PIPE_CAP_ENDIANNESS:
131 return PIPE_ENDIAN_LITTLE;
132 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
133 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
134
135 /* supported caps */
136 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
137 case PIPE_CAP_TEXTURE_SWIZZLE:
138 case PIPE_CAP_TEXTURE_SHADOW_MAP:
139 case PIPE_CAP_NPOT_TEXTURES:
140 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
141 case PIPE_CAP_ANISOTROPIC_FILTER:
142 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
143 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
144 case PIPE_CAP_TWO_SIDED_STENCIL:
145 case PIPE_CAP_DEPTH_CLIP_DISABLE:
146 case PIPE_CAP_POINT_SPRITE:
147 case PIPE_CAP_SM3:
148 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
149 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
150 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
151 case PIPE_CAP_QUERY_TIMESTAMP:
152 case PIPE_CAP_QUERY_TIME_ELAPSED:
153 case PIPE_CAP_OCCLUSION_QUERY:
154 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
155 case PIPE_CAP_INDEP_BLEND_ENABLE:
156 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
157 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
158 case PIPE_CAP_PRIMITIVE_RESTART:
159 case PIPE_CAP_TGSI_INSTANCEID:
160 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
161 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
162 case PIPE_CAP_CONDITIONAL_RENDER:
163 case PIPE_CAP_TEXTURE_BARRIER:
164 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
165 case PIPE_CAP_START_INSTANCE:
166 case PIPE_CAP_USER_CONSTANT_BUFFERS:
167 case PIPE_CAP_USER_INDEX_BUFFERS:
168 case PIPE_CAP_USER_VERTEX_BUFFERS:
169 case PIPE_CAP_TEXTURE_MULTISAMPLE:
170 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
171 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
172 case PIPE_CAP_SAMPLER_VIEW_TARGET:
173 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
174 case PIPE_CAP_CLIP_HALFZ:
175 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
176 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
177 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
178 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
179 case PIPE_CAP_DEPTH_BOUNDS_TEST:
180 case PIPE_CAP_TGSI_TXQS:
181 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
182 case PIPE_CAP_SHAREABLE_SHADERS:
183 case PIPE_CAP_CLEAR_TEXTURE:
184 case PIPE_CAP_COMPUTE:
185 return 1;
186 case PIPE_CAP_SEAMLESS_CUBE_MAP:
187 return 1; /* class_3d >= NVA0_3D_CLASS; */
188 /* supported on nva0+ */
189 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
190 return class_3d >= NVA0_3D_CLASS;
191 /* supported on nva3+ */
192 case PIPE_CAP_CUBE_MAP_ARRAY:
193 case PIPE_CAP_INDEP_BLEND_FUNC:
194 case PIPE_CAP_TEXTURE_QUERY_LOD:
195 case PIPE_CAP_SAMPLE_SHADING:
196 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
197 return class_3d >= NVA3_3D_CLASS;
198
199 /* unsupported caps */
200 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
201 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
202 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
203 case PIPE_CAP_SHADER_STENCIL_EXPORT:
204 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
205 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
206 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
207 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
208 case PIPE_CAP_TGSI_TEXCOORD:
209 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
210 case PIPE_CAP_TEXTURE_GATHER_SM5:
211 case PIPE_CAP_FAKE_SW_MSAA:
212 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
213 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
214 case PIPE_CAP_DRAW_INDIRECT:
215 case PIPE_CAP_MULTI_DRAW_INDIRECT:
216 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
217 case PIPE_CAP_VERTEXID_NOBASE:
218 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
219 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
220 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
221 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
222 case PIPE_CAP_DRAW_PARAMETERS:
223 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
224 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
225 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
226 return 0;
227
228 case PIPE_CAP_VENDOR_ID:
229 return 0x10de;
230 case PIPE_CAP_DEVICE_ID: {
231 uint64_t device_id;
232 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
233 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
234 return -1;
235 }
236 return device_id;
237 }
238 case PIPE_CAP_ACCELERATED:
239 return 1;
240 case PIPE_CAP_VIDEO_MEMORY:
241 return dev->vram_size >> 20;
242 case PIPE_CAP_UMA:
243 return 0;
244 }
245
246 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
247 return 0;
248 }
249
250 static int
251 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
252 enum pipe_shader_cap param)
253 {
254 switch (shader) {
255 case PIPE_SHADER_VERTEX:
256 case PIPE_SHADER_GEOMETRY:
257 case PIPE_SHADER_FRAGMENT:
258 case PIPE_SHADER_COMPUTE:
259 break;
260 default:
261 return 0;
262 }
263
264 switch (param) {
265 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
266 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
267 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
268 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
269 return 16384;
270 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
271 return 4;
272 case PIPE_SHADER_CAP_MAX_INPUTS:
273 if (shader == PIPE_SHADER_VERTEX)
274 return 32;
275 return 15;
276 case PIPE_SHADER_CAP_MAX_OUTPUTS:
277 return 16;
278 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
279 return 65536;
280 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
281 return NV50_MAX_PIPE_CONSTBUFS;
282 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
283 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
284 return shader != PIPE_SHADER_FRAGMENT;
285 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
286 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
287 return 1;
288 case PIPE_SHADER_CAP_MAX_PREDS:
289 return 0;
290 case PIPE_SHADER_CAP_MAX_TEMPS:
291 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
292 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
293 return 1;
294 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
295 return 0;
296 case PIPE_SHADER_CAP_SUBROUTINES:
297 return 0; /* please inline, or provide function declarations */
298 case PIPE_SHADER_CAP_INTEGERS:
299 return 1;
300 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
301 /* The chip could handle more sampler views than samplers */
302 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
303 return MIN2(16, PIPE_MAX_SAMPLERS);
304 case PIPE_SHADER_CAP_DOUBLES:
305 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
306 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
307 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
308 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
309 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
310 return 0;
311 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
312 return 32;
313 default:
314 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
315 return 0;
316 }
317 }
318
319 static float
320 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
321 {
322 switch (param) {
323 case PIPE_CAPF_MAX_LINE_WIDTH:
324 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
325 return 10.0f;
326 case PIPE_CAPF_MAX_POINT_WIDTH:
327 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
328 return 64.0f;
329 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
330 return 16.0f;
331 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
332 return 4.0f;
333 case PIPE_CAPF_GUARD_BAND_LEFT:
334 case PIPE_CAPF_GUARD_BAND_TOP:
335 return 0.0f;
336 case PIPE_CAPF_GUARD_BAND_RIGHT:
337 case PIPE_CAPF_GUARD_BAND_BOTTOM:
338 return 0.0f; /* that or infinity */
339 }
340
341 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
342 return 0.0f;
343 }
344
345 static int
346 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
347 enum pipe_compute_cap param, void *data)
348 {
349 struct nv50_screen *screen = nv50_screen(pscreen);
350
351 #define RET(x) do { \
352 if (data) \
353 memcpy(data, x, sizeof(x)); \
354 return sizeof(x); \
355 } while (0)
356
357 switch (param) {
358 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
359 RET((uint64_t []) { 2 });
360 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
361 RET(((uint64_t []) { 65535, 65535 }));
362 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
363 RET(((uint64_t []) { 512, 512, 64 }));
364 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
365 RET((uint64_t []) { 512 });
366 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
367 RET((uint64_t []) { 1ULL << 32 });
368 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
369 RET((uint64_t []) { 16 << 10 });
370 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
371 RET((uint64_t []) { 16 << 10 });
372 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
373 RET((uint64_t []) { 4096 });
374 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
375 RET((uint32_t []) { 32 });
376 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
377 RET((uint64_t []) { 1ULL << 40 });
378 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
379 RET((uint32_t []) { 0 });
380 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
381 RET((uint32_t []) { screen->mp_count });
382 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
383 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
384 default:
385 return 0;
386 }
387
388 #undef RET
389 }
390
391 static void
392 nv50_screen_destroy(struct pipe_screen *pscreen)
393 {
394 struct nv50_screen *screen = nv50_screen(pscreen);
395
396 if (!nouveau_drm_screen_unref(&screen->base))
397 return;
398
399 if (screen->base.fence.current) {
400 struct nouveau_fence *current = NULL;
401
402 /* nouveau_fence_wait will create a new current fence, so wait on the
403 * _current_ one, and remove both.
404 */
405 nouveau_fence_ref(screen->base.fence.current, &current);
406 nouveau_fence_wait(current, NULL);
407 nouveau_fence_ref(NULL, &current);
408 nouveau_fence_ref(NULL, &screen->base.fence.current);
409 }
410 if (screen->base.pushbuf)
411 screen->base.pushbuf->user_priv = NULL;
412
413 if (screen->blitter)
414 nv50_blitter_destroy(screen);
415 if (screen->pm.prog) {
416 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
417 nv50_program_destroy(NULL, screen->pm.prog);
418 FREE(screen->pm.prog);
419 }
420
421 nouveau_bo_ref(NULL, &screen->code);
422 nouveau_bo_ref(NULL, &screen->tls_bo);
423 nouveau_bo_ref(NULL, &screen->stack_bo);
424 nouveau_bo_ref(NULL, &screen->txc);
425 nouveau_bo_ref(NULL, &screen->uniforms);
426 nouveau_bo_ref(NULL, &screen->fence.bo);
427
428 nouveau_heap_destroy(&screen->vp_code_heap);
429 nouveau_heap_destroy(&screen->gp_code_heap);
430 nouveau_heap_destroy(&screen->fp_code_heap);
431
432 FREE(screen->tic.entries);
433
434 nouveau_object_del(&screen->tesla);
435 nouveau_object_del(&screen->eng2d);
436 nouveau_object_del(&screen->m2mf);
437 nouveau_object_del(&screen->compute);
438 nouveau_object_del(&screen->sync);
439
440 nouveau_screen_fini(&screen->base);
441
442 FREE(screen);
443 }
444
445 static void
446 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
447 {
448 struct nv50_screen *screen = nv50_screen(pscreen);
449 struct nouveau_pushbuf *push = screen->base.pushbuf;
450
451 /* we need to do it after possible flush in MARK_RING */
452 *sequence = ++screen->base.fence.sequence;
453
454 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
455 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
456 PUSH_DATAh(push, screen->fence.bo->offset);
457 PUSH_DATA (push, screen->fence.bo->offset);
458 PUSH_DATA (push, *sequence);
459 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
460 NV50_3D_QUERY_GET_UNK4 |
461 NV50_3D_QUERY_GET_UNIT_CROP |
462 NV50_3D_QUERY_GET_TYPE_QUERY |
463 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
464 NV50_3D_QUERY_GET_SHORT);
465 }
466
467 static u32
468 nv50_screen_fence_update(struct pipe_screen *pscreen)
469 {
470 return nv50_screen(pscreen)->fence.map[0];
471 }
472
473 static void
474 nv50_screen_init_hwctx(struct nv50_screen *screen)
475 {
476 struct nouveau_pushbuf *push = screen->base.pushbuf;
477 struct nv04_fifo *fifo;
478 unsigned i;
479
480 fifo = (struct nv04_fifo *)screen->base.channel->data;
481
482 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
483 PUSH_DATA (push, screen->m2mf->handle);
484 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
485 PUSH_DATA (push, screen->sync->handle);
486 PUSH_DATA (push, fifo->vram);
487 PUSH_DATA (push, fifo->vram);
488
489 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
490 PUSH_DATA (push, screen->eng2d->handle);
491 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
492 PUSH_DATA (push, screen->sync->handle);
493 PUSH_DATA (push, fifo->vram);
494 PUSH_DATA (push, fifo->vram);
495 PUSH_DATA (push, fifo->vram);
496 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
497 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
498 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
499 PUSH_DATA (push, 0);
500 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
501 PUSH_DATA (push, 0);
502 BEGIN_NV04(push, SUBC_2D(0x0888), 1);
503 PUSH_DATA (push, 1);
504 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
505 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
506
507 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
508 PUSH_DATA (push, screen->tesla->handle);
509
510 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
511 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
512
513 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
514 PUSH_DATA (push, screen->sync->handle);
515 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
516 for (i = 0; i < 11; ++i)
517 PUSH_DATA(push, fifo->vram);
518 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
519 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
520 PUSH_DATA(push, fifo->vram);
521
522 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
523 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
524 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
525 PUSH_DATA (push, 0xf);
526
527 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
528 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
529 PUSH_DATA (push, 0x18);
530 }
531
532 BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
533 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
534
535 BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
536 for (i = 0; i < 8; ++i)
537 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
538
539 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
540 PUSH_DATA (push, 1);
541
542 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
543 PUSH_DATA (push, 0);
544 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
545 PUSH_DATA (push, 0);
546 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
547 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
548 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
549 PUSH_DATA (push, 0);
550 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
551 PUSH_DATA (push, 1);
552 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
553 PUSH_DATA (push, 1);
554
555 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
556 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
557 PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
558 }
559
560 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
561 PUSH_DATA (push, 0);
562 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
563 PUSH_DATA (push, 0);
564 PUSH_DATA (push, 0);
565 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
566 PUSH_DATA (push, 0x3f);
567
568 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
569 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
570 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
571
572 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
573 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
574 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
575
576 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
577 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
578 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
579
580 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
581 PUSH_DATAh(push, screen->tls_bo->offset);
582 PUSH_DATA (push, screen->tls_bo->offset);
583 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
584
585 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
586 PUSH_DATAh(push, screen->stack_bo->offset);
587 PUSH_DATA (push, screen->stack_bo->offset);
588 PUSH_DATA (push, 4);
589
590 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
591 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
592 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
593 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
594
595 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
596 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
597 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
598 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
599
600 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
601 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
602 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
603 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
604
605 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
606 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
607 PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
608 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
609
610 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
611 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
612 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
613 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
614
615 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
616 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
617 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
618 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
619 PUSH_DATAf(push, 0.0f);
620 PUSH_DATAf(push, 0.0f);
621 PUSH_DATAf(push, 0.0f);
622 PUSH_DATAf(push, 0.0f);
623 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
624 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
625 PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
626
627 nv50_upload_ms_info(push);
628
629 /* max TIC (bits 4:8) & TSC bindings, per program type */
630 for (i = 0; i < 3; ++i) {
631 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
632 PUSH_DATA (push, 0x54);
633 }
634
635 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
636 PUSH_DATAh(push, screen->txc->offset);
637 PUSH_DATA (push, screen->txc->offset);
638 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
639
640 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
641 PUSH_DATAh(push, screen->txc->offset + 65536);
642 PUSH_DATA (push, screen->txc->offset + 65536);
643 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
644
645 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
646 PUSH_DATA (push, 0);
647
648 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
649 PUSH_DATA (push, 0);
650 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
651 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
652 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
653 for (i = 0; i < 8 * 2; ++i)
654 PUSH_DATA(push, 0);
655 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
656 PUSH_DATA (push, 0);
657
658 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
659 PUSH_DATA (push, 1);
660 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
661 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
662 PUSH_DATAf(push, 0.0f);
663 PUSH_DATAf(push, 1.0f);
664 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
665 PUSH_DATA (push, 8192 << 16);
666 PUSH_DATA (push, 8192 << 16);
667 }
668
669 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
670 #ifdef NV50_SCISSORS_CLIPPING
671 PUSH_DATA (push, 0x0000);
672 #else
673 PUSH_DATA (push, 0x1080);
674 #endif
675
676 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
677 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
678
679 /* We use scissors instead of exact view volume clipping,
680 * so they're always enabled.
681 */
682 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
683 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
684 PUSH_DATA (push, 1);
685 PUSH_DATA (push, 8192 << 16);
686 PUSH_DATA (push, 8192 << 16);
687 }
688
689 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
690 PUSH_DATA (push, 1);
691 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
692 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
693 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
694 PUSH_DATA (push, 0x11111111);
695 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
696 PUSH_DATA (push, 1);
697
698 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
699 PUSH_DATA (push, 0);
700 if (screen->base.class_3d >= NV84_3D_CLASS) {
701 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
702 PUSH_DATA (push, 0);
703 }
704
705 PUSH_KICK (push);
706 }
707
708 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
709 uint64_t *tls_size)
710 {
711 struct nouveau_device *dev = screen->base.device;
712 int ret;
713
714 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
715 ONE_TEMP_SIZE;
716 if (nouveau_mesa_debug)
717 debug_printf("allocating space for %u temps\n",
718 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
719 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
720 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
721
722 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
723 *tls_size, NULL, &screen->tls_bo);
724 if (ret) {
725 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
726 return ret;
727 }
728
729 return 0;
730 }
731
732 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
733 {
734 struct nouveau_pushbuf *push = screen->base.pushbuf;
735 int ret;
736 uint64_t tls_size;
737
738 if (tls_space < screen->cur_tls_space)
739 return 0;
740 if (tls_space > screen->max_tls_space) {
741 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
742 * LOCAL_WARPS_NO_CLAMP) */
743 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
744 (unsigned)(tls_space / ONE_TEMP_SIZE),
745 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
746 return -ENOMEM;
747 }
748
749 nouveau_bo_ref(NULL, &screen->tls_bo);
750 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
751 if (ret)
752 return ret;
753
754 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
755 PUSH_DATAh(push, screen->tls_bo->offset);
756 PUSH_DATA (push, screen->tls_bo->offset);
757 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
758
759 return 1;
760 }
761
762 struct nouveau_screen *
763 nv50_screen_create(struct nouveau_device *dev)
764 {
765 struct nv50_screen *screen;
766 struct pipe_screen *pscreen;
767 struct nouveau_object *chan;
768 uint64_t value;
769 uint32_t tesla_class;
770 unsigned stack_size;
771 int ret;
772
773 screen = CALLOC_STRUCT(nv50_screen);
774 if (!screen)
775 return NULL;
776 pscreen = &screen->base.base;
777 pscreen->destroy = nv50_screen_destroy;
778
779 ret = nouveau_screen_init(&screen->base, dev);
780 if (ret) {
781 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
782 goto fail;
783 }
784
785 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
786 * admit them to VRAM.
787 */
788 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
789 PIPE_BIND_VERTEX_BUFFER;
790 screen->base.sysmem_bindings |=
791 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
792
793 screen->base.pushbuf->user_priv = screen;
794 screen->base.pushbuf->rsvd_kick = 5;
795
796 chan = screen->base.channel;
797
798 pscreen->context_create = nv50_create;
799 pscreen->is_format_supported = nv50_screen_is_format_supported;
800 pscreen->get_param = nv50_screen_get_param;
801 pscreen->get_shader_param = nv50_screen_get_shader_param;
802 pscreen->get_paramf = nv50_screen_get_paramf;
803 pscreen->get_compute_param = nv50_screen_get_compute_param;
804 pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
805 pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
806
807 nv50_screen_init_resource_functions(pscreen);
808
809 if (screen->base.device->chipset < 0x84 ||
810 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
811 /* PMPEG */
812 nouveau_screen_init_vdec(&screen->base);
813 } else if (screen->base.device->chipset < 0x98 ||
814 screen->base.device->chipset == 0xa0) {
815 /* VP2 */
816 screen->base.base.get_video_param = nv84_screen_get_video_param;
817 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
818 } else {
819 /* VP3/4 */
820 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
821 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
822 }
823
824 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
825 NULL, &screen->fence.bo);
826 if (ret) {
827 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
828 goto fail;
829 }
830
831 nouveau_bo_map(screen->fence.bo, 0, NULL);
832 screen->fence.map = screen->fence.bo->map;
833 screen->base.fence.emit = nv50_screen_fence_emit;
834 screen->base.fence.update = nv50_screen_fence_update;
835
836 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
837 &(struct nv04_notify){ .length = 32 },
838 sizeof(struct nv04_notify), &screen->sync);
839 if (ret) {
840 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
841 goto fail;
842 }
843
844 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
845 NULL, 0, &screen->m2mf);
846 if (ret) {
847 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
848 goto fail;
849 }
850
851 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
852 NULL, 0, &screen->eng2d);
853 if (ret) {
854 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
855 goto fail;
856 }
857
858 switch (dev->chipset & 0xf0) {
859 case 0x50:
860 tesla_class = NV50_3D_CLASS;
861 break;
862 case 0x80:
863 case 0x90:
864 tesla_class = NV84_3D_CLASS;
865 break;
866 case 0xa0:
867 switch (dev->chipset) {
868 case 0xa0:
869 case 0xaa:
870 case 0xac:
871 tesla_class = NVA0_3D_CLASS;
872 break;
873 case 0xaf:
874 tesla_class = NVAF_3D_CLASS;
875 break;
876 default:
877 tesla_class = NVA3_3D_CLASS;
878 break;
879 }
880 break;
881 default:
882 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
883 goto fail;
884 }
885 screen->base.class_3d = tesla_class;
886
887 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
888 NULL, 0, &screen->tesla);
889 if (ret) {
890 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
891 goto fail;
892 }
893
894 /* This over-allocates by a page. The GP, which would execute at the end of
895 * the last page, would trigger faults. The going theory is that it
896 * prefetches up to a certain amount.
897 */
898 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
899 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
900 NULL, &screen->code);
901 if (ret) {
902 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
903 goto fail;
904 }
905
906 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
907 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
908 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
909
910 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
911
912 screen->TPs = util_bitcount(value & 0xffff);
913 screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
914
915 screen->mp_count = screen->TPs * screen->MPsInTP;
916
917 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
918 STACK_WARPS_ALLOC * 64 * 8;
919
920 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
921 &screen->stack_bo);
922 if (ret) {
923 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
924 goto fail;
925 }
926
927 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
928 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
929 ONE_TEMP_SIZE;
930 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
931 screen->max_tls_space /= 2; /* half of vram */
932
933 /* hw can address max 64 KiB */
934 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
935
936 uint64_t tls_size;
937 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
938 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
939 if (ret)
940 goto fail;
941
942 if (nouveau_mesa_debug)
943 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
944 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
945
946 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
947 &screen->uniforms);
948 if (ret) {
949 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
950 goto fail;
951 }
952
953 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
954 &screen->txc);
955 if (ret) {
956 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
957 goto fail;
958 }
959
960 screen->tic.entries = CALLOC(4096, sizeof(void *));
961 screen->tsc.entries = screen->tic.entries + 2048;
962
963 if (!nv50_blitter_create(screen))
964 goto fail;
965
966 nv50_screen_init_hwctx(screen);
967
968 ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
969 if (ret) {
970 NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
971 goto fail;
972 }
973
974 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
975
976 return &screen->base;
977
978 fail:
979 screen->base.base.context_create = NULL;
980 return &screen->base;
981 }
982
983 int
984 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
985 {
986 int i = screen->tic.next;
987
988 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
989 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
990
991 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
992
993 if (screen->tic.entries[i])
994 nv50_tic_entry(screen->tic.entries[i])->id = -1;
995
996 screen->tic.entries[i] = entry;
997 return i;
998 }
999
1000 int
1001 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1002 {
1003 int i = screen->tsc.next;
1004
1005 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1006 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1007
1008 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1009
1010 if (screen->tsc.entries[i])
1011 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1012
1013 screen->tsc.entries[i] = entry;
1014 return i;
1015 }