src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50/nv50_context.h"
  28 #include "nv50/nv50_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nv_object.xml.h"
  33 #include <errno.h>
  34
  35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  37 #endif
  38
  39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  40 #define LOCAL_WARPS_ALLOC 32
  41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  42 #define STACK_WARPS_ALLOC 32
  43
  44 #define THREADS_IN_WARP 32
  45
  46 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  47
  48 static boolean
  49 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  50                                 enum pipe_format format,
  51                                 enum pipe_texture_target target,
  52                                 unsigned sample_count,
  53                                 unsigned bindings)
  54 {
  55    if (sample_count > 8)
  56       return FALSE;
  57    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  58       return FALSE;
  59    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  60       return FALSE;
  61
  62    if (!util_format_is_supported(format, bindings))
  63       return FALSE;
  64
  65    switch (format) {
  66    case PIPE_FORMAT_Z16_UNORM:
  67       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  68          return FALSE;
  69       break;
  70    default:
  71       break;
  72    }
  73
  74    /* transfers & shared are always supported */
  75    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  76                  PIPE_BIND_TRANSFER_WRITE |
  77                  PIPE_BIND_SHARED);
  78
  79    return (nv50_format_table[format].usage & bindings) == bindings;
  80 }
  81
  82 static int
  83 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  84 {
  85    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  86
  87    switch (param) {
  88    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  89       return 14;
  90    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  91       return 12;
  92    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  93       return 14;
  94    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  95       return 512;
  96    case PIPE_CAP_MIN_TEXEL_OFFSET:
  97       return -8;
  98    case PIPE_CAP_MAX_TEXEL_OFFSET:
  99       return 7;
 100    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 101    case PIPE_CAP_TEXTURE_SWIZZLE:
 102    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 103    case PIPE_CAP_NPOT_TEXTURES:
 104    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 105    case PIPE_CAP_ANISOTROPIC_FILTER:
 106    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 107       return 1;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 65536;
 110    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 111       return 1; /* nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS; */
 112    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 113       return 0;
 114    case PIPE_CAP_CUBE_MAP_ARRAY:
 115       return 0;
 116       /*
 117       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 118       */
 119    case PIPE_CAP_TWO_SIDED_STENCIL:
 120    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 121    case PIPE_CAP_POINT_SPRITE:
 122       return 1;
 123    case PIPE_CAP_SM3:
 124       return 1;
 125    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 126       return 330;
 127    case PIPE_CAP_MAX_RENDER_TARGETS:
 128       return 8;
 129    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 130       return 1;
 131    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 132    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 133    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 134       return 1;
 135    case PIPE_CAP_QUERY_TIMESTAMP:
 136    case PIPE_CAP_QUERY_TIME_ELAPSED:
 137    case PIPE_CAP_OCCLUSION_QUERY:
 138       return 1;
 139    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 140       return 4;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 142    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 143       return 64;
 144    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 145    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 146       return 1024;
 147    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 148       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 149    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 150    case PIPE_CAP_INDEP_BLEND_ENABLE:
 151       return 1;
 152    case PIPE_CAP_INDEP_BLEND_FUNC:
 153       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 154    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 155    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 156       return 1;
 157    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 158    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 159       return 0;
 160    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 161       return 0;
 162    case PIPE_CAP_PRIMITIVE_RESTART:
 163    case PIPE_CAP_TGSI_INSTANCEID:
 164    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 165    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 166    case PIPE_CAP_CONDITIONAL_RENDER:
 167    case PIPE_CAP_TEXTURE_BARRIER:
 168    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 169    case PIPE_CAP_START_INSTANCE:
 170       return 1;
 171    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 172       return 0; /* state trackers will know better */
 173    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 174    case PIPE_CAP_USER_INDEX_BUFFERS:
 175    case PIPE_CAP_USER_VERTEX_BUFFERS:
 176       return 1;
 177    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 178       return 256;
 179    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 180       return 1; /* 256 for binding as RT, but that's not possible in GL */
 181    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 182       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 183    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 184    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 185    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 186    case PIPE_CAP_TGSI_TEXCOORD:
 187       return 0;
 188    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 189       return 1;
 190    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 191       return 1;
 192    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 193       return 0;
 194    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 195       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 196    case PIPE_CAP_ENDIANNESS:
 197       return PIPE_ENDIAN_LITTLE;
 198    case PIPE_CAP_TGSI_VS_LAYER:
 199    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 200    case PIPE_CAP_TEXTURE_GATHER_SM5:
 201       return 0;
 202    case PIPE_CAP_MAX_VIEWPORTS:
 203       return NV50_MAX_VIEWPORTS;
 204    default:
 205       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 206       return 0;
 207    }
 208 }
 209
 210 static int
 211 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 212                              enum pipe_shader_cap param)
 213 {
 214    switch (shader) {
 215    case PIPE_SHADER_VERTEX:
 216    case PIPE_SHADER_GEOMETRY:
 217    case PIPE_SHADER_FRAGMENT:
 218       break;
 219    default:
 220       return 0;
 221    }
 222
 223    switch (param) {
 224    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 225    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 226    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 227    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 228       return 16384;
 229    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 230       return 4;
 231    case PIPE_SHADER_CAP_MAX_INPUTS:
 232       if (shader == PIPE_SHADER_VERTEX)
 233          return 32;
 234       return 15;
 235    case PIPE_SHADER_CAP_MAX_CONSTS:
 236       return 65536 / 16;
 237    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 238       return NV50_MAX_PIPE_CONSTBUFS;
 239    case PIPE_SHADER_CAP_MAX_ADDRS:
 240       return 1;
 241    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 242    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 243       return shader != PIPE_SHADER_FRAGMENT;
 244    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 245    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 246       return 1;
 247    case PIPE_SHADER_CAP_MAX_PREDS:
 248       return 0;
 249    case PIPE_SHADER_CAP_MAX_TEMPS:
 250       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 251    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 252       return 1;
 253    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 254       return 0;
 255    case PIPE_SHADER_CAP_SUBROUTINES:
 256       return 0; /* please inline, or provide function declarations */
 257    case PIPE_SHADER_CAP_INTEGERS:
 258       return 1;
 259    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 260       /* The chip could handle more sampler views than samplers */
 261    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 262       return MIN2(32, PIPE_MAX_SAMPLERS);
 263    default:
 264       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 265       return 0;
 266    }
 267 }
 268
 269 static float
 270 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 271 {
 272    switch (param) {
 273    case PIPE_CAPF_MAX_LINE_WIDTH:
 274    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 275       return 10.0f;
 276    case PIPE_CAPF_MAX_POINT_WIDTH:
 277    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 278       return 64.0f;
 279    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 280       return 16.0f;
 281    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 282       return 4.0f;
 283    default:
 284       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 285       return 0.0f;
 286    }
 287 }
 288
 289 static void
 290 nv50_screen_destroy(struct pipe_screen *pscreen)
 291 {
 292    struct nv50_screen *screen = nv50_screen(pscreen);
 293
 294    if (!nouveau_drm_screen_unref(&screen->base))
 295       return;
 296
 297    if (screen->base.fence.current) {
 298       nouveau_fence_wait(screen->base.fence.current);
 299       nouveau_fence_ref (NULL, &screen->base.fence.current);
 300    }
 301    if (screen->base.pushbuf)
 302       screen->base.pushbuf->user_priv = NULL;
 303
 304    if (screen->blitter)
 305       nv50_blitter_destroy(screen);
 306
 307    nouveau_bo_ref(NULL, &screen->code);
 308    nouveau_bo_ref(NULL, &screen->tls_bo);
 309    nouveau_bo_ref(NULL, &screen->stack_bo);
 310    nouveau_bo_ref(NULL, &screen->txc);
 311    nouveau_bo_ref(NULL, &screen->uniforms);
 312    nouveau_bo_ref(NULL, &screen->fence.bo);
 313
 314    nouveau_heap_destroy(&screen->vp_code_heap);
 315    nouveau_heap_destroy(&screen->gp_code_heap);
 316    nouveau_heap_destroy(&screen->fp_code_heap);
 317
 318    FREE(screen->tic.entries);
 319
 320    nouveau_object_del(&screen->tesla);
 321    nouveau_object_del(&screen->eng2d);
 322    nouveau_object_del(&screen->m2mf);
 323    nouveau_object_del(&screen->sync);
 324
 325    nouveau_screen_fini(&screen->base);
 326
 327    FREE(screen);
 328 }
 329
 330 static void
 331 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 332 {
 333    struct nv50_screen *screen = nv50_screen(pscreen);
 334    struct nouveau_pushbuf *push = screen->base.pushbuf;
 335
 336    /* we need to do it after possible flush in MARK_RING */
 337    *sequence = ++screen->base.fence.sequence;
 338
 339    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 340    PUSH_DATAh(push, screen->fence.bo->offset);
 341    PUSH_DATA (push, screen->fence.bo->offset);
 342    PUSH_DATA (push, *sequence);
 343    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 344                     NV50_3D_QUERY_GET_UNK4 |
 345                     NV50_3D_QUERY_GET_UNIT_CROP |
 346                     NV50_3D_QUERY_GET_TYPE_QUERY |
 347                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 348                     NV50_3D_QUERY_GET_SHORT);
 349 }
 350
 351 static u32
 352 nv50_screen_fence_update(struct pipe_screen *pscreen)
 353 {
 354    return nv50_screen(pscreen)->fence.map[0];
 355 }
 356
 357 static void
 358 nv50_screen_init_hwctx(struct nv50_screen *screen)
 359 {
 360    struct nouveau_pushbuf *push = screen->base.pushbuf;
 361    struct nv04_fifo *fifo;
 362    unsigned i;
 363
 364    fifo = (struct nv04_fifo *)screen->base.channel->data;
 365
 366    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 367    PUSH_DATA (push, screen->m2mf->handle);
 368    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 369    PUSH_DATA (push, screen->sync->handle);
 370    PUSH_DATA (push, fifo->vram);
 371    PUSH_DATA (push, fifo->vram);
 372
 373    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 374    PUSH_DATA (push, screen->eng2d->handle);
 375    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 376    PUSH_DATA (push, screen->sync->handle);
 377    PUSH_DATA (push, fifo->vram);
 378    PUSH_DATA (push, fifo->vram);
 379    PUSH_DATA (push, fifo->vram);
 380    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 381    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 382    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 383    PUSH_DATA (push, 0);
 384    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 385    PUSH_DATA (push, 0);
 386    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 387    PUSH_DATA (push, 1);
 388
 389    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 390    PUSH_DATA (push, screen->tesla->handle);
 391
 392    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 393    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 394
 395    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 396    PUSH_DATA (push, screen->sync->handle);
 397    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 398    for (i = 0; i < 11; ++i)
 399       PUSH_DATA(push, fifo->vram);
 400    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 401    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 402       PUSH_DATA(push, fifo->vram);
 403
 404    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 405    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 406    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 407    PUSH_DATA (push, 0xf);
 408
 409    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 410       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 411       PUSH_DATA (push, 0x18);
 412    }
 413
 414    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 415    PUSH_DATA (push, 1);
 416
 417    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 418    PUSH_DATA (push, 0);
 419    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 420    PUSH_DATA (push, 0);
 421    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 422    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 423    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 424    PUSH_DATA (push, 0);
 425    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 426    PUSH_DATA (push, 0);
 427    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 428    PUSH_DATA (push, 1);
 429
 430    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 431       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 432       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 433    }
 434
 435    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 436    PUSH_DATA (push, 0);
 437    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 438    PUSH_DATA (push, 0);
 439    PUSH_DATA (push, 0);
 440    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 441    PUSH_DATA (push, 0x3f);
 442
 443    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 444    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 445    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 446
 447    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 448    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 449    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 450
 451    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 452    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 453    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 454
 455    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 456    PUSH_DATAh(push, screen->tls_bo->offset);
 457    PUSH_DATA (push, screen->tls_bo->offset);
 458    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 459
 460    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 461    PUSH_DATAh(push, screen->stack_bo->offset);
 462    PUSH_DATA (push, screen->stack_bo->offset);
 463    PUSH_DATA (push, 4);
 464
 465    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 466    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 467    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 468    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 469
 470    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 471    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 472    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 473    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 474
 475    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 476    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 477    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 478    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 479
 480    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 481    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 482    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 483    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 484
 485    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 486    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 487    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 488    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 489
 490    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 491    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 492    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 493    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 494    PUSH_DATAf(push, 0.0f);
 495    PUSH_DATAf(push, 0.0f);
 496    PUSH_DATAf(push, 0.0f);
 497    PUSH_DATAf(push, 0.0f);
 498    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 499    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 500    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 501
 502    nv50_upload_ms_info(push);
 503
 504    /* max TIC (bits 4:8) & TSC bindings, per program type */
 505    for (i = 0; i < 3; ++i) {
 506       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 507       PUSH_DATA (push, 0x54);
 508    }
 509
 510    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 511    PUSH_DATAh(push, screen->txc->offset);
 512    PUSH_DATA (push, screen->txc->offset);
 513    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 514
 515    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 516    PUSH_DATAh(push, screen->txc->offset + 65536);
 517    PUSH_DATA (push, screen->txc->offset + 65536);
 518    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 519
 520    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 521    PUSH_DATA (push, 0);
 522
 523    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 524    PUSH_DATA (push, 0);
 525    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 526    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 527    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 528    for (i = 0; i < 8 * 2; ++i)
 529       PUSH_DATA(push, 0);
 530    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 531    PUSH_DATA (push, 0);
 532
 533    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 534    PUSH_DATA (push, 1);
 535    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 536       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 537       PUSH_DATAf(push, 0.0f);
 538       PUSH_DATAf(push, 1.0f);
 539       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 540       PUSH_DATA (push, 8192 << 16);
 541       PUSH_DATA (push, 8192 << 16);
 542    }
 543
 544    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 545 #ifdef NV50_SCISSORS_CLIPPING
 546    PUSH_DATA (push, 0x0000);
 547 #else
 548    PUSH_DATA (push, 0x1080);
 549 #endif
 550
 551    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 552    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 553
 554    /* We use scissors instead of exact view volume clipping,
 555     * so they're always enabled.
 556     */
 557    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 558       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 559       PUSH_DATA (push, 1);
 560       PUSH_DATA (push, 8192 << 16);
 561       PUSH_DATA (push, 8192 << 16);
 562    }
 563
 564    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 565    PUSH_DATA (push, 1);
 566    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 567    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 568    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 569    PUSH_DATA (push, 0x11111111);
 570    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 571    PUSH_DATA (push, 1);
 572
 573    PUSH_KICK (push);
 574 }
 575
 576 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 577       uint64_t *tls_size)
 578 {
 579    struct nouveau_device *dev = screen->base.device;
 580    int ret;
 581
 582    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 583          ONE_TEMP_SIZE;
 584    if (nouveau_mesa_debug)
 585       debug_printf("allocating space for %u temps\n",
 586             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 587    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 588          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 589
 590    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 591                         *tls_size, NULL, &screen->tls_bo);
 592    if (ret) {
 593       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 594       return ret;
 595    }
 596
 597    return 0;
 598 }
 599
 600 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 601 {
 602    struct nouveau_pushbuf *push = screen->base.pushbuf;
 603    int ret;
 604    uint64_t tls_size;
 605
 606    if (tls_space < screen->cur_tls_space)
 607       return 0;
 608    if (tls_space > screen->max_tls_space) {
 609       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 610        * LOCAL_WARPS_NO_CLAMP) */
 611       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 612             (unsigned)(tls_space / ONE_TEMP_SIZE),
 613             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 614       return -ENOMEM;
 615    }
 616
 617    nouveau_bo_ref(NULL, &screen->tls_bo);
 618    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 619    if (ret)
 620       return ret;
 621
 622    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 623    PUSH_DATAh(push, screen->tls_bo->offset);
 624    PUSH_DATA (push, screen->tls_bo->offset);
 625    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 626
 627    return 1;
 628 }
 629
 630 struct pipe_screen *
 631 nv50_screen_create(struct nouveau_device *dev)
 632 {
 633    struct nv50_screen *screen;
 634    struct pipe_screen *pscreen;
 635    struct nouveau_object *chan;
 636    uint64_t value;
 637    uint32_t tesla_class;
 638    unsigned stack_size;
 639    int ret;
 640
 641    screen = CALLOC_STRUCT(nv50_screen);
 642    if (!screen)
 643       return NULL;
 644    pscreen = &screen->base.base;
 645
 646    ret = nouveau_screen_init(&screen->base, dev);
 647    if (ret) {
 648       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 649       goto fail;
 650    }
 651
 652    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 653     *  admit them to VRAM.
 654     */
 655    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 656       PIPE_BIND_VERTEX_BUFFER;
 657    screen->base.sysmem_bindings |=
 658       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 659
 660    screen->base.pushbuf->user_priv = screen;
 661    screen->base.pushbuf->rsvd_kick = 5;
 662
 663    chan = screen->base.channel;
 664
 665    pscreen->destroy = nv50_screen_destroy;
 666    pscreen->context_create = nv50_create;
 667    pscreen->is_format_supported = nv50_screen_is_format_supported;
 668    pscreen->get_param = nv50_screen_get_param;
 669    pscreen->get_shader_param = nv50_screen_get_shader_param;
 670    pscreen->get_paramf = nv50_screen_get_paramf;
 671
 672    nv50_screen_init_resource_functions(pscreen);
 673
 674    if (screen->base.device->chipset < 0x84 ||
 675        debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
 676       /* PMPEG */
 677       nouveau_screen_init_vdec(&screen->base);
 678    } else if (screen->base.device->chipset < 0x98 ||
 679               screen->base.device->chipset == 0xa0) {
 680       /* VP2 */
 681       screen->base.base.get_video_param = nv84_screen_get_video_param;
 682       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 683    } else {
 684       /* VP3/4 */
 685       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 686       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 687    }
 688
 689    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 690                         NULL, &screen->fence.bo);
 691    if (ret) {
 692       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 693       goto fail;
 694    }
 695
 696    nouveau_bo_map(screen->fence.bo, 0, NULL);
 697    screen->fence.map = screen->fence.bo->map;
 698    screen->base.fence.emit = nv50_screen_fence_emit;
 699    screen->base.fence.update = nv50_screen_fence_update;
 700
 701    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 702                             &(struct nv04_notify){ .length = 32 },
 703                             sizeof(struct nv04_notify), &screen->sync);
 704    if (ret) {
 705       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 706       goto fail;
 707    }
 708
 709    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 710                             NULL, 0, &screen->m2mf);
 711    if (ret) {
 712       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 713       goto fail;
 714    }
 715
 716    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 717                             NULL, 0, &screen->eng2d);
 718    if (ret) {
 719       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 720       goto fail;
 721    }
 722
 723    switch (dev->chipset & 0xf0) {
 724    case 0x50:
 725       tesla_class = NV50_3D_CLASS;
 726       break;
 727    case 0x80:
 728    case 0x90:
 729       tesla_class = NV84_3D_CLASS;
 730       break;
 731    case 0xa0:
 732       switch (dev->chipset) {
 733       case 0xa0:
 734       case 0xaa:
 735       case 0xac:
 736          tesla_class = NVA0_3D_CLASS;
 737          break;
 738       case 0xaf:
 739          tesla_class = NVAF_3D_CLASS;
 740          break;
 741       default:
 742          tesla_class = NVA3_3D_CLASS;
 743          break;
 744       }
 745       break;
 746    default:
 747       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 748       goto fail;
 749    }
 750    screen->base.class_3d = tesla_class;
 751
 752    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 753                             NULL, 0, &screen->tesla);
 754    if (ret) {
 755       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 756       goto fail;
 757    }
 758
 759    /* This over-allocates by a page. The GP, which would execute at the end of
 760     * the last page, would trigger faults. The going theory is that it
 761     * prefetches up to a certain amount.
 762     */
 763    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 764                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 765                         NULL, &screen->code);
 766    if (ret) {
 767       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 768       goto fail;
 769    }
 770
 771    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 772    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 773    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 774
 775    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 776
 777    screen->TPs = util_bitcount(value & 0xffff);
 778    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 779
 780    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 781          STACK_WARPS_ALLOC * 64 * 8;
 782
 783    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 784                         &screen->stack_bo);
 785    if (ret) {
 786       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 787       goto fail;
 788    }
 789
 790    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 791          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 792          ONE_TEMP_SIZE;
 793    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 794    screen->max_tls_space /= 2; /* half of vram */
 795
 796    /* hw can address max 64 KiB */
 797    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 798
 799    uint64_t tls_size;
 800    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 801    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 802    if (ret)
 803       goto fail;
 804
 805    if (nouveau_mesa_debug)
 806       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 807             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 808
 809    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 810                         &screen->uniforms);
 811    if (ret) {
 812       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 813       goto fail;
 814    }
 815
 816    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 817                         &screen->txc);
 818    if (ret) {
 819       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 820       goto fail;
 821    }
 822
 823    screen->tic.entries = CALLOC(4096, sizeof(void *));
 824    screen->tsc.entries = screen->tic.entries + 2048;
 825
 826    if (!nv50_blitter_create(screen))
 827       goto fail;
 828
 829    nv50_screen_init_hwctx(screen);
 830
 831    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 832
 833    return pscreen;
 834
 835 fail:
 836    nv50_screen_destroy(pscreen);
 837    return NULL;
 838 }
 839
 840 int
 841 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 842 {
 843    int i = screen->tic.next;
 844
 845    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 846       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 847
 848    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 849
 850    if (screen->tic.entries[i])
 851       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 852
 853    screen->tic.entries[i] = entry;
 854    return i;
 855 }
 856
 857 int
 858 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 859 {
 860    int i = screen->tsc.next;
 861
 862    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 863       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 864
 865    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 866
 867    if (screen->tsc.entries[i])
 868       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 869
 870    screen->tsc.entries[i] = entry;
 871    return i;
 872 }