src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* shared is always supported */
  79    bindings &= ~(PIPE_BIND_LINEAR |
  80                  PIPE_BIND_SHARED);
  81
  82    return (( nv50_format_table[format].usage |
  83             nv50_vertex_format[format].usage) & bindings) == bindings;
  84 }
  85
  86 static int
  87 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  88 {
  89    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  90    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  91
  92    switch (param) {
  93    /* non-boolean caps */
  94    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  97       return 12;
  98    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  99       return 14;
 100    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 101       return 512;
 102    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 103    case PIPE_CAP_MIN_TEXEL_OFFSET:
 104       return -8;
 105    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MAX_TEXEL_OFFSET:
 107       return 7;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 128 * 1024 * 1024;
 110    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 111       return 330;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 113       return 140;
 114    case PIPE_CAP_MAX_RENDER_TARGETS:
 115       return 8;
 116    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 117       return 1;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 119       return 4;
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122       return 64;
 123    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 124    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 125       return 1024;
 126    case PIPE_CAP_MAX_VERTEX_STREAMS:
 127       return 1;
 128    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 129       return 2048;
 130    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 131       return 256;
 132    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 133       return 16; /* 256 for binding as RT, but that's not possible in GL */
 134    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 135       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 136    case PIPE_CAP_MAX_VIEWPORTS:
 137       return NV50_MAX_VIEWPORTS;
 138    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 139       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 140    case PIPE_CAP_ENDIANNESS:
 141       return PIPE_ENDIAN_LITTLE;
 142    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 143       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 144    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 145       return NV50_MAX_WINDOW_RECTANGLES;
 146
 147    /* supported caps */
 148    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 149    case PIPE_CAP_TEXTURE_SWIZZLE:
 150    case PIPE_CAP_NPOT_TEXTURES:
 151    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 152    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 153    case PIPE_CAP_ANISOTROPIC_FILTER:
 154    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 155    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 156    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 157    case PIPE_CAP_POINT_SPRITE:
 158    case PIPE_CAP_SM3:
 159    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 160    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 161    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 162    case PIPE_CAP_QUERY_TIMESTAMP:
 163    case PIPE_CAP_QUERY_TIME_ELAPSED:
 164    case PIPE_CAP_OCCLUSION_QUERY:
 165    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 166    case PIPE_CAP_INDEP_BLEND_ENABLE:
 167    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 168    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 169    case PIPE_CAP_PRIMITIVE_RESTART:
 170    case PIPE_CAP_TGSI_INSTANCEID:
 171    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 172    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173    case PIPE_CAP_CONDITIONAL_RENDER:
 174    case PIPE_CAP_TEXTURE_BARRIER:
 175    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 176    case PIPE_CAP_START_INSTANCE:
 177    case PIPE_CAP_USER_VERTEX_BUFFERS:
 178    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 179    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 180    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 181    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 182    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 183    case PIPE_CAP_CLIP_HALFZ:
 184    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 185    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 186    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 187    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 188    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 189    case PIPE_CAP_TGSI_TXQS:
 190    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 191    case PIPE_CAP_SHAREABLE_SHADERS:
 192    case PIPE_CAP_CLEAR_TEXTURE:
 193    case PIPE_CAP_COMPUTE:
 194    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 195    case PIPE_CAP_INVALIDATE_BUFFER:
 196    case PIPE_CAP_STRING_MARKER:
 197    case PIPE_CAP_CULL_DISTANCE:
 198    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 199    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 200    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 201    case PIPE_CAP_TGSI_CLOCK:
 202    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 203    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 204       return 1;
 205    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 206       return 1; /* class_3d >= NVA0_3D_CLASS; */
 207    /* supported on nva0+ */
 208    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 209       return class_3d >= NVA0_3D_CLASS;
 210    /* supported on nva3+ */
 211    case PIPE_CAP_CUBE_MAP_ARRAY:
 212    case PIPE_CAP_INDEP_BLEND_FUNC:
 213    case PIPE_CAP_TEXTURE_QUERY_LOD:
 214    case PIPE_CAP_SAMPLE_SHADING:
 215    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 216       return class_3d >= NVA3_3D_CLASS;
 217
 218    /* unsupported caps */
 219    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 220    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 221    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 222    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 223    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 224    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 225    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 226    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 227    case PIPE_CAP_TGSI_TEXCOORD:
 228    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 229    case PIPE_CAP_TEXTURE_GATHER_SM5:
 230    case PIPE_CAP_FAKE_SW_MSAA:
 231    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 232    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 233    case PIPE_CAP_DRAW_INDIRECT:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 235    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 236    case PIPE_CAP_VERTEXID_NOBASE:
 237    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 238    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 239    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 240    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 241    case PIPE_CAP_DRAW_PARAMETERS:
 242    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 243    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 244    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 245    case PIPE_CAP_GENERATE_MIPMAP:
 246    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 247    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 248    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 249    case PIPE_CAP_QUERY_MEMORY_INFO:
 250    case PIPE_CAP_PCI_GROUP:
 251    case PIPE_CAP_PCI_BUS:
 252    case PIPE_CAP_PCI_DEVICE:
 253    case PIPE_CAP_PCI_FUNCTION:
 254    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 255    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 256    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 257    case PIPE_CAP_TGSI_VOTE:
 258    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 259    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 260    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 261    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 262    case PIPE_CAP_NATIVE_FENCE_FD:
 263    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 264    case PIPE_CAP_TGSI_FS_FBFETCH:
 265    case PIPE_CAP_DOUBLES:
 266    case PIPE_CAP_INT64:
 267    case PIPE_CAP_INT64_DIVMOD:
 268    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 269    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 270    case PIPE_CAP_TGSI_BALLOT:
 271    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 272    case PIPE_CAP_POST_DEPTH_COVERAGE:
 273    case PIPE_CAP_BINDLESS_TEXTURE:
 274    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 275    case PIPE_CAP_QUERY_SO_OVERFLOW:
 276    case PIPE_CAP_MEMOBJ:
 277    case PIPE_CAP_LOAD_CONSTBUF:
 278    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 279    case PIPE_CAP_TILE_RASTER_ORDER:
 280    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 281    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 282    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 283    case PIPE_CAP_FENCE_SIGNAL:
 284    case PIPE_CAP_CONSTBUF0_FLAGS:
 285    case PIPE_CAP_PACKED_UNIFORMS:
 286    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 287    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 288    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 289    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 290    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 291    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 292       return 0;
 293
 294    case PIPE_CAP_VENDOR_ID:
 295       return 0x10de;
 296    case PIPE_CAP_DEVICE_ID: {
 297       uint64_t device_id;
 298       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 299          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 300          return -1;
 301       }
 302       return device_id;
 303    }
 304    case PIPE_CAP_ACCELERATED:
 305       return 1;
 306    case PIPE_CAP_VIDEO_MEMORY:
 307       return dev->vram_size >> 20;
 308    case PIPE_CAP_UMA:
 309       return 0;
 310    }
 311
 312    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 313    return 0;
 314 }
 315
 316 static int
 317 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 318                              enum pipe_shader_type shader,
 319                              enum pipe_shader_cap param)
 320 {
 321    switch (shader) {
 322    case PIPE_SHADER_VERTEX:
 323    case PIPE_SHADER_GEOMETRY:
 324    case PIPE_SHADER_FRAGMENT:
 325       break;
 326    case PIPE_SHADER_COMPUTE:
 327    default:
 328       return 0;
 329    }
 330
 331    switch (param) {
 332    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 333    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 334    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 335    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 336       return 16384;
 337    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 338       return 4;
 339    case PIPE_SHADER_CAP_MAX_INPUTS:
 340       if (shader == PIPE_SHADER_VERTEX)
 341          return 32;
 342       return 15;
 343    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 344       return 16;
 345    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 346       return 65536;
 347    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 348       return NV50_MAX_PIPE_CONSTBUFS;
 349    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 350       return shader != PIPE_SHADER_FRAGMENT;
 351    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 352    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 353    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 354       return 1;
 355    case PIPE_SHADER_CAP_MAX_TEMPS:
 356       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 357    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 358       return 1;
 359    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 360       return 1;
 361    case PIPE_SHADER_CAP_INT64_ATOMICS:
 362    case PIPE_SHADER_CAP_FP16:
 363    case PIPE_SHADER_CAP_SUBROUTINES:
 364       return 0; /* please inline, or provide function declarations */
 365    case PIPE_SHADER_CAP_INTEGERS:
 366       return 1;
 367    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 368       return 1;
 369    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 370       /* The chip could handle more sampler views than samplers */
 371    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 372       return MIN2(16, PIPE_MAX_SAMPLERS);
 373    case PIPE_SHADER_CAP_PREFERRED_IR:
 374       return PIPE_SHADER_IR_TGSI;
 375    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 376       return 32;
 377    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 378    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 379    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 380    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 381    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 382    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 383    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 384    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 385    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 386    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 387    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 388       return 0;
 389    default:
 390       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 391       return 0;
 392    }
 393 }
 394
 395 static float
 396 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 397 {
 398    switch (param) {
 399    case PIPE_CAPF_MAX_LINE_WIDTH:
 400    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 401       return 10.0f;
 402    case PIPE_CAPF_MAX_POINT_WIDTH:
 403    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 404       return 64.0f;
 405    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 406       return 16.0f;
 407    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 408       return 4.0f;
 409    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 410    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 411    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 412       return 0.0f;
 413    }
 414
 415    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 416    return 0.0f;
 417 }
 418
 419 static int
 420 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 421                               enum pipe_shader_ir ir_type,
 422                               enum pipe_compute_cap param, void *data)
 423 {
 424    struct nv50_screen *screen = nv50_screen(pscreen);
 425
 426 #define RET(x) do {                  \
 427    if (data)                         \
 428       memcpy(data, x, sizeof(x));    \
 429    return sizeof(x);                 \
 430 } while (0)
 431
 432    switch (param) {
 433    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 434       RET((uint64_t []) { 2 });
 435    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 436       RET(((uint64_t []) { 65535, 65535 }));
 437    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 438       RET(((uint64_t []) { 512, 512, 64 }));
 439    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 440       RET((uint64_t []) { 512 });
 441    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 442       RET((uint64_t []) { 1ULL << 32 });
 443    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 444       RET((uint64_t []) { 16 << 10 });
 445    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 446       RET((uint64_t []) { 16 << 10 });
 447    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 448       RET((uint64_t []) { 4096 });
 449    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 450       RET((uint32_t []) { 32 });
 451    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 452       RET((uint64_t []) { 1ULL << 40 });
 453    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 454       RET((uint32_t []) { 0 });
 455    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 456       RET((uint32_t []) { screen->mp_count });
 457    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 458       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 459    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 460       RET((uint32_t []) { 32 });
 461    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 462       RET((uint64_t []) { 0 });
 463    default:
 464       return 0;
 465    }
 466
 467 #undef RET
 468 }
 469
 470 static void
 471 nv50_screen_destroy(struct pipe_screen *pscreen)
 472 {
 473    struct nv50_screen *screen = nv50_screen(pscreen);
 474
 475    if (!nouveau_drm_screen_unref(&screen->base))
 476       return;
 477
 478    if (screen->base.fence.current) {
 479       struct nouveau_fence *current = NULL;
 480
 481       /* nouveau_fence_wait will create a new current fence, so wait on the
 482        * _current_ one, and remove both.
 483        */
 484       nouveau_fence_ref(screen->base.fence.current, &current);
 485       nouveau_fence_wait(current, NULL);
 486       nouveau_fence_ref(NULL, &current);
 487       nouveau_fence_ref(NULL, &screen->base.fence.current);
 488    }
 489    if (screen->base.pushbuf)
 490       screen->base.pushbuf->user_priv = NULL;
 491
 492    if (screen->blitter)
 493       nv50_blitter_destroy(screen);
 494    if (screen->pm.prog) {
 495       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 496       nv50_program_destroy(NULL, screen->pm.prog);
 497       FREE(screen->pm.prog);
 498    }
 499
 500    nouveau_bo_ref(NULL, &screen->code);
 501    nouveau_bo_ref(NULL, &screen->tls_bo);
 502    nouveau_bo_ref(NULL, &screen->stack_bo);
 503    nouveau_bo_ref(NULL, &screen->txc);
 504    nouveau_bo_ref(NULL, &screen->uniforms);
 505    nouveau_bo_ref(NULL, &screen->fence.bo);
 506
 507    nouveau_heap_destroy(&screen->vp_code_heap);
 508    nouveau_heap_destroy(&screen->gp_code_heap);
 509    nouveau_heap_destroy(&screen->fp_code_heap);
 510
 511    FREE(screen->tic.entries);
 512
 513    nouveau_object_del(&screen->tesla);
 514    nouveau_object_del(&screen->eng2d);
 515    nouveau_object_del(&screen->m2mf);
 516    nouveau_object_del(&screen->compute);
 517    nouveau_object_del(&screen->sync);
 518
 519    nouveau_screen_fini(&screen->base);
 520
 521    FREE(screen);
 522 }
 523
 524 static void
 525 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 526 {
 527    struct nv50_screen *screen = nv50_screen(pscreen);
 528    struct nouveau_pushbuf *push = screen->base.pushbuf;
 529
 530    /* we need to do it after possible flush in MARK_RING */
 531    *sequence = ++screen->base.fence.sequence;
 532
 533    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 534    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 535    PUSH_DATAh(push, screen->fence.bo->offset);
 536    PUSH_DATA (push, screen->fence.bo->offset);
 537    PUSH_DATA (push, *sequence);
 538    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 539                     NV50_3D_QUERY_GET_UNK4 |
 540                     NV50_3D_QUERY_GET_UNIT_CROP |
 541                     NV50_3D_QUERY_GET_TYPE_QUERY |
 542                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 543                     NV50_3D_QUERY_GET_SHORT);
 544 }
 545
 546 static u32
 547 nv50_screen_fence_update(struct pipe_screen *pscreen)
 548 {
 549    return nv50_screen(pscreen)->fence.map[0];
 550 }
 551
 552 static void
 553 nv50_screen_init_hwctx(struct nv50_screen *screen)
 554 {
 555    struct nouveau_pushbuf *push = screen->base.pushbuf;
 556    struct nv04_fifo *fifo;
 557    unsigned i;
 558
 559    fifo = (struct nv04_fifo *)screen->base.channel->data;
 560
 561    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 562    PUSH_DATA (push, screen->m2mf->handle);
 563    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 564    PUSH_DATA (push, screen->sync->handle);
 565    PUSH_DATA (push, fifo->vram);
 566    PUSH_DATA (push, fifo->vram);
 567
 568    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 569    PUSH_DATA (push, screen->eng2d->handle);
 570    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 571    PUSH_DATA (push, screen->sync->handle);
 572    PUSH_DATA (push, fifo->vram);
 573    PUSH_DATA (push, fifo->vram);
 574    PUSH_DATA (push, fifo->vram);
 575    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 576    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 577    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 578    PUSH_DATA (push, 0);
 579    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 580    PUSH_DATA (push, 0);
 581    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 582    PUSH_DATA (push, 1);
 583    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 584    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 585
 586    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 587    PUSH_DATA (push, screen->tesla->handle);
 588
 589    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 590    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 591
 592    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 593    PUSH_DATA (push, screen->sync->handle);
 594    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 595    for (i = 0; i < 11; ++i)
 596       PUSH_DATA(push, fifo->vram);
 597    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 598    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 599       PUSH_DATA(push, fifo->vram);
 600
 601    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 602    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 603    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 604    PUSH_DATA (push, 0xf);
 605
 606    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 607       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 608       PUSH_DATA (push, 0x18);
 609    }
 610
 611    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 612    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 613
 614    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 615    for (i = 0; i < 8; ++i)
 616       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 617
 618    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 619    PUSH_DATA (push, 1);
 620
 621    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 622    PUSH_DATA (push, 0);
 623    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 624    PUSH_DATA (push, 0);
 625    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 626    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 627    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 628    PUSH_DATA (push, 0);
 629    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 630    PUSH_DATA (push, 1);
 631    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 632    PUSH_DATA (push, 1);
 633
 634    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 635       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 636       PUSH_DATA (push, 0);
 637    }
 638
 639    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 640    PUSH_DATA (push, 0);
 641    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 642    PUSH_DATA (push, 0);
 643    PUSH_DATA (push, 0);
 644    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 645    PUSH_DATA (push, 0x3f);
 646
 647    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 648    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 649    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 650
 651    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 652    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 653    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 654
 655    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 656    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 657    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 658
 659    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 660    PUSH_DATAh(push, screen->tls_bo->offset);
 661    PUSH_DATA (push, screen->tls_bo->offset);
 662    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 663
 664    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 665    PUSH_DATAh(push, screen->stack_bo->offset);
 666    PUSH_DATA (push, screen->stack_bo->offset);
 667    PUSH_DATA (push, 4);
 668
 669    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 670    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 671    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 672    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 673
 674    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 675    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 676    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 677    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 678
 679    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 680    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 681    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 682    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 683
 684    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 685    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 686    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 687    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 688
 689    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 690    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 691    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 692    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 693
 694    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 695    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 696    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 697    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 698    PUSH_DATAf(push, 0.0f);
 699    PUSH_DATAf(push, 0.0f);
 700    PUSH_DATAf(push, 0.0f);
 701    PUSH_DATAf(push, 0.0f);
 702    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 703    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 704    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 705
 706    nv50_upload_ms_info(push);
 707
 708    /* max TIC (bits 4:8) & TSC bindings, per program type */
 709    for (i = 0; i < 3; ++i) {
 710       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 711       PUSH_DATA (push, 0x54);
 712    }
 713
 714    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 715    PUSH_DATAh(push, screen->txc->offset);
 716    PUSH_DATA (push, screen->txc->offset);
 717    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 718
 719    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 720    PUSH_DATAh(push, screen->txc->offset + 65536);
 721    PUSH_DATA (push, screen->txc->offset + 65536);
 722    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 723
 724    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 725    PUSH_DATA (push, 0);
 726
 727    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 728    PUSH_DATA (push, 0);
 729    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 730    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 731    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 732    for (i = 0; i < 8 * 2; ++i)
 733       PUSH_DATA(push, 0);
 734    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 735    PUSH_DATA (push, 0);
 736
 737    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 738    PUSH_DATA (push, 1);
 739    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 740       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 741       PUSH_DATAf(push, 0.0f);
 742       PUSH_DATAf(push, 1.0f);
 743       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 744       PUSH_DATA (push, 8192 << 16);
 745       PUSH_DATA (push, 8192 << 16);
 746    }
 747
 748    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 749 #ifdef NV50_SCISSORS_CLIPPING
 750    PUSH_DATA (push, 0x0000);
 751 #else
 752    PUSH_DATA (push, 0x1080);
 753 #endif
 754
 755    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 756    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 757
 758    /* We use scissors instead of exact view volume clipping,
 759     * so they're always enabled.
 760     */
 761    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 762       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 763       PUSH_DATA (push, 1);
 764       PUSH_DATA (push, 8192 << 16);
 765       PUSH_DATA (push, 8192 << 16);
 766    }
 767
 768    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 769    PUSH_DATA (push, 1);
 770    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 771    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 772    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 773    PUSH_DATA (push, 0x11111111);
 774    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 775    PUSH_DATA (push, 1);
 776
 777    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 778    PUSH_DATA (push, 0);
 779    if (screen->base.class_3d >= NV84_3D_CLASS) {
 780       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 781       PUSH_DATA (push, 0);
 782    }
 783
 784    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 785    PUSH_DATA (push, 1);
 786    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 787    PUSH_DATA (push, 1);
 788
 789    PUSH_KICK (push);
 790 }
 791
 792 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 793       uint64_t *tls_size)
 794 {
 795    struct nouveau_device *dev = screen->base.device;
 796    int ret;
 797
 798    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 799          ONE_TEMP_SIZE;
 800    if (nouveau_mesa_debug)
 801       debug_printf("allocating space for %u temps\n",
 802             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 803    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 804          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 805
 806    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 807                         *tls_size, NULL, &screen->tls_bo);
 808    if (ret) {
 809       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 810       return ret;
 811    }
 812
 813    return 0;
 814 }
 815
 816 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 817 {
 818    struct nouveau_pushbuf *push = screen->base.pushbuf;
 819    int ret;
 820    uint64_t tls_size;
 821
 822    if (tls_space < screen->cur_tls_space)
 823       return 0;
 824    if (tls_space > screen->max_tls_space) {
 825       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 826        * LOCAL_WARPS_NO_CLAMP) */
 827       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 828             (unsigned)(tls_space / ONE_TEMP_SIZE),
 829             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 830       return -ENOMEM;
 831    }
 832
 833    nouveau_bo_ref(NULL, &screen->tls_bo);
 834    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 835    if (ret)
 836       return ret;
 837
 838    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 839    PUSH_DATAh(push, screen->tls_bo->offset);
 840    PUSH_DATA (push, screen->tls_bo->offset);
 841    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 842
 843    return 1;
 844 }
 845
 846 struct nouveau_screen *
 847 nv50_screen_create(struct nouveau_device *dev)
 848 {
 849    struct nv50_screen *screen;
 850    struct pipe_screen *pscreen;
 851    struct nouveau_object *chan;
 852    uint64_t value;
 853    uint32_t tesla_class;
 854    unsigned stack_size;
 855    int ret;
 856
 857    screen = CALLOC_STRUCT(nv50_screen);
 858    if (!screen)
 859       return NULL;
 860    pscreen = &screen->base.base;
 861    pscreen->destroy = nv50_screen_destroy;
 862
 863    ret = nouveau_screen_init(&screen->base, dev);
 864    if (ret) {
 865       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 866       goto fail;
 867    }
 868
 869    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 870     *  admit them to VRAM.
 871     */
 872    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 873       PIPE_BIND_VERTEX_BUFFER;
 874    screen->base.sysmem_bindings |=
 875       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 876
 877    screen->base.pushbuf->user_priv = screen;
 878    screen->base.pushbuf->rsvd_kick = 5;
 879
 880    chan = screen->base.channel;
 881
 882    pscreen->context_create = nv50_create;
 883    pscreen->is_format_supported = nv50_screen_is_format_supported;
 884    pscreen->get_param = nv50_screen_get_param;
 885    pscreen->get_shader_param = nv50_screen_get_shader_param;
 886    pscreen->get_paramf = nv50_screen_get_paramf;
 887    pscreen->get_compute_param = nv50_screen_get_compute_param;
 888    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 889    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 890
 891    nv50_screen_init_resource_functions(pscreen);
 892
 893    if (screen->base.device->chipset < 0x84 ||
 894        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 895       /* PMPEG */
 896       nouveau_screen_init_vdec(&screen->base);
 897    } else if (screen->base.device->chipset < 0x98 ||
 898               screen->base.device->chipset == 0xa0) {
 899       /* VP2 */
 900       screen->base.base.get_video_param = nv84_screen_get_video_param;
 901       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 902    } else {
 903       /* VP3/4 */
 904       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 905       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 906    }
 907
 908    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 909                         NULL, &screen->fence.bo);
 910    if (ret) {
 911       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 912       goto fail;
 913    }
 914
 915    nouveau_bo_map(screen->fence.bo, 0, NULL);
 916    screen->fence.map = screen->fence.bo->map;
 917    screen->base.fence.emit = nv50_screen_fence_emit;
 918    screen->base.fence.update = nv50_screen_fence_update;
 919
 920    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 921                             &(struct nv04_notify){ .length = 32 },
 922                             sizeof(struct nv04_notify), &screen->sync);
 923    if (ret) {
 924       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 925       goto fail;
 926    }
 927
 928    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 929                             NULL, 0, &screen->m2mf);
 930    if (ret) {
 931       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 932       goto fail;
 933    }
 934
 935    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 936                             NULL, 0, &screen->eng2d);
 937    if (ret) {
 938       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 939       goto fail;
 940    }
 941
 942    switch (dev->chipset & 0xf0) {
 943    case 0x50:
 944       tesla_class = NV50_3D_CLASS;
 945       break;
 946    case 0x80:
 947    case 0x90:
 948       tesla_class = NV84_3D_CLASS;
 949       break;
 950    case 0xa0:
 951       switch (dev->chipset) {
 952       case 0xa0:
 953       case 0xaa:
 954       case 0xac:
 955          tesla_class = NVA0_3D_CLASS;
 956          break;
 957       case 0xaf:
 958          tesla_class = NVAF_3D_CLASS;
 959          break;
 960       default:
 961          tesla_class = NVA3_3D_CLASS;
 962          break;
 963       }
 964       break;
 965    default:
 966       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 967       goto fail;
 968    }
 969    screen->base.class_3d = tesla_class;
 970
 971    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 972                             NULL, 0, &screen->tesla);
 973    if (ret) {
 974       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 975       goto fail;
 976    }
 977
 978    /* This over-allocates by a page. The GP, which would execute at the end of
 979     * the last page, would trigger faults. The going theory is that it
 980     * prefetches up to a certain amount.
 981     */
 982    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 983                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 984                         NULL, &screen->code);
 985    if (ret) {
 986       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 987       goto fail;
 988    }
 989
 990    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 991    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 992    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 993
 994    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 995
 996    screen->TPs = util_bitcount(value & 0xffff);
 997    screen->MPsInTP = util_bitcount(value & 0x0f000000);
 998
 999    screen->mp_count = screen->TPs * screen->MPsInTP;
1000
1001    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1002          STACK_WARPS_ALLOC * 64 * 8;
1003
1004    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1005                         &screen->stack_bo);
1006    if (ret) {
1007       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1008       goto fail;
1009    }
1010
1011    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1012          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1013          ONE_TEMP_SIZE;
1014    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1015    screen->max_tls_space /= 2; /* half of vram */
1016
1017    /* hw can address max 64 KiB */
1018    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1019
1020    uint64_t tls_size;
1021    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1022    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1023    if (ret)
1024       goto fail;
1025
1026    if (nouveau_mesa_debug)
1027       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1028             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1029
1030    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1031                         &screen->uniforms);
1032    if (ret) {
1033       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1034       goto fail;
1035    }
1036
1037    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1038                         &screen->txc);
1039    if (ret) {
1040       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1041       goto fail;
1042    }
1043
1044    screen->tic.entries = CALLOC(4096, sizeof(void *));
1045    screen->tsc.entries = screen->tic.entries + 2048;
1046
1047    if (!nv50_blitter_create(screen))
1048       goto fail;
1049
1050    nv50_screen_init_hwctx(screen);
1051
1052    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1053    if (ret) {
1054       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1055       goto fail;
1056    }
1057
1058    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1059
1060    return &screen->base;
1061
1062 fail:
1063    screen->base.base.context_create = NULL;
1064    return &screen->base;
1065 }
1066
1067 int
1068 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1069 {
1070    int i = screen->tic.next;
1071
1072    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1073       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1074
1075    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1076
1077    if (screen->tic.entries[i])
1078       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1079
1080    screen->tic.entries[i] = entry;
1081    return i;
1082 }
1083
1084 int
1085 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1086 {
1087    int i = screen->tsc.next;
1088
1089    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1090       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1091
1092    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1093
1094    if (screen->tsc.entries[i])
1095       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1096
1097    screen->tsc.entries[i] = entry;
1098    return i;
1099 }