src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* shared is always supported */
  79    bindings &= ~(PIPE_BIND_LINEAR |
  80                  PIPE_BIND_SHARED);
  81
  82    return (( nv50_format_table[format].usage |
  83             nv50_vertex_format[format].usage) & bindings) == bindings;
  84 }
  85
  86 static int
  87 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  88 {
  89    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  90    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  91
  92    switch (param) {
  93    /* non-boolean caps */
  94    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  97       return 12;
  98    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  99       return 14;
 100    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 101       return 512;
 102    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 103    case PIPE_CAP_MIN_TEXEL_OFFSET:
 104       return -8;
 105    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MAX_TEXEL_OFFSET:
 107       return 7;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 128 * 1024 * 1024;
 110    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 111       return 330;
 112    case PIPE_CAP_MAX_RENDER_TARGETS:
 113       return 8;
 114    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 115       return 1;
 116    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 117       return 4;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 120       return 64;
 121    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 122    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 123       return 1024;
 124    case PIPE_CAP_MAX_VERTEX_STREAMS:
 125       return 1;
 126    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 127       return 2048;
 128    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 129       return 256;
 130    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 131       return 16; /* 256 for binding as RT, but that's not possible in GL */
 132    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 133       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 134    case PIPE_CAP_MAX_VIEWPORTS:
 135       return NV50_MAX_VIEWPORTS;
 136    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 137       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 138    case PIPE_CAP_ENDIANNESS:
 139       return PIPE_ENDIAN_LITTLE;
 140    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 141       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 142    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 143       return NV50_MAX_WINDOW_RECTANGLES;
 144
 145    /* supported caps */
 146    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 147    case PIPE_CAP_TEXTURE_SWIZZLE:
 148    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 149    case PIPE_CAP_NPOT_TEXTURES:
 150    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 152    case PIPE_CAP_ANISOTROPIC_FILTER:
 153    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 154    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 155    case PIPE_CAP_TWO_SIDED_STENCIL:
 156    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 157    case PIPE_CAP_POINT_SPRITE:
 158    case PIPE_CAP_SM3:
 159    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 160    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 161    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 162    case PIPE_CAP_QUERY_TIMESTAMP:
 163    case PIPE_CAP_QUERY_TIME_ELAPSED:
 164    case PIPE_CAP_OCCLUSION_QUERY:
 165    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 166    case PIPE_CAP_INDEP_BLEND_ENABLE:
 167    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 168    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 169    case PIPE_CAP_PRIMITIVE_RESTART:
 170    case PIPE_CAP_TGSI_INSTANCEID:
 171    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 172    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173    case PIPE_CAP_CONDITIONAL_RENDER:
 174    case PIPE_CAP_TEXTURE_BARRIER:
 175    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 176    case PIPE_CAP_START_INSTANCE:
 177    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 178    case PIPE_CAP_USER_VERTEX_BUFFERS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 181    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 182    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 183    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 184    case PIPE_CAP_CLIP_HALFZ:
 185    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 186    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 187    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 188    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 189    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 190    case PIPE_CAP_TGSI_TXQS:
 191    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 192    case PIPE_CAP_SHAREABLE_SHADERS:
 193    case PIPE_CAP_CLEAR_TEXTURE:
 194    case PIPE_CAP_COMPUTE:
 195    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 196    case PIPE_CAP_INVALIDATE_BUFFER:
 197    case PIPE_CAP_STRING_MARKER:
 198    case PIPE_CAP_CULL_DISTANCE:
 199    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 200    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 201    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 202    case PIPE_CAP_TGSI_CLOCK:
 203       return 1;
 204    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 205       return 1; /* class_3d >= NVA0_3D_CLASS; */
 206    /* supported on nva0+ */
 207    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 208       return class_3d >= NVA0_3D_CLASS;
 209    /* supported on nva3+ */
 210    case PIPE_CAP_CUBE_MAP_ARRAY:
 211    case PIPE_CAP_INDEP_BLEND_FUNC:
 212    case PIPE_CAP_TEXTURE_QUERY_LOD:
 213    case PIPE_CAP_SAMPLE_SHADING:
 214    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 215       return class_3d >= NVA3_3D_CLASS;
 216
 217    /* unsupported caps */
 218    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 219    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 220    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 221    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 222    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 223    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 224    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 225    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 226    case PIPE_CAP_TGSI_TEXCOORD:
 227    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 228    case PIPE_CAP_TEXTURE_GATHER_SM5:
 229    case PIPE_CAP_FAKE_SW_MSAA:
 230    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 231    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 232    case PIPE_CAP_DRAW_INDIRECT:
 233    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 235    case PIPE_CAP_VERTEXID_NOBASE:
 236    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 237    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 238    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 239    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 240    case PIPE_CAP_DRAW_PARAMETERS:
 241    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 242    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 243    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 244    case PIPE_CAP_GENERATE_MIPMAP:
 245    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 246    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 247    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 248    case PIPE_CAP_QUERY_MEMORY_INFO:
 249    case PIPE_CAP_PCI_GROUP:
 250    case PIPE_CAP_PCI_BUS:
 251    case PIPE_CAP_PCI_DEVICE:
 252    case PIPE_CAP_PCI_FUNCTION:
 253    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 254    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 255    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 256    case PIPE_CAP_TGSI_VOTE:
 257    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 258    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 259    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 260    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 261    case PIPE_CAP_NATIVE_FENCE_FD:
 262    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 263    case PIPE_CAP_TGSI_FS_FBFETCH:
 264    case PIPE_CAP_DOUBLES:
 265    case PIPE_CAP_INT64:
 266    case PIPE_CAP_INT64_DIVMOD:
 267    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 268    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 269    case PIPE_CAP_TGSI_BALLOT:
 270    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 271       return 0;
 272
 273    case PIPE_CAP_VENDOR_ID:
 274       return 0x10de;
 275    case PIPE_CAP_DEVICE_ID: {
 276       uint64_t device_id;
 277       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 278          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 279          return -1;
 280       }
 281       return device_id;
 282    }
 283    case PIPE_CAP_ACCELERATED:
 284       return 1;
 285    case PIPE_CAP_VIDEO_MEMORY:
 286       return dev->vram_size >> 20;
 287    case PIPE_CAP_UMA:
 288       return 0;
 289    }
 290
 291    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 292    return 0;
 293 }
 294
 295 static int
 296 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 297                              enum pipe_shader_type shader,
 298                              enum pipe_shader_cap param)
 299 {
 300    switch (shader) {
 301    case PIPE_SHADER_VERTEX:
 302    case PIPE_SHADER_GEOMETRY:
 303    case PIPE_SHADER_FRAGMENT:
 304       break;
 305    case PIPE_SHADER_COMPUTE:
 306    default:
 307       return 0;
 308    }
 309
 310    switch (param) {
 311    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 312    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 313    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 314    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 315       return 16384;
 316    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 317       return 4;
 318    case PIPE_SHADER_CAP_MAX_INPUTS:
 319       if (shader == PIPE_SHADER_VERTEX)
 320          return 32;
 321       return 15;
 322    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 323       return 16;
 324    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 325       return 65536;
 326    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 327       return NV50_MAX_PIPE_CONSTBUFS;
 328    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 329       return shader != PIPE_SHADER_FRAGMENT;
 330    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 331    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 332    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 333       return 1;
 334    case PIPE_SHADER_CAP_MAX_TEMPS:
 335       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 336    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 337       return 1;
 338    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 339       return 1;
 340    case PIPE_SHADER_CAP_SUBROUTINES:
 341       return 0; /* please inline, or provide function declarations */
 342    case PIPE_SHADER_CAP_INTEGERS:
 343       return 1;
 344    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 345       /* The chip could handle more sampler views than samplers */
 346    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 347       return MIN2(16, PIPE_MAX_SAMPLERS);
 348    case PIPE_SHADER_CAP_PREFERRED_IR:
 349       return PIPE_SHADER_IR_TGSI;
 350    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 351       return 32;
 352    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 353    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 354    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 355    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 356    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 357    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 358    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 359    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 360    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 361       return 0;
 362    default:
 363       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 364       return 0;
 365    }
 366 }
 367
 368 static float
 369 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 370 {
 371    switch (param) {
 372    case PIPE_CAPF_MAX_LINE_WIDTH:
 373    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 374       return 10.0f;
 375    case PIPE_CAPF_MAX_POINT_WIDTH:
 376    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 377       return 64.0f;
 378    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 379       return 16.0f;
 380    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 381       return 4.0f;
 382    case PIPE_CAPF_GUARD_BAND_LEFT:
 383    case PIPE_CAPF_GUARD_BAND_TOP:
 384       return 0.0f;
 385    case PIPE_CAPF_GUARD_BAND_RIGHT:
 386    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 387       return 0.0f; /* that or infinity */
 388    }
 389
 390    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 391    return 0.0f;
 392 }
 393
 394 static int
 395 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 396                               enum pipe_shader_ir ir_type,
 397                               enum pipe_compute_cap param, void *data)
 398 {
 399    struct nv50_screen *screen = nv50_screen(pscreen);
 400
 401 #define RET(x) do {                  \
 402    if (data)                         \
 403       memcpy(data, x, sizeof(x));    \
 404    return sizeof(x);                 \
 405 } while (0)
 406
 407    switch (param) {
 408    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 409       RET((uint64_t []) { 2 });
 410    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 411       RET(((uint64_t []) { 65535, 65535 }));
 412    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 413       RET(((uint64_t []) { 512, 512, 64 }));
 414    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 415       RET((uint64_t []) { 512 });
 416    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 417       RET((uint64_t []) { 1ULL << 32 });
 418    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 419       RET((uint64_t []) { 16 << 10 });
 420    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 421       RET((uint64_t []) { 16 << 10 });
 422    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 423       RET((uint64_t []) { 4096 });
 424    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 425       RET((uint32_t []) { 32 });
 426    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 427       RET((uint64_t []) { 1ULL << 40 });
 428    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 429       RET((uint32_t []) { 0 });
 430    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 431       RET((uint32_t []) { screen->mp_count });
 432    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 433       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 434    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 435       RET((uint32_t []) { 32 });
 436    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 437       RET((uint64_t []) { 0 });
 438    default:
 439       return 0;
 440    }
 441
 442 #undef RET
 443 }
 444
 445 static void
 446 nv50_screen_destroy(struct pipe_screen *pscreen)
 447 {
 448    struct nv50_screen *screen = nv50_screen(pscreen);
 449
 450    if (!nouveau_drm_screen_unref(&screen->base))
 451       return;
 452
 453    if (screen->base.fence.current) {
 454       struct nouveau_fence *current = NULL;
 455
 456       /* nouveau_fence_wait will create a new current fence, so wait on the
 457        * _current_ one, and remove both.
 458        */
 459       nouveau_fence_ref(screen->base.fence.current, &current);
 460       nouveau_fence_wait(current, NULL);
 461       nouveau_fence_ref(NULL, &current);
 462       nouveau_fence_ref(NULL, &screen->base.fence.current);
 463    }
 464    if (screen->base.pushbuf)
 465       screen->base.pushbuf->user_priv = NULL;
 466
 467    if (screen->blitter)
 468       nv50_blitter_destroy(screen);
 469    if (screen->pm.prog) {
 470       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 471       nv50_program_destroy(NULL, screen->pm.prog);
 472       FREE(screen->pm.prog);
 473    }
 474
 475    nouveau_bo_ref(NULL, &screen->code);
 476    nouveau_bo_ref(NULL, &screen->tls_bo);
 477    nouveau_bo_ref(NULL, &screen->stack_bo);
 478    nouveau_bo_ref(NULL, &screen->txc);
 479    nouveau_bo_ref(NULL, &screen->uniforms);
 480    nouveau_bo_ref(NULL, &screen->fence.bo);
 481
 482    nouveau_heap_destroy(&screen->vp_code_heap);
 483    nouveau_heap_destroy(&screen->gp_code_heap);
 484    nouveau_heap_destroy(&screen->fp_code_heap);
 485
 486    FREE(screen->tic.entries);
 487
 488    nouveau_object_del(&screen->tesla);
 489    nouveau_object_del(&screen->eng2d);
 490    nouveau_object_del(&screen->m2mf);
 491    nouveau_object_del(&screen->compute);
 492    nouveau_object_del(&screen->sync);
 493
 494    nouveau_screen_fini(&screen->base);
 495
 496    FREE(screen);
 497 }
 498
 499 static void
 500 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 501 {
 502    struct nv50_screen *screen = nv50_screen(pscreen);
 503    struct nouveau_pushbuf *push = screen->base.pushbuf;
 504
 505    /* we need to do it after possible flush in MARK_RING */
 506    *sequence = ++screen->base.fence.sequence;
 507
 508    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 509    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 510    PUSH_DATAh(push, screen->fence.bo->offset);
 511    PUSH_DATA (push, screen->fence.bo->offset);
 512    PUSH_DATA (push, *sequence);
 513    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 514                     NV50_3D_QUERY_GET_UNK4 |
 515                     NV50_3D_QUERY_GET_UNIT_CROP |
 516                     NV50_3D_QUERY_GET_TYPE_QUERY |
 517                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 518                     NV50_3D_QUERY_GET_SHORT);
 519 }
 520
 521 static u32
 522 nv50_screen_fence_update(struct pipe_screen *pscreen)
 523 {
 524    return nv50_screen(pscreen)->fence.map[0];
 525 }
 526
 527 static void
 528 nv50_screen_init_hwctx(struct nv50_screen *screen)
 529 {
 530    struct nouveau_pushbuf *push = screen->base.pushbuf;
 531    struct nv04_fifo *fifo;
 532    unsigned i;
 533
 534    fifo = (struct nv04_fifo *)screen->base.channel->data;
 535
 536    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 537    PUSH_DATA (push, screen->m2mf->handle);
 538    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 539    PUSH_DATA (push, screen->sync->handle);
 540    PUSH_DATA (push, fifo->vram);
 541    PUSH_DATA (push, fifo->vram);
 542
 543    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 544    PUSH_DATA (push, screen->eng2d->handle);
 545    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 546    PUSH_DATA (push, screen->sync->handle);
 547    PUSH_DATA (push, fifo->vram);
 548    PUSH_DATA (push, fifo->vram);
 549    PUSH_DATA (push, fifo->vram);
 550    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 551    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 552    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 553    PUSH_DATA (push, 0);
 554    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 555    PUSH_DATA (push, 0);
 556    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 557    PUSH_DATA (push, 1);
 558    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 559    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 560
 561    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 562    PUSH_DATA (push, screen->tesla->handle);
 563
 564    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 565    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 566
 567    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 568    PUSH_DATA (push, screen->sync->handle);
 569    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 570    for (i = 0; i < 11; ++i)
 571       PUSH_DATA(push, fifo->vram);
 572    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 573    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 574       PUSH_DATA(push, fifo->vram);
 575
 576    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 577    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 578    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 579    PUSH_DATA (push, 0xf);
 580
 581    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 582       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 583       PUSH_DATA (push, 0x18);
 584    }
 585
 586    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 587    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 588
 589    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 590    for (i = 0; i < 8; ++i)
 591       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 592
 593    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 594    PUSH_DATA (push, 1);
 595
 596    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 597    PUSH_DATA (push, 0);
 598    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 599    PUSH_DATA (push, 0);
 600    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 601    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 602    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 603    PUSH_DATA (push, 0);
 604    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 605    PUSH_DATA (push, 1);
 606    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 607    PUSH_DATA (push, 1);
 608
 609    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 610       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 611       PUSH_DATA (push, 0);
 612    }
 613
 614    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 615    PUSH_DATA (push, 0);
 616    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 617    PUSH_DATA (push, 0);
 618    PUSH_DATA (push, 0);
 619    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 620    PUSH_DATA (push, 0x3f);
 621
 622    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 623    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 624    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 625
 626    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 627    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 628    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 629
 630    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 631    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 632    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 633
 634    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 635    PUSH_DATAh(push, screen->tls_bo->offset);
 636    PUSH_DATA (push, screen->tls_bo->offset);
 637    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 638
 639    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 640    PUSH_DATAh(push, screen->stack_bo->offset);
 641    PUSH_DATA (push, screen->stack_bo->offset);
 642    PUSH_DATA (push, 4);
 643
 644    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 645    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 646    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 647    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 648
 649    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 650    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 651    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 652    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 653
 654    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 655    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 656    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 657    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 658
 659    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 660    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 661    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 662    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 663
 664    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 665    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 666    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 667    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 668
 669    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 670    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 671    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 672    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 673    PUSH_DATAf(push, 0.0f);
 674    PUSH_DATAf(push, 0.0f);
 675    PUSH_DATAf(push, 0.0f);
 676    PUSH_DATAf(push, 0.0f);
 677    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 678    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 679    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 680
 681    nv50_upload_ms_info(push);
 682
 683    /* max TIC (bits 4:8) & TSC bindings, per program type */
 684    for (i = 0; i < 3; ++i) {
 685       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 686       PUSH_DATA (push, 0x54);
 687    }
 688
 689    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 690    PUSH_DATAh(push, screen->txc->offset);
 691    PUSH_DATA (push, screen->txc->offset);
 692    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 693
 694    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 695    PUSH_DATAh(push, screen->txc->offset + 65536);
 696    PUSH_DATA (push, screen->txc->offset + 65536);
 697    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 698
 699    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 700    PUSH_DATA (push, 0);
 701
 702    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 703    PUSH_DATA (push, 0);
 704    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 705    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 706    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 707    for (i = 0; i < 8 * 2; ++i)
 708       PUSH_DATA(push, 0);
 709    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 710    PUSH_DATA (push, 0);
 711
 712    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 713    PUSH_DATA (push, 1);
 714    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 715       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 716       PUSH_DATAf(push, 0.0f);
 717       PUSH_DATAf(push, 1.0f);
 718       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 719       PUSH_DATA (push, 8192 << 16);
 720       PUSH_DATA (push, 8192 << 16);
 721    }
 722
 723    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 724 #ifdef NV50_SCISSORS_CLIPPING
 725    PUSH_DATA (push, 0x0000);
 726 #else
 727    PUSH_DATA (push, 0x1080);
 728 #endif
 729
 730    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 731    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 732
 733    /* We use scissors instead of exact view volume clipping,
 734     * so they're always enabled.
 735     */
 736    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 737       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 738       PUSH_DATA (push, 1);
 739       PUSH_DATA (push, 8192 << 16);
 740       PUSH_DATA (push, 8192 << 16);
 741    }
 742
 743    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 744    PUSH_DATA (push, 1);
 745    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 746    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 747    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 748    PUSH_DATA (push, 0x11111111);
 749    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 750    PUSH_DATA (push, 1);
 751
 752    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 753    PUSH_DATA (push, 0);
 754    if (screen->base.class_3d >= NV84_3D_CLASS) {
 755       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 756       PUSH_DATA (push, 0);
 757    }
 758
 759    PUSH_KICK (push);
 760 }
 761
 762 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 763       uint64_t *tls_size)
 764 {
 765    struct nouveau_device *dev = screen->base.device;
 766    int ret;
 767
 768    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 769          ONE_TEMP_SIZE;
 770    if (nouveau_mesa_debug)
 771       debug_printf("allocating space for %u temps\n",
 772             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 773    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 774          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 775
 776    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 777                         *tls_size, NULL, &screen->tls_bo);
 778    if (ret) {
 779       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 780       return ret;
 781    }
 782
 783    return 0;
 784 }
 785
 786 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 787 {
 788    struct nouveau_pushbuf *push = screen->base.pushbuf;
 789    int ret;
 790    uint64_t tls_size;
 791
 792    if (tls_space < screen->cur_tls_space)
 793       return 0;
 794    if (tls_space > screen->max_tls_space) {
 795       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 796        * LOCAL_WARPS_NO_CLAMP) */
 797       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 798             (unsigned)(tls_space / ONE_TEMP_SIZE),
 799             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 800       return -ENOMEM;
 801    }
 802
 803    nouveau_bo_ref(NULL, &screen->tls_bo);
 804    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 805    if (ret)
 806       return ret;
 807
 808    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 809    PUSH_DATAh(push, screen->tls_bo->offset);
 810    PUSH_DATA (push, screen->tls_bo->offset);
 811    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 812
 813    return 1;
 814 }
 815
 816 struct nouveau_screen *
 817 nv50_screen_create(struct nouveau_device *dev)
 818 {
 819    struct nv50_screen *screen;
 820    struct pipe_screen *pscreen;
 821    struct nouveau_object *chan;
 822    uint64_t value;
 823    uint32_t tesla_class;
 824    unsigned stack_size;
 825    int ret;
 826
 827    screen = CALLOC_STRUCT(nv50_screen);
 828    if (!screen)
 829       return NULL;
 830    pscreen = &screen->base.base;
 831    pscreen->destroy = nv50_screen_destroy;
 832
 833    ret = nouveau_screen_init(&screen->base, dev);
 834    if (ret) {
 835       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 836       goto fail;
 837    }
 838
 839    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 840     *  admit them to VRAM.
 841     */
 842    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 843       PIPE_BIND_VERTEX_BUFFER;
 844    screen->base.sysmem_bindings |=
 845       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 846
 847    screen->base.pushbuf->user_priv = screen;
 848    screen->base.pushbuf->rsvd_kick = 5;
 849
 850    chan = screen->base.channel;
 851
 852    pscreen->context_create = nv50_create;
 853    pscreen->is_format_supported = nv50_screen_is_format_supported;
 854    pscreen->get_param = nv50_screen_get_param;
 855    pscreen->get_shader_param = nv50_screen_get_shader_param;
 856    pscreen->get_paramf = nv50_screen_get_paramf;
 857    pscreen->get_compute_param = nv50_screen_get_compute_param;
 858    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 859    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 860
 861    nv50_screen_init_resource_functions(pscreen);
 862
 863    if (screen->base.device->chipset < 0x84 ||
 864        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 865       /* PMPEG */
 866       nouveau_screen_init_vdec(&screen->base);
 867    } else if (screen->base.device->chipset < 0x98 ||
 868               screen->base.device->chipset == 0xa0) {
 869       /* VP2 */
 870       screen->base.base.get_video_param = nv84_screen_get_video_param;
 871       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 872    } else {
 873       /* VP3/4 */
 874       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 875       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 876    }
 877
 878    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 879                         NULL, &screen->fence.bo);
 880    if (ret) {
 881       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 882       goto fail;
 883    }
 884
 885    nouveau_bo_map(screen->fence.bo, 0, NULL);
 886    screen->fence.map = screen->fence.bo->map;
 887    screen->base.fence.emit = nv50_screen_fence_emit;
 888    screen->base.fence.update = nv50_screen_fence_update;
 889
 890    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 891                             &(struct nv04_notify){ .length = 32 },
 892                             sizeof(struct nv04_notify), &screen->sync);
 893    if (ret) {
 894       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 895       goto fail;
 896    }
 897
 898    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 899                             NULL, 0, &screen->m2mf);
 900    if (ret) {
 901       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 902       goto fail;
 903    }
 904
 905    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 906                             NULL, 0, &screen->eng2d);
 907    if (ret) {
 908       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 909       goto fail;
 910    }
 911
 912    switch (dev->chipset & 0xf0) {
 913    case 0x50:
 914       tesla_class = NV50_3D_CLASS;
 915       break;
 916    case 0x80:
 917    case 0x90:
 918       tesla_class = NV84_3D_CLASS;
 919       break;
 920    case 0xa0:
 921       switch (dev->chipset) {
 922       case 0xa0:
 923       case 0xaa:
 924       case 0xac:
 925          tesla_class = NVA0_3D_CLASS;
 926          break;
 927       case 0xaf:
 928          tesla_class = NVAF_3D_CLASS;
 929          break;
 930       default:
 931          tesla_class = NVA3_3D_CLASS;
 932          break;
 933       }
 934       break;
 935    default:
 936       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 937       goto fail;
 938    }
 939    screen->base.class_3d = tesla_class;
 940
 941    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 942                             NULL, 0, &screen->tesla);
 943    if (ret) {
 944       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 945       goto fail;
 946    }
 947
 948    /* This over-allocates by a page. The GP, which would execute at the end of
 949     * the last page, would trigger faults. The going theory is that it
 950     * prefetches up to a certain amount.
 951     */
 952    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 953                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 954                         NULL, &screen->code);
 955    if (ret) {
 956       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 957       goto fail;
 958    }
 959
 960    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 961    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 962    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 963
 964    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 965
 966    screen->TPs = util_bitcount(value & 0xffff);
 967    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 968
 969    screen->mp_count = screen->TPs * screen->MPsInTP;
 970
 971    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 972          STACK_WARPS_ALLOC * 64 * 8;
 973
 974    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 975                         &screen->stack_bo);
 976    if (ret) {
 977       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 978       goto fail;
 979    }
 980
 981    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 982          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 983          ONE_TEMP_SIZE;
 984    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 985    screen->max_tls_space /= 2; /* half of vram */
 986
 987    /* hw can address max 64 KiB */
 988    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 989
 990    uint64_t tls_size;
 991    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 992    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 993    if (ret)
 994       goto fail;
 995
 996    if (nouveau_mesa_debug)
 997       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 998             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 999
1000    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1001                         &screen->uniforms);
1002    if (ret) {
1003       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1004       goto fail;
1005    }
1006
1007    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1008                         &screen->txc);
1009    if (ret) {
1010       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1011       goto fail;
1012    }
1013
1014    screen->tic.entries = CALLOC(4096, sizeof(void *));
1015    screen->tsc.entries = screen->tic.entries + 2048;
1016
1017    if (!nv50_blitter_create(screen))
1018       goto fail;
1019
1020    nv50_screen_init_hwctx(screen);
1021
1022    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1023    if (ret) {
1024       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1025       goto fail;
1026    }
1027
1028    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1029
1030    return &screen->base;
1031
1032 fail:
1033    screen->base.base.context_create = NULL;
1034    return &screen->base;
1035 }
1036
1037 int
1038 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1039 {
1040    int i = screen->tic.next;
1041
1042    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1043       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1044
1045    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1046
1047    if (screen->tic.entries[i])
1048       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1049
1050    screen->tic.entries[i] = entry;
1051    return i;
1052 }
1053
1054 int
1055 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1056 {
1057    int i = screen->tsc.next;
1058
1059    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1060       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1061
1062    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1063
1064    if (screen->tsc.entries[i])
1065       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1066
1067    screen->tsc.entries[i] = entry;
1068    return i;
1069 }