src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50/nv50_context.h"
  28 #include "nv50/nv50_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nv_object.xml.h"
  33 #include <errno.h>
  34
  35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  37 #endif
  38
  39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  40 #define LOCAL_WARPS_ALLOC 32
  41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  42 #define STACK_WARPS_ALLOC 32
  43
  44 #define THREADS_IN_WARP 32
  45
  46 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  47
  48 static boolean
  49 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  50                                 enum pipe_format format,
  51                                 enum pipe_texture_target target,
  52                                 unsigned sample_count,
  53                                 unsigned bindings)
  54 {
  55    if (sample_count > 8)
  56       return FALSE;
  57    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  58       return FALSE;
  59    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  60       return FALSE;
  61
  62    if (!util_format_is_supported(format, bindings))
  63       return FALSE;
  64
  65    switch (format) {
  66    case PIPE_FORMAT_Z16_UNORM:
  67       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  68          return FALSE;
  69       break;
  70    default:
  71       break;
  72    }
  73
  74    /* transfers & shared are always supported */
  75    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  76                  PIPE_BIND_TRANSFER_WRITE |
  77                  PIPE_BIND_SHARED);
  78
  79    return (nv50_format_table[format].usage & bindings) == bindings;
  80 }
  81
  82 static int
  83 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  84 {
  85    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  86
  87    switch (param) {
  88    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  89       return 64;
  90    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  91       return 14;
  92    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  93       return 12;
  94    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  97       return 512;
  98    case PIPE_CAP_MIN_TEXEL_OFFSET:
  99       return -8;
 100    case PIPE_CAP_MAX_TEXEL_OFFSET:
 101       return 7;
 102    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 103    case PIPE_CAP_TEXTURE_SWIZZLE:
 104    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 105    case PIPE_CAP_NPOT_TEXTURES:
 106    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 107    case PIPE_CAP_ANISOTROPIC_FILTER:
 108    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 109       return 1;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 65536;
 112    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 113       return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS;
 114    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 115       return 0;
 116    case PIPE_CAP_CUBE_MAP_ARRAY:
 117       return 0;
 118       /*
 119       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 120       */
 121    case PIPE_CAP_TWO_SIDED_STENCIL:
 122    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 123    case PIPE_CAP_POINT_SPRITE:
 124       return 1;
 125    case PIPE_CAP_SM3:
 126       return 1;
 127    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 128       return 140;
 129    case PIPE_CAP_MAX_RENDER_TARGETS:
 130       return 8;
 131    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 132       return 1;
 133    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 134    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 135    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 136       return 1;
 137    case PIPE_CAP_QUERY_TIMESTAMP:
 138    case PIPE_CAP_QUERY_TIME_ELAPSED:
 139    case PIPE_CAP_OCCLUSION_QUERY:
 140       return 1;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 142       return 4;
 143    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 145       return 64;
 146    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 147       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 148    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 149    case PIPE_CAP_INDEP_BLEND_ENABLE:
 150       return 1;
 151    case PIPE_CAP_INDEP_BLEND_FUNC:
 152       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 153    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 154    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 155       return 1;
 156    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 157    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 158       return 0;
 159    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 160       return 0;
 161    case PIPE_CAP_PRIMITIVE_RESTART:
 162    case PIPE_CAP_TGSI_INSTANCEID:
 163    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 164    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 165    case PIPE_CAP_CONDITIONAL_RENDER:
 166    case PIPE_CAP_TEXTURE_BARRIER:
 167    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 168    case PIPE_CAP_START_INSTANCE:
 169       return 1;
 170    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 171       return 0; /* state trackers will know better */
 172    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 173    case PIPE_CAP_USER_INDEX_BUFFERS:
 174    case PIPE_CAP_USER_VERTEX_BUFFERS:
 175       return 1;
 176    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 177       return 256;
 178    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 179       return 1; /* 256 for binding as RT, but that's not possible in GL */
 180    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 181       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 182    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 183    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 184    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 185    case PIPE_CAP_TGSI_TEXCOORD:
 186       return 0;
 187    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 188       return 1;
 189    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 190       return 1;
 191    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 192       return 0;
 193    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 194       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 195    case PIPE_CAP_ENDIANNESS:
 196       return PIPE_ENDIAN_LITTLE;
 197    case PIPE_CAP_TGSI_VS_LAYER:
 198       return 0;
 199    default:
 200       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 201       return 0;
 202    }
 203 }
 204
 205 static int
 206 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 207                              enum pipe_shader_cap param)
 208 {
 209    switch (shader) {
 210    case PIPE_SHADER_VERTEX:
 211    case PIPE_SHADER_GEOMETRY:
 212    case PIPE_SHADER_FRAGMENT:
 213       break;
 214    default:
 215       return 0;
 216    }
 217
 218    switch (param) {
 219    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 220    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 221    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 222    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 223       return 16384;
 224    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 225       return 4;
 226    case PIPE_SHADER_CAP_MAX_INPUTS:
 227       if (shader == PIPE_SHADER_VERTEX)
 228          return 32;
 229       return 15;
 230    case PIPE_SHADER_CAP_MAX_CONSTS:
 231       return 65536 / 16;
 232    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 233       return NV50_MAX_PIPE_CONSTBUFS;
 234    case PIPE_SHADER_CAP_MAX_ADDRS:
 235       return 1;
 236    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 237    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 238       return shader != PIPE_SHADER_FRAGMENT;
 239    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 240    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 241       return 1;
 242    case PIPE_SHADER_CAP_MAX_PREDS:
 243       return 0;
 244    case PIPE_SHADER_CAP_MAX_TEMPS:
 245       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 246    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 247       return 1;
 248    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 249       return 0;
 250    case PIPE_SHADER_CAP_SUBROUTINES:
 251       return 0; /* please inline, or provide function declarations */
 252    case PIPE_SHADER_CAP_INTEGERS:
 253       return 1;
 254    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 255       /* The chip could handle more sampler views than samplers */
 256    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 257       return MIN2(32, PIPE_MAX_SAMPLERS);
 258    default:
 259       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 260       return 0;
 261    }
 262 }
 263
 264 static float
 265 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 266 {
 267    switch (param) {
 268    case PIPE_CAPF_MAX_LINE_WIDTH:
 269    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 270       return 10.0f;
 271    case PIPE_CAPF_MAX_POINT_WIDTH:
 272    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 273       return 64.0f;
 274    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 275       return 16.0f;
 276    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 277       return 4.0f;
 278    default:
 279       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 280       return 0.0f;
 281    }
 282 }
 283
 284 static void
 285 nv50_screen_destroy(struct pipe_screen *pscreen)
 286 {
 287    struct nv50_screen *screen = nv50_screen(pscreen);
 288
 289    if (screen->base.fence.current) {
 290       nouveau_fence_wait(screen->base.fence.current);
 291       nouveau_fence_ref (NULL, &screen->base.fence.current);
 292    }
 293    if (screen->base.pushbuf)
 294       screen->base.pushbuf->user_priv = NULL;
 295
 296    if (screen->blitter)
 297       nv50_blitter_destroy(screen);
 298
 299    nouveau_bo_ref(NULL, &screen->code);
 300    nouveau_bo_ref(NULL, &screen->tls_bo);
 301    nouveau_bo_ref(NULL, &screen->stack_bo);
 302    nouveau_bo_ref(NULL, &screen->txc);
 303    nouveau_bo_ref(NULL, &screen->uniforms);
 304    nouveau_bo_ref(NULL, &screen->fence.bo);
 305
 306    nouveau_heap_destroy(&screen->vp_code_heap);
 307    nouveau_heap_destroy(&screen->gp_code_heap);
 308    nouveau_heap_destroy(&screen->fp_code_heap);
 309
 310    FREE(screen->tic.entries);
 311
 312    nouveau_object_del(&screen->tesla);
 313    nouveau_object_del(&screen->eng2d);
 314    nouveau_object_del(&screen->m2mf);
 315    nouveau_object_del(&screen->sync);
 316
 317    nouveau_screen_fini(&screen->base);
 318
 319    FREE(screen);
 320 }
 321
 322 static void
 323 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 324 {
 325    struct nv50_screen *screen = nv50_screen(pscreen);
 326    struct nouveau_pushbuf *push = screen->base.pushbuf;
 327
 328    /* we need to do it after possible flush in MARK_RING */
 329    *sequence = ++screen->base.fence.sequence;
 330
 331    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 332    PUSH_DATAh(push, screen->fence.bo->offset);
 333    PUSH_DATA (push, screen->fence.bo->offset);
 334    PUSH_DATA (push, *sequence);
 335    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 336                     NV50_3D_QUERY_GET_UNK4 |
 337                     NV50_3D_QUERY_GET_UNIT_CROP |
 338                     NV50_3D_QUERY_GET_TYPE_QUERY |
 339                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 340                     NV50_3D_QUERY_GET_SHORT);
 341 }
 342
 343 static u32
 344 nv50_screen_fence_update(struct pipe_screen *pscreen)
 345 {
 346    return nv50_screen(pscreen)->fence.map[0];
 347 }
 348
 349 static void
 350 nv50_screen_init_hwctx(struct nv50_screen *screen)
 351 {
 352    struct nouveau_pushbuf *push = screen->base.pushbuf;
 353    struct nv04_fifo *fifo;
 354    unsigned i;
 355
 356    fifo = (struct nv04_fifo *)screen->base.channel->data;
 357
 358    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 359    PUSH_DATA (push, screen->m2mf->handle);
 360    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 361    PUSH_DATA (push, screen->sync->handle);
 362    PUSH_DATA (push, fifo->vram);
 363    PUSH_DATA (push, fifo->vram);
 364
 365    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 366    PUSH_DATA (push, screen->eng2d->handle);
 367    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 368    PUSH_DATA (push, screen->sync->handle);
 369    PUSH_DATA (push, fifo->vram);
 370    PUSH_DATA (push, fifo->vram);
 371    PUSH_DATA (push, fifo->vram);
 372    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 373    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 374    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 375    PUSH_DATA (push, 0);
 376    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 377    PUSH_DATA (push, 0);
 378    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 379    PUSH_DATA (push, 1);
 380
 381    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 382    PUSH_DATA (push, screen->tesla->handle);
 383
 384    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 385    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 386
 387    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 388    PUSH_DATA (push, screen->sync->handle);
 389    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 390    for (i = 0; i < 11; ++i)
 391       PUSH_DATA(push, fifo->vram);
 392    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 393    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 394       PUSH_DATA(push, fifo->vram);
 395
 396    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 397    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 398    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 399    PUSH_DATA (push, 0xf);
 400
 401    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 402       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 403       PUSH_DATA (push, 0x18);
 404    }
 405
 406    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 407    PUSH_DATA (push, 1);
 408
 409    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 410    PUSH_DATA (push, 0);
 411    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 412    PUSH_DATA (push, 0);
 413    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 414    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 415    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 416    PUSH_DATA (push, 0);
 417    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 418    PUSH_DATA (push, 0);
 419    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 420    PUSH_DATA (push, 1);
 421
 422    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 423       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 424       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 425    }
 426
 427    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 428    PUSH_DATA (push, 0);
 429    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 430    PUSH_DATA (push, 0);
 431    PUSH_DATA (push, 0);
 432    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 433    PUSH_DATA (push, 0x3f);
 434
 435    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 436    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 437    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 438
 439    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 440    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 441    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 442
 443    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 444    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 445    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 446
 447    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 448    PUSH_DATAh(push, screen->tls_bo->offset);
 449    PUSH_DATA (push, screen->tls_bo->offset);
 450    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 451
 452    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 453    PUSH_DATAh(push, screen->stack_bo->offset);
 454    PUSH_DATA (push, screen->stack_bo->offset);
 455    PUSH_DATA (push, 4);
 456
 457    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 458    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 459    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 460    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 461
 462    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 463    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 464    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 465    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 466
 467    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 468    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 469    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 470    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 471
 472    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 473    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 474    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 475    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 476
 477    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 478    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 479    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 480    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 481
 482    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 483    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 484    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 485    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 486    PUSH_DATAf(push, 0.0f);
 487    PUSH_DATAf(push, 0.0f);
 488    PUSH_DATAf(push, 0.0f);
 489    PUSH_DATAf(push, 0.0f);
 490    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 491    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 492    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 493
 494    nv50_upload_ms_info(push);
 495
 496    /* max TIC (bits 4:8) & TSC bindings, per program type */
 497    for (i = 0; i < 3; ++i) {
 498       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 499       PUSH_DATA (push, 0x54);
 500    }
 501
 502    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 503    PUSH_DATAh(push, screen->txc->offset);
 504    PUSH_DATA (push, screen->txc->offset);
 505    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 506
 507    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 508    PUSH_DATAh(push, screen->txc->offset + 65536);
 509    PUSH_DATA (push, screen->txc->offset + 65536);
 510    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 511
 512    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 513    PUSH_DATA (push, 0);
 514
 515    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 516    PUSH_DATA (push, 0);
 517    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 518    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 519    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 520    for (i = 0; i < 8 * 2; ++i)
 521       PUSH_DATA(push, 0);
 522    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 523    PUSH_DATA (push, 0);
 524
 525    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 526    PUSH_DATA (push, 1);
 527    BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
 528    PUSH_DATAf(push, 0.0f);
 529    PUSH_DATAf(push, 1.0f);
 530
 531    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 532 #ifdef NV50_SCISSORS_CLIPPING
 533    PUSH_DATA (push, 0x0000);
 534 #else
 535    PUSH_DATA (push, 0x1080);
 536 #endif
 537
 538    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 539    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 540
 541    /* We use scissors instead of exact view volume clipping,
 542     * so they're always enabled.
 543     */
 544    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
 545    PUSH_DATA (push, 1);
 546    PUSH_DATA (push, 8192 << 16);
 547    PUSH_DATA (push, 8192 << 16);
 548
 549    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 550    PUSH_DATA (push, 1);
 551    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 552    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 553    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 554    PUSH_DATA (push, 0x11111111);
 555    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 556    PUSH_DATA (push, 1);
 557
 558    PUSH_KICK (push);
 559 }
 560
 561 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 562       uint64_t *tls_size)
 563 {
 564    struct nouveau_device *dev = screen->base.device;
 565    int ret;
 566
 567    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 568          ONE_TEMP_SIZE;
 569    if (nouveau_mesa_debug)
 570       debug_printf("allocating space for %u temps\n",
 571             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 572    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 573          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 574
 575    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 576                         *tls_size, NULL, &screen->tls_bo);
 577    if (ret) {
 578       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 579       return ret;
 580    }
 581
 582    return 0;
 583 }
 584
 585 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 586 {
 587    struct nouveau_pushbuf *push = screen->base.pushbuf;
 588    int ret;
 589    uint64_t tls_size;
 590
 591    if (tls_space < screen->cur_tls_space)
 592       return 0;
 593    if (tls_space > screen->max_tls_space) {
 594       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 595        * LOCAL_WARPS_NO_CLAMP) */
 596       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 597             (unsigned)(tls_space / ONE_TEMP_SIZE),
 598             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 599       return -ENOMEM;
 600    }
 601
 602    nouveau_bo_ref(NULL, &screen->tls_bo);
 603    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 604    if (ret)
 605       return ret;
 606
 607    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 608    PUSH_DATAh(push, screen->tls_bo->offset);
 609    PUSH_DATA (push, screen->tls_bo->offset);
 610    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 611
 612    return 1;
 613 }
 614
 615 struct pipe_screen *
 616 nv50_screen_create(struct nouveau_device *dev)
 617 {
 618    struct nv50_screen *screen;
 619    struct pipe_screen *pscreen;
 620    struct nouveau_object *chan;
 621    uint64_t value;
 622    uint32_t tesla_class;
 623    unsigned stack_size;
 624    int ret;
 625
 626    screen = CALLOC_STRUCT(nv50_screen);
 627    if (!screen)
 628       return NULL;
 629    pscreen = &screen->base.base;
 630
 631    ret = nouveau_screen_init(&screen->base, dev);
 632    if (ret) {
 633       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 634       goto fail;
 635    }
 636
 637    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 638     *  admit them to VRAM.
 639     */
 640    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 641       PIPE_BIND_VERTEX_BUFFER;
 642    screen->base.sysmem_bindings |=
 643       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 644
 645    screen->base.pushbuf->user_priv = screen;
 646    screen->base.pushbuf->rsvd_kick = 5;
 647
 648    chan = screen->base.channel;
 649
 650    pscreen->destroy = nv50_screen_destroy;
 651    pscreen->context_create = nv50_create;
 652    pscreen->is_format_supported = nv50_screen_is_format_supported;
 653    pscreen->get_param = nv50_screen_get_param;
 654    pscreen->get_shader_param = nv50_screen_get_shader_param;
 655    pscreen->get_paramf = nv50_screen_get_paramf;
 656
 657    nv50_screen_init_resource_functions(pscreen);
 658
 659    if (screen->base.device->chipset < 0x84 ||
 660        debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
 661       /* PMPEG */
 662       nouveau_screen_init_vdec(&screen->base);
 663    } else if (screen->base.device->chipset < 0x98 ||
 664               screen->base.device->chipset == 0xa0) {
 665       /* VP2 */
 666       screen->base.base.get_video_param = nv84_screen_get_video_param;
 667       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 668    } else {
 669       /* VP3/4 */
 670       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 671       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 672    }
 673
 674    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 675                         NULL, &screen->fence.bo);
 676    if (ret) {
 677       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 678       goto fail;
 679    }
 680
 681    nouveau_bo_map(screen->fence.bo, 0, NULL);
 682    screen->fence.map = screen->fence.bo->map;
 683    screen->base.fence.emit = nv50_screen_fence_emit;
 684    screen->base.fence.update = nv50_screen_fence_update;
 685
 686    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 687                             &(struct nv04_notify){ .length = 32 },
 688                             sizeof(struct nv04_notify), &screen->sync);
 689    if (ret) {
 690       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 691       goto fail;
 692    }
 693
 694    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 695                             NULL, 0, &screen->m2mf);
 696    if (ret) {
 697       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 698       goto fail;
 699    }
 700
 701    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 702                             NULL, 0, &screen->eng2d);
 703    if (ret) {
 704       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 705       goto fail;
 706    }
 707
 708    switch (dev->chipset & 0xf0) {
 709    case 0x50:
 710       tesla_class = NV50_3D_CLASS;
 711       break;
 712    case 0x80:
 713    case 0x90:
 714       tesla_class = NV84_3D_CLASS;
 715       break;
 716    case 0xa0:
 717       switch (dev->chipset) {
 718       case 0xa0:
 719       case 0xaa:
 720       case 0xac:
 721          tesla_class = NVA0_3D_CLASS;
 722          break;
 723       case 0xaf:
 724          tesla_class = NVAF_3D_CLASS;
 725          break;
 726       default:
 727          tesla_class = NVA3_3D_CLASS;
 728          break;
 729       }
 730       break;
 731    default:
 732       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 733       goto fail;
 734    }
 735    screen->base.class_3d = tesla_class;
 736
 737    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 738                             NULL, 0, &screen->tesla);
 739    if (ret) {
 740       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 741       goto fail;
 742    }
 743
 744    /* This over-allocates by a whole code BO. The GP, which would execute at
 745     * the end of the last page, would trigger faults. The going theory is that
 746     * it prefetches up to a certain amount. This avoids dmesg spam.
 747     */
 748    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 749                         4 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code);
 750    if (ret) {
 751       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 752       goto fail;
 753    }
 754
 755    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 756    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 757    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 758
 759    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 760
 761    screen->TPs = util_bitcount(value & 0xffff);
 762    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 763
 764    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 765          STACK_WARPS_ALLOC * 64 * 8;
 766
 767    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 768                         &screen->stack_bo);
 769    if (ret) {
 770       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 771       goto fail;
 772    }
 773
 774    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 775          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 776          ONE_TEMP_SIZE;
 777    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 778    screen->max_tls_space /= 2; /* half of vram */
 779
 780    /* hw can address max 64 KiB */
 781    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 782
 783    uint64_t tls_size;
 784    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 785    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 786    if (ret)
 787       goto fail;
 788
 789    if (nouveau_mesa_debug)
 790       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 791             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 792
 793    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 794                         &screen->uniforms);
 795    if (ret) {
 796       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 797       goto fail;
 798    }
 799
 800    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 801                         &screen->txc);
 802    if (ret) {
 803       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 804       goto fail;
 805    }
 806
 807    screen->tic.entries = CALLOC(4096, sizeof(void *));
 808    screen->tsc.entries = screen->tic.entries + 2048;
 809
 810    if (!nv50_blitter_create(screen))
 811       goto fail;
 812
 813    nv50_screen_init_hwctx(screen);
 814
 815    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 816
 817    return pscreen;
 818
 819 fail:
 820    nv50_screen_destroy(pscreen);
 821    return NULL;
 822 }
 823
 824 int
 825 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 826 {
 827    int i = screen->tic.next;
 828
 829    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 830       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 831
 832    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 833
 834    if (screen->tic.entries[i])
 835       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 836
 837    screen->tic.entries[i] = entry;
 838    return i;
 839 }
 840
 841 int
 842 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 843 {
 844    int i = screen->tsc.next;
 845
 846    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 847       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 848
 849    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 850
 851    if (screen->tsc.entries[i])
 852       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 853
 854    screen->tsc.entries[i] = entry;
 855    return i;
 856 }