src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* shared is always supported */
  79    bindings &= ~(PIPE_BIND_LINEAR |
  80                  PIPE_BIND_SHARED);
  81
  82    return (( nv50_format_table[format].usage |
  83             nv50_vertex_format[format].usage) & bindings) == bindings;
  84 }
  85
  86 static int
  87 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  88 {
  89    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  90    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  91
  92    switch (param) {
  93    /* non-boolean caps */
  94    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  97       return 12;
  98    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  99       return 14;
 100    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 101       return 512;
 102    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 103    case PIPE_CAP_MIN_TEXEL_OFFSET:
 104       return -8;
 105    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MAX_TEXEL_OFFSET:
 107       return 7;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 128 * 1024 * 1024;
 110    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 111       return 330;
 112    case PIPE_CAP_MAX_RENDER_TARGETS:
 113       return 8;
 114    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 115       return 1;
 116    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 117       return 4;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 120       return 64;
 121    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 122    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 123       return 1024;
 124    case PIPE_CAP_MAX_VERTEX_STREAMS:
 125       return 1;
 126    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 127       return 2048;
 128    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 129       return 256;
 130    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 131       return 16; /* 256 for binding as RT, but that's not possible in GL */
 132    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 133       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 134    case PIPE_CAP_MAX_VIEWPORTS:
 135       return NV50_MAX_VIEWPORTS;
 136    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 137       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 138    case PIPE_CAP_ENDIANNESS:
 139       return PIPE_ENDIAN_LITTLE;
 140    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 141       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 142    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 143       return NV50_MAX_WINDOW_RECTANGLES;
 144
 145    /* supported caps */
 146    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 147    case PIPE_CAP_TEXTURE_SWIZZLE:
 148    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 149    case PIPE_CAP_NPOT_TEXTURES:
 150    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 152    case PIPE_CAP_ANISOTROPIC_FILTER:
 153    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 154    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 155    case PIPE_CAP_TWO_SIDED_STENCIL:
 156    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 157    case PIPE_CAP_POINT_SPRITE:
 158    case PIPE_CAP_SM3:
 159    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 160    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 161    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 162    case PIPE_CAP_QUERY_TIMESTAMP:
 163    case PIPE_CAP_QUERY_TIME_ELAPSED:
 164    case PIPE_CAP_OCCLUSION_QUERY:
 165    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 166    case PIPE_CAP_INDEP_BLEND_ENABLE:
 167    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 168    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 169    case PIPE_CAP_PRIMITIVE_RESTART:
 170    case PIPE_CAP_TGSI_INSTANCEID:
 171    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 172    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173    case PIPE_CAP_CONDITIONAL_RENDER:
 174    case PIPE_CAP_TEXTURE_BARRIER:
 175    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 176    case PIPE_CAP_START_INSTANCE:
 177    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 178    case PIPE_CAP_USER_INDEX_BUFFERS:
 179    case PIPE_CAP_USER_VERTEX_BUFFERS:
 180    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 181    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 182    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 183    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 184    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 185    case PIPE_CAP_CLIP_HALFZ:
 186    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 187    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 188    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 189    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 190    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 191    case PIPE_CAP_TGSI_TXQS:
 192    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 193    case PIPE_CAP_SHAREABLE_SHADERS:
 194    case PIPE_CAP_CLEAR_TEXTURE:
 195    case PIPE_CAP_COMPUTE:
 196    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 197    case PIPE_CAP_INVALIDATE_BUFFER:
 198    case PIPE_CAP_STRING_MARKER:
 199    case PIPE_CAP_CULL_DISTANCE:
 200    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 201       return 1;
 202    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 203       return 1; /* class_3d >= NVA0_3D_CLASS; */
 204    /* supported on nva0+ */
 205    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 206       return class_3d >= NVA0_3D_CLASS;
 207    /* supported on nva3+ */
 208    case PIPE_CAP_CUBE_MAP_ARRAY:
 209    case PIPE_CAP_INDEP_BLEND_FUNC:
 210    case PIPE_CAP_TEXTURE_QUERY_LOD:
 211    case PIPE_CAP_SAMPLE_SHADING:
 212    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 213       return class_3d >= NVA3_3D_CLASS;
 214
 215    /* unsupported caps */
 216    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 217    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 218    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 219    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 220    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 221    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 222    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 223    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 224    case PIPE_CAP_TGSI_TEXCOORD:
 225    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 226    case PIPE_CAP_TEXTURE_GATHER_SM5:
 227    case PIPE_CAP_FAKE_SW_MSAA:
 228    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 229    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 230    case PIPE_CAP_DRAW_INDIRECT:
 231    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 232    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 233    case PIPE_CAP_VERTEXID_NOBASE:
 234    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 235    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 236    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 237    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 238    case PIPE_CAP_DRAW_PARAMETERS:
 239    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 240    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 241    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 242    case PIPE_CAP_GENERATE_MIPMAP:
 243    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 244    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 245    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 246    case PIPE_CAP_QUERY_MEMORY_INFO:
 247    case PIPE_CAP_PCI_GROUP:
 248    case PIPE_CAP_PCI_BUS:
 249    case PIPE_CAP_PCI_DEVICE:
 250    case PIPE_CAP_PCI_FUNCTION:
 251    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 252    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 253    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 254    case PIPE_CAP_TGSI_VOTE:
 255    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 256    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 257    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 258       return 0;
 259
 260    case PIPE_CAP_VENDOR_ID:
 261       return 0x10de;
 262    case PIPE_CAP_DEVICE_ID: {
 263       uint64_t device_id;
 264       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 265          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 266          return -1;
 267       }
 268       return device_id;
 269    }
 270    case PIPE_CAP_ACCELERATED:
 271       return 1;
 272    case PIPE_CAP_VIDEO_MEMORY:
 273       return dev->vram_size >> 20;
 274    case PIPE_CAP_UMA:
 275       return 0;
 276    }
 277
 278    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 279    return 0;
 280 }
 281
 282 static int
 283 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 284                              enum pipe_shader_cap param)
 285 {
 286    switch (shader) {
 287    case PIPE_SHADER_VERTEX:
 288    case PIPE_SHADER_GEOMETRY:
 289    case PIPE_SHADER_FRAGMENT:
 290       break;
 291    case PIPE_SHADER_COMPUTE:
 292    default:
 293       return 0;
 294    }
 295
 296    switch (param) {
 297    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 298    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 299    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 300    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 301       return 16384;
 302    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 303       return 4;
 304    case PIPE_SHADER_CAP_MAX_INPUTS:
 305       if (shader == PIPE_SHADER_VERTEX)
 306          return 32;
 307       return 15;
 308    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 309       return 16;
 310    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 311       return 65536;
 312    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 313       return NV50_MAX_PIPE_CONSTBUFS;
 314    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 315       return shader != PIPE_SHADER_FRAGMENT;
 316    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 317    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 318    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 319       return 1;
 320    case PIPE_SHADER_CAP_MAX_PREDS:
 321       return 0;
 322    case PIPE_SHADER_CAP_MAX_TEMPS:
 323       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 324    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 325       return 1;
 326    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 327       return 1;
 328    case PIPE_SHADER_CAP_SUBROUTINES:
 329       return 0; /* please inline, or provide function declarations */
 330    case PIPE_SHADER_CAP_INTEGERS:
 331       return 1;
 332    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 333       /* The chip could handle more sampler views than samplers */
 334    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 335       return MIN2(16, PIPE_MAX_SAMPLERS);
 336    case PIPE_SHADER_CAP_PREFERRED_IR:
 337       return PIPE_SHADER_IR_TGSI;
 338    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 339       return 32;
 340    case PIPE_SHADER_CAP_DOUBLES:
 341    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 342    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 343    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 344    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 345    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 346    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 347    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 348       return 0;
 349    default:
 350       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 351       return 0;
 352    }
 353 }
 354
 355 static float
 356 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 357 {
 358    switch (param) {
 359    case PIPE_CAPF_MAX_LINE_WIDTH:
 360    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 361       return 10.0f;
 362    case PIPE_CAPF_MAX_POINT_WIDTH:
 363    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 364       return 64.0f;
 365    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 366       return 16.0f;
 367    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 368       return 4.0f;
 369    case PIPE_CAPF_GUARD_BAND_LEFT:
 370    case PIPE_CAPF_GUARD_BAND_TOP:
 371       return 0.0f;
 372    case PIPE_CAPF_GUARD_BAND_RIGHT:
 373    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 374       return 0.0f; /* that or infinity */
 375    }
 376
 377    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 378    return 0.0f;
 379 }
 380
 381 static int
 382 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 383                               enum pipe_shader_ir ir_type,
 384                               enum pipe_compute_cap param, void *data)
 385 {
 386    struct nv50_screen *screen = nv50_screen(pscreen);
 387
 388 #define RET(x) do {                  \
 389    if (data)                         \
 390       memcpy(data, x, sizeof(x));    \
 391    return sizeof(x);                 \
 392 } while (0)
 393
 394    switch (param) {
 395    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 396       RET((uint64_t []) { 2 });
 397    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 398       RET(((uint64_t []) { 65535, 65535 }));
 399    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 400       RET(((uint64_t []) { 512, 512, 64 }));
 401    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 402       RET((uint64_t []) { 512 });
 403    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 404       RET((uint64_t []) { 1ULL << 32 });
 405    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 406       RET((uint64_t []) { 16 << 10 });
 407    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 408       RET((uint64_t []) { 16 << 10 });
 409    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 410       RET((uint64_t []) { 4096 });
 411    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 412       RET((uint32_t []) { 32 });
 413    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 414       RET((uint64_t []) { 1ULL << 40 });
 415    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 416       RET((uint32_t []) { 0 });
 417    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 418       RET((uint32_t []) { screen->mp_count });
 419    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 420       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 421    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 422       RET((uint32_t []) { 32 });
 423    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 424       RET((uint64_t []) { 0 });
 425    default:
 426       return 0;
 427    }
 428
 429 #undef RET
 430 }
 431
 432 static void
 433 nv50_screen_destroy(struct pipe_screen *pscreen)
 434 {
 435    struct nv50_screen *screen = nv50_screen(pscreen);
 436
 437    if (!nouveau_drm_screen_unref(&screen->base))
 438       return;
 439
 440    if (screen->base.fence.current) {
 441       struct nouveau_fence *current = NULL;
 442
 443       /* nouveau_fence_wait will create a new current fence, so wait on the
 444        * _current_ one, and remove both.
 445        */
 446       nouveau_fence_ref(screen->base.fence.current, &current);
 447       nouveau_fence_wait(current, NULL);
 448       nouveau_fence_ref(NULL, &current);
 449       nouveau_fence_ref(NULL, &screen->base.fence.current);
 450    }
 451    if (screen->base.pushbuf)
 452       screen->base.pushbuf->user_priv = NULL;
 453
 454    if (screen->blitter)
 455       nv50_blitter_destroy(screen);
 456    if (screen->pm.prog) {
 457       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 458       nv50_program_destroy(NULL, screen->pm.prog);
 459       FREE(screen->pm.prog);
 460    }
 461
 462    nouveau_bo_ref(NULL, &screen->code);
 463    nouveau_bo_ref(NULL, &screen->tls_bo);
 464    nouveau_bo_ref(NULL, &screen->stack_bo);
 465    nouveau_bo_ref(NULL, &screen->txc);
 466    nouveau_bo_ref(NULL, &screen->uniforms);
 467    nouveau_bo_ref(NULL, &screen->fence.bo);
 468
 469    nouveau_heap_destroy(&screen->vp_code_heap);
 470    nouveau_heap_destroy(&screen->gp_code_heap);
 471    nouveau_heap_destroy(&screen->fp_code_heap);
 472
 473    FREE(screen->tic.entries);
 474
 475    nouveau_object_del(&screen->tesla);
 476    nouveau_object_del(&screen->eng2d);
 477    nouveau_object_del(&screen->m2mf);
 478    nouveau_object_del(&screen->compute);
 479    nouveau_object_del(&screen->sync);
 480
 481    nouveau_screen_fini(&screen->base);
 482
 483    FREE(screen);
 484 }
 485
 486 static void
 487 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 488 {
 489    struct nv50_screen *screen = nv50_screen(pscreen);
 490    struct nouveau_pushbuf *push = screen->base.pushbuf;
 491
 492    /* we need to do it after possible flush in MARK_RING */
 493    *sequence = ++screen->base.fence.sequence;
 494
 495    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 496    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 497    PUSH_DATAh(push, screen->fence.bo->offset);
 498    PUSH_DATA (push, screen->fence.bo->offset);
 499    PUSH_DATA (push, *sequence);
 500    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 501                     NV50_3D_QUERY_GET_UNK4 |
 502                     NV50_3D_QUERY_GET_UNIT_CROP |
 503                     NV50_3D_QUERY_GET_TYPE_QUERY |
 504                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 505                     NV50_3D_QUERY_GET_SHORT);
 506 }
 507
 508 static u32
 509 nv50_screen_fence_update(struct pipe_screen *pscreen)
 510 {
 511    return nv50_screen(pscreen)->fence.map[0];
 512 }
 513
 514 static void
 515 nv50_screen_init_hwctx(struct nv50_screen *screen)
 516 {
 517    struct nouveau_pushbuf *push = screen->base.pushbuf;
 518    struct nv04_fifo *fifo;
 519    unsigned i;
 520
 521    fifo = (struct nv04_fifo *)screen->base.channel->data;
 522
 523    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 524    PUSH_DATA (push, screen->m2mf->handle);
 525    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 526    PUSH_DATA (push, screen->sync->handle);
 527    PUSH_DATA (push, fifo->vram);
 528    PUSH_DATA (push, fifo->vram);
 529
 530    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 531    PUSH_DATA (push, screen->eng2d->handle);
 532    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 533    PUSH_DATA (push, screen->sync->handle);
 534    PUSH_DATA (push, fifo->vram);
 535    PUSH_DATA (push, fifo->vram);
 536    PUSH_DATA (push, fifo->vram);
 537    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 538    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 539    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 540    PUSH_DATA (push, 0);
 541    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 542    PUSH_DATA (push, 0);
 543    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 544    PUSH_DATA (push, 1);
 545    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 546    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 547
 548    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 549    PUSH_DATA (push, screen->tesla->handle);
 550
 551    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 552    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 553
 554    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 555    PUSH_DATA (push, screen->sync->handle);
 556    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 557    for (i = 0; i < 11; ++i)
 558       PUSH_DATA(push, fifo->vram);
 559    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 560    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 561       PUSH_DATA(push, fifo->vram);
 562
 563    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 564    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 565    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 566    PUSH_DATA (push, 0xf);
 567
 568    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 569       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 570       PUSH_DATA (push, 0x18);
 571    }
 572
 573    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 574    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 575
 576    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 577    for (i = 0; i < 8; ++i)
 578       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 579
 580    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 581    PUSH_DATA (push, 1);
 582
 583    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 584    PUSH_DATA (push, 0);
 585    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 586    PUSH_DATA (push, 0);
 587    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 588    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 589    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 590    PUSH_DATA (push, 0);
 591    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 592    PUSH_DATA (push, 1);
 593    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 594    PUSH_DATA (push, 1);
 595
 596    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 597       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 598       PUSH_DATA (push, 0);
 599    }
 600
 601    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 602    PUSH_DATA (push, 0);
 603    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 604    PUSH_DATA (push, 0);
 605    PUSH_DATA (push, 0);
 606    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 607    PUSH_DATA (push, 0x3f);
 608
 609    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 610    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 611    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 612
 613    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 614    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 615    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 616
 617    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 618    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 619    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 620
 621    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 622    PUSH_DATAh(push, screen->tls_bo->offset);
 623    PUSH_DATA (push, screen->tls_bo->offset);
 624    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 625
 626    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 627    PUSH_DATAh(push, screen->stack_bo->offset);
 628    PUSH_DATA (push, screen->stack_bo->offset);
 629    PUSH_DATA (push, 4);
 630
 631    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 632    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 633    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 634    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 635
 636    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 637    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 638    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 639    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 640
 641    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 642    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 643    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 644    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 645
 646    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 647    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 648    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 649    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 650
 651    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 652    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 653    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 654    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 655
 656    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 657    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 658    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 659    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 660    PUSH_DATAf(push, 0.0f);
 661    PUSH_DATAf(push, 0.0f);
 662    PUSH_DATAf(push, 0.0f);
 663    PUSH_DATAf(push, 0.0f);
 664    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 665    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 666    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 667
 668    nv50_upload_ms_info(push);
 669
 670    /* max TIC (bits 4:8) & TSC bindings, per program type */
 671    for (i = 0; i < 3; ++i) {
 672       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 673       PUSH_DATA (push, 0x54);
 674    }
 675
 676    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 677    PUSH_DATAh(push, screen->txc->offset);
 678    PUSH_DATA (push, screen->txc->offset);
 679    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 680
 681    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 682    PUSH_DATAh(push, screen->txc->offset + 65536);
 683    PUSH_DATA (push, screen->txc->offset + 65536);
 684    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 685
 686    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 687    PUSH_DATA (push, 0);
 688
 689    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 690    PUSH_DATA (push, 0);
 691    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 692    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 693    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 694    for (i = 0; i < 8 * 2; ++i)
 695       PUSH_DATA(push, 0);
 696    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 697    PUSH_DATA (push, 0);
 698
 699    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 700    PUSH_DATA (push, 1);
 701    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 702       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 703       PUSH_DATAf(push, 0.0f);
 704       PUSH_DATAf(push, 1.0f);
 705       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 706       PUSH_DATA (push, 8192 << 16);
 707       PUSH_DATA (push, 8192 << 16);
 708    }
 709
 710    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 711 #ifdef NV50_SCISSORS_CLIPPING
 712    PUSH_DATA (push, 0x0000);
 713 #else
 714    PUSH_DATA (push, 0x1080);
 715 #endif
 716
 717    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 718    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 719
 720    /* We use scissors instead of exact view volume clipping,
 721     * so they're always enabled.
 722     */
 723    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 724       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 725       PUSH_DATA (push, 1);
 726       PUSH_DATA (push, 8192 << 16);
 727       PUSH_DATA (push, 8192 << 16);
 728    }
 729
 730    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 731    PUSH_DATA (push, 1);
 732    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 733    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 734    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 735    PUSH_DATA (push, 0x11111111);
 736    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 737    PUSH_DATA (push, 1);
 738
 739    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 740    PUSH_DATA (push, 0);
 741    if (screen->base.class_3d >= NV84_3D_CLASS) {
 742       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 743       PUSH_DATA (push, 0);
 744    }
 745
 746    PUSH_KICK (push);
 747 }
 748
 749 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 750       uint64_t *tls_size)
 751 {
 752    struct nouveau_device *dev = screen->base.device;
 753    int ret;
 754
 755    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 756          ONE_TEMP_SIZE;
 757    if (nouveau_mesa_debug)
 758       debug_printf("allocating space for %u temps\n",
 759             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 760    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 761          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 762
 763    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 764                         *tls_size, NULL, &screen->tls_bo);
 765    if (ret) {
 766       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 767       return ret;
 768    }
 769
 770    return 0;
 771 }
 772
 773 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 774 {
 775    struct nouveau_pushbuf *push = screen->base.pushbuf;
 776    int ret;
 777    uint64_t tls_size;
 778
 779    if (tls_space < screen->cur_tls_space)
 780       return 0;
 781    if (tls_space > screen->max_tls_space) {
 782       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 783        * LOCAL_WARPS_NO_CLAMP) */
 784       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 785             (unsigned)(tls_space / ONE_TEMP_SIZE),
 786             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 787       return -ENOMEM;
 788    }
 789
 790    nouveau_bo_ref(NULL, &screen->tls_bo);
 791    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 792    if (ret)
 793       return ret;
 794
 795    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 796    PUSH_DATAh(push, screen->tls_bo->offset);
 797    PUSH_DATA (push, screen->tls_bo->offset);
 798    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 799
 800    return 1;
 801 }
 802
 803 struct nouveau_screen *
 804 nv50_screen_create(struct nouveau_device *dev)
 805 {
 806    struct nv50_screen *screen;
 807    struct pipe_screen *pscreen;
 808    struct nouveau_object *chan;
 809    uint64_t value;
 810    uint32_t tesla_class;
 811    unsigned stack_size;
 812    int ret;
 813
 814    screen = CALLOC_STRUCT(nv50_screen);
 815    if (!screen)
 816       return NULL;
 817    pscreen = &screen->base.base;
 818    pscreen->destroy = nv50_screen_destroy;
 819
 820    ret = nouveau_screen_init(&screen->base, dev);
 821    if (ret) {
 822       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 823       goto fail;
 824    }
 825
 826    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 827     *  admit them to VRAM.
 828     */
 829    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 830       PIPE_BIND_VERTEX_BUFFER;
 831    screen->base.sysmem_bindings |=
 832       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 833
 834    screen->base.pushbuf->user_priv = screen;
 835    screen->base.pushbuf->rsvd_kick = 5;
 836
 837    chan = screen->base.channel;
 838
 839    pscreen->context_create = nv50_create;
 840    pscreen->is_format_supported = nv50_screen_is_format_supported;
 841    pscreen->get_param = nv50_screen_get_param;
 842    pscreen->get_shader_param = nv50_screen_get_shader_param;
 843    pscreen->get_paramf = nv50_screen_get_paramf;
 844    pscreen->get_compute_param = nv50_screen_get_compute_param;
 845    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 846    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 847
 848    nv50_screen_init_resource_functions(pscreen);
 849
 850    if (screen->base.device->chipset < 0x84 ||
 851        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 852       /* PMPEG */
 853       nouveau_screen_init_vdec(&screen->base);
 854    } else if (screen->base.device->chipset < 0x98 ||
 855               screen->base.device->chipset == 0xa0) {
 856       /* VP2 */
 857       screen->base.base.get_video_param = nv84_screen_get_video_param;
 858       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 859    } else {
 860       /* VP3/4 */
 861       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 862       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 863    }
 864
 865    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 866                         NULL, &screen->fence.bo);
 867    if (ret) {
 868       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 869       goto fail;
 870    }
 871
 872    nouveau_bo_map(screen->fence.bo, 0, NULL);
 873    screen->fence.map = screen->fence.bo->map;
 874    screen->base.fence.emit = nv50_screen_fence_emit;
 875    screen->base.fence.update = nv50_screen_fence_update;
 876
 877    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 878                             &(struct nv04_notify){ .length = 32 },
 879                             sizeof(struct nv04_notify), &screen->sync);
 880    if (ret) {
 881       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 882       goto fail;
 883    }
 884
 885    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 886                             NULL, 0, &screen->m2mf);
 887    if (ret) {
 888       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 889       goto fail;
 890    }
 891
 892    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 893                             NULL, 0, &screen->eng2d);
 894    if (ret) {
 895       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 896       goto fail;
 897    }
 898
 899    switch (dev->chipset & 0xf0) {
 900    case 0x50:
 901       tesla_class = NV50_3D_CLASS;
 902       break;
 903    case 0x80:
 904    case 0x90:
 905       tesla_class = NV84_3D_CLASS;
 906       break;
 907    case 0xa0:
 908       switch (dev->chipset) {
 909       case 0xa0:
 910       case 0xaa:
 911       case 0xac:
 912          tesla_class = NVA0_3D_CLASS;
 913          break;
 914       case 0xaf:
 915          tesla_class = NVAF_3D_CLASS;
 916          break;
 917       default:
 918          tesla_class = NVA3_3D_CLASS;
 919          break;
 920       }
 921       break;
 922    default:
 923       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 924       goto fail;
 925    }
 926    screen->base.class_3d = tesla_class;
 927
 928    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 929                             NULL, 0, &screen->tesla);
 930    if (ret) {
 931       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 932       goto fail;
 933    }
 934
 935    /* This over-allocates by a page. The GP, which would execute at the end of
 936     * the last page, would trigger faults. The going theory is that it
 937     * prefetches up to a certain amount.
 938     */
 939    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 940                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 941                         NULL, &screen->code);
 942    if (ret) {
 943       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 944       goto fail;
 945    }
 946
 947    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 948    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 949    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 950
 951    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 952
 953    screen->TPs = util_bitcount(value & 0xffff);
 954    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 955
 956    screen->mp_count = screen->TPs * screen->MPsInTP;
 957
 958    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 959          STACK_WARPS_ALLOC * 64 * 8;
 960
 961    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 962                         &screen->stack_bo);
 963    if (ret) {
 964       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 965       goto fail;
 966    }
 967
 968    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 969          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 970          ONE_TEMP_SIZE;
 971    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 972    screen->max_tls_space /= 2; /* half of vram */
 973
 974    /* hw can address max 64 KiB */
 975    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 976
 977    uint64_t tls_size;
 978    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 979    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 980    if (ret)
 981       goto fail;
 982
 983    if (nouveau_mesa_debug)
 984       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 985             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 986
 987    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 988                         &screen->uniforms);
 989    if (ret) {
 990       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 991       goto fail;
 992    }
 993
 994    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 995                         &screen->txc);
 996    if (ret) {
 997       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 998       goto fail;
 999    }
1000
1001    screen->tic.entries = CALLOC(4096, sizeof(void *));
1002    screen->tsc.entries = screen->tic.entries + 2048;
1003
1004    if (!nv50_blitter_create(screen))
1005       goto fail;
1006
1007    nv50_screen_init_hwctx(screen);
1008
1009    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1010    if (ret) {
1011       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1012       goto fail;
1013    }
1014
1015    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1016
1017    return &screen->base;
1018
1019 fail:
1020    screen->base.base.context_create = NULL;
1021    return &screen->base;
1022 }
1023
1024 int
1025 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1026 {
1027    int i = screen->tic.next;
1028
1029    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1030       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1031
1032    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1033
1034    if (screen->tic.entries[i])
1035       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1036
1037    screen->tic.entries[i] = entry;
1038    return i;
1039 }
1040
1041 int
1042 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1043 {
1044    int i = screen->tsc.next;
1045
1046    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1047       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1048
1049    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1050
1051    if (screen->tsc.entries[i])
1052       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1053
1054    screen->tsc.entries[i] = entry;
1055    return i;
1056 }