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gallium: Add PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <errno.h>
24 #include <xf86drm.h>
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nv_object.xml.h"
36
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
41
42 #define THREADS_IN_WARP 32
43
44 static boolean
45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
46 enum pipe_format format,
47 enum pipe_texture_target target,
48 unsigned sample_count,
49 unsigned bindings)
50 {
51 if (sample_count > 8)
52 return false;
53 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
54 return false;
55 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
56 return false;
57
58 if (!util_format_is_supported(format, bindings))
59 return false;
60
61 switch (format) {
62 case PIPE_FORMAT_Z16_UNORM:
63 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
64 return false;
65 break;
66 default:
67 break;
68 }
69
70 if (bindings & PIPE_BIND_LINEAR)
71 if (util_format_is_depth_or_stencil(format) ||
72 (target != PIPE_TEXTURE_1D &&
73 target != PIPE_TEXTURE_2D &&
74 target != PIPE_TEXTURE_RECT) ||
75 sample_count > 1)
76 return false;
77
78 /* transfers & shared are always supported */
79 bindings &= ~(PIPE_BIND_TRANSFER_READ |
80 PIPE_BIND_TRANSFER_WRITE |
81 PIPE_BIND_LINEAR |
82 PIPE_BIND_SHARED);
83
84 return (( nv50_format_table[format].usage |
85 nv50_vertex_format[format].usage) & bindings) == bindings;
86 }
87
88 static int
89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
90 {
91 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
92 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
93
94 switch (param) {
95 /* non-boolean caps */
96 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
97 return 14;
98 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
99 return 12;
100 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
101 return 14;
102 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
103 return 512;
104 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
105 case PIPE_CAP_MIN_TEXEL_OFFSET:
106 return -8;
107 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
108 case PIPE_CAP_MAX_TEXEL_OFFSET:
109 return 7;
110 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
111 return 128 * 1024 * 1024;
112 case PIPE_CAP_GLSL_FEATURE_LEVEL:
113 return 330;
114 case PIPE_CAP_MAX_RENDER_TARGETS:
115 return 8;
116 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
117 return 1;
118 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
119 return 4;
120 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
121 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
122 return 64;
123 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
124 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
125 return 1024;
126 case PIPE_CAP_MAX_VERTEX_STREAMS:
127 return 1;
128 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
129 return 2048;
130 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
131 return 256;
132 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
133 return 16; /* 256 for binding as RT, but that's not possible in GL */
134 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
135 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
136 case PIPE_CAP_MAX_VIEWPORTS:
137 return NV50_MAX_VIEWPORTS;
138 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
139 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
140 case PIPE_CAP_ENDIANNESS:
141 return PIPE_ENDIAN_LITTLE;
142 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
143 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
144
145 /* supported caps */
146 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
147 case PIPE_CAP_TEXTURE_SWIZZLE:
148 case PIPE_CAP_TEXTURE_SHADOW_MAP:
149 case PIPE_CAP_NPOT_TEXTURES:
150 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
151 case PIPE_CAP_ANISOTROPIC_FILTER:
152 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
153 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
154 case PIPE_CAP_TWO_SIDED_STENCIL:
155 case PIPE_CAP_DEPTH_CLIP_DISABLE:
156 case PIPE_CAP_POINT_SPRITE:
157 case PIPE_CAP_SM3:
158 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
159 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
160 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
161 case PIPE_CAP_QUERY_TIMESTAMP:
162 case PIPE_CAP_QUERY_TIME_ELAPSED:
163 case PIPE_CAP_OCCLUSION_QUERY:
164 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
165 case PIPE_CAP_INDEP_BLEND_ENABLE:
166 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
167 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
168 case PIPE_CAP_PRIMITIVE_RESTART:
169 case PIPE_CAP_TGSI_INSTANCEID:
170 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
171 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
172 case PIPE_CAP_CONDITIONAL_RENDER:
173 case PIPE_CAP_TEXTURE_BARRIER:
174 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
175 case PIPE_CAP_START_INSTANCE:
176 case PIPE_CAP_USER_CONSTANT_BUFFERS:
177 case PIPE_CAP_USER_INDEX_BUFFERS:
178 case PIPE_CAP_USER_VERTEX_BUFFERS:
179 case PIPE_CAP_TEXTURE_MULTISAMPLE:
180 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
181 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
182 case PIPE_CAP_SAMPLER_VIEW_TARGET:
183 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
184 case PIPE_CAP_CLIP_HALFZ:
185 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
186 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
187 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
188 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
189 case PIPE_CAP_DEPTH_BOUNDS_TEST:
190 case PIPE_CAP_TGSI_TXQS:
191 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
192 case PIPE_CAP_SHAREABLE_SHADERS:
193 case PIPE_CAP_CLEAR_TEXTURE:
194 case PIPE_CAP_COMPUTE:
195 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
196 return 1;
197 case PIPE_CAP_SEAMLESS_CUBE_MAP:
198 return 1; /* class_3d >= NVA0_3D_CLASS; */
199 /* supported on nva0+ */
200 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
201 return class_3d >= NVA0_3D_CLASS;
202 /* supported on nva3+ */
203 case PIPE_CAP_CUBE_MAP_ARRAY:
204 case PIPE_CAP_INDEP_BLEND_FUNC:
205 case PIPE_CAP_TEXTURE_QUERY_LOD:
206 case PIPE_CAP_SAMPLE_SHADING:
207 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
208 return class_3d >= NVA3_3D_CLASS;
209
210 /* unsupported caps */
211 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
212 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
213 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
214 case PIPE_CAP_SHADER_STENCIL_EXPORT:
215 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
216 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
217 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
218 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
219 case PIPE_CAP_TGSI_TEXCOORD:
220 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
221 case PIPE_CAP_TEXTURE_GATHER_SM5:
222 case PIPE_CAP_FAKE_SW_MSAA:
223 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
224 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
225 case PIPE_CAP_DRAW_INDIRECT:
226 case PIPE_CAP_MULTI_DRAW_INDIRECT:
227 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
228 case PIPE_CAP_VERTEXID_NOBASE:
229 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
230 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
231 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
232 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
233 case PIPE_CAP_DRAW_PARAMETERS:
234 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
235 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
236 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
237 case PIPE_CAP_INVALIDATE_BUFFER:
238 case PIPE_CAP_GENERATE_MIPMAP:
239 case PIPE_CAP_STRING_MARKER:
240 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
241 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
242 case PIPE_CAP_QUERY_BUFFER_OBJECT:
243 case PIPE_CAP_QUERY_MEMORY_INFO:
244 case PIPE_CAP_PCI_GROUP:
245 case PIPE_CAP_PCI_BUS:
246 case PIPE_CAP_PCI_DEVICE:
247 case PIPE_CAP_PCI_FUNCTION:
248 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
249 return 0;
250
251 case PIPE_CAP_VENDOR_ID:
252 return 0x10de;
253 case PIPE_CAP_DEVICE_ID: {
254 uint64_t device_id;
255 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
256 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
257 return -1;
258 }
259 return device_id;
260 }
261 case PIPE_CAP_ACCELERATED:
262 return 1;
263 case PIPE_CAP_VIDEO_MEMORY:
264 return dev->vram_size >> 20;
265 case PIPE_CAP_UMA:
266 return 0;
267 }
268
269 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
270 return 0;
271 }
272
273 static int
274 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
275 enum pipe_shader_cap param)
276 {
277 switch (shader) {
278 case PIPE_SHADER_VERTEX:
279 case PIPE_SHADER_GEOMETRY:
280 case PIPE_SHADER_FRAGMENT:
281 break;
282 case PIPE_SHADER_COMPUTE:
283 default:
284 return 0;
285 }
286
287 switch (param) {
288 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
289 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
290 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
291 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
292 return 16384;
293 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
294 return 4;
295 case PIPE_SHADER_CAP_MAX_INPUTS:
296 if (shader == PIPE_SHADER_VERTEX)
297 return 32;
298 return 15;
299 case PIPE_SHADER_CAP_MAX_OUTPUTS:
300 return 16;
301 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
302 return 65536;
303 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
304 return NV50_MAX_PIPE_CONSTBUFS;
305 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
306 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
307 return shader != PIPE_SHADER_FRAGMENT;
308 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
309 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
310 return 1;
311 case PIPE_SHADER_CAP_MAX_PREDS:
312 return 0;
313 case PIPE_SHADER_CAP_MAX_TEMPS:
314 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
315 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
316 return 1;
317 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
318 return 1;
319 case PIPE_SHADER_CAP_SUBROUTINES:
320 return 0; /* please inline, or provide function declarations */
321 case PIPE_SHADER_CAP_INTEGERS:
322 return 1;
323 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
324 /* The chip could handle more sampler views than samplers */
325 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
326 return MIN2(16, PIPE_MAX_SAMPLERS);
327 case PIPE_SHADER_CAP_DOUBLES:
328 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
329 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
330 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
331 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
332 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
333 case PIPE_SHADER_CAP_SUPPORTED_IRS:
334 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
335 return 0;
336 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
337 return 32;
338 default:
339 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
340 return 0;
341 }
342 }
343
344 static float
345 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
346 {
347 switch (param) {
348 case PIPE_CAPF_MAX_LINE_WIDTH:
349 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
350 return 10.0f;
351 case PIPE_CAPF_MAX_POINT_WIDTH:
352 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
353 return 64.0f;
354 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
355 return 16.0f;
356 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
357 return 4.0f;
358 case PIPE_CAPF_GUARD_BAND_LEFT:
359 case PIPE_CAPF_GUARD_BAND_TOP:
360 return 0.0f;
361 case PIPE_CAPF_GUARD_BAND_RIGHT:
362 case PIPE_CAPF_GUARD_BAND_BOTTOM:
363 return 0.0f; /* that or infinity */
364 }
365
366 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
367 return 0.0f;
368 }
369
370 static int
371 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
372 enum pipe_shader_ir ir_type,
373 enum pipe_compute_cap param, void *data)
374 {
375 struct nv50_screen *screen = nv50_screen(pscreen);
376
377 #define RET(x) do { \
378 if (data) \
379 memcpy(data, x, sizeof(x)); \
380 return sizeof(x); \
381 } while (0)
382
383 switch (param) {
384 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
385 RET((uint64_t []) { 2 });
386 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
387 RET(((uint64_t []) { 65535, 65535 }));
388 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
389 RET(((uint64_t []) { 512, 512, 64 }));
390 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
391 RET((uint64_t []) { 512 });
392 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
393 RET((uint64_t []) { 1ULL << 32 });
394 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
395 RET((uint64_t []) { 16 << 10 });
396 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
397 RET((uint64_t []) { 16 << 10 });
398 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
399 RET((uint64_t []) { 4096 });
400 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
401 RET((uint32_t []) { 32 });
402 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
403 RET((uint64_t []) { 1ULL << 40 });
404 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
405 RET((uint32_t []) { 0 });
406 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
407 RET((uint32_t []) { screen->mp_count });
408 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
409 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
410 default:
411 return 0;
412 }
413
414 #undef RET
415 }
416
417 static void
418 nv50_screen_destroy(struct pipe_screen *pscreen)
419 {
420 struct nv50_screen *screen = nv50_screen(pscreen);
421
422 if (!nouveau_drm_screen_unref(&screen->base))
423 return;
424
425 if (screen->base.fence.current) {
426 struct nouveau_fence *current = NULL;
427
428 /* nouveau_fence_wait will create a new current fence, so wait on the
429 * _current_ one, and remove both.
430 */
431 nouveau_fence_ref(screen->base.fence.current, &current);
432 nouveau_fence_wait(current, NULL);
433 nouveau_fence_ref(NULL, &current);
434 nouveau_fence_ref(NULL, &screen->base.fence.current);
435 }
436 if (screen->base.pushbuf)
437 screen->base.pushbuf->user_priv = NULL;
438
439 if (screen->blitter)
440 nv50_blitter_destroy(screen);
441 if (screen->pm.prog) {
442 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
443 nv50_program_destroy(NULL, screen->pm.prog);
444 FREE(screen->pm.prog);
445 }
446
447 nouveau_bo_ref(NULL, &screen->code);
448 nouveau_bo_ref(NULL, &screen->tls_bo);
449 nouveau_bo_ref(NULL, &screen->stack_bo);
450 nouveau_bo_ref(NULL, &screen->txc);
451 nouveau_bo_ref(NULL, &screen->uniforms);
452 nouveau_bo_ref(NULL, &screen->fence.bo);
453
454 nouveau_heap_destroy(&screen->vp_code_heap);
455 nouveau_heap_destroy(&screen->gp_code_heap);
456 nouveau_heap_destroy(&screen->fp_code_heap);
457
458 FREE(screen->tic.entries);
459
460 nouveau_object_del(&screen->tesla);
461 nouveau_object_del(&screen->eng2d);
462 nouveau_object_del(&screen->m2mf);
463 nouveau_object_del(&screen->compute);
464 nouveau_object_del(&screen->sync);
465
466 nouveau_screen_fini(&screen->base);
467
468 FREE(screen);
469 }
470
471 static void
472 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
473 {
474 struct nv50_screen *screen = nv50_screen(pscreen);
475 struct nouveau_pushbuf *push = screen->base.pushbuf;
476
477 /* we need to do it after possible flush in MARK_RING */
478 *sequence = ++screen->base.fence.sequence;
479
480 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
481 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
482 PUSH_DATAh(push, screen->fence.bo->offset);
483 PUSH_DATA (push, screen->fence.bo->offset);
484 PUSH_DATA (push, *sequence);
485 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
486 NV50_3D_QUERY_GET_UNK4 |
487 NV50_3D_QUERY_GET_UNIT_CROP |
488 NV50_3D_QUERY_GET_TYPE_QUERY |
489 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
490 NV50_3D_QUERY_GET_SHORT);
491 }
492
493 static u32
494 nv50_screen_fence_update(struct pipe_screen *pscreen)
495 {
496 return nv50_screen(pscreen)->fence.map[0];
497 }
498
499 static void
500 nv50_screen_init_hwctx(struct nv50_screen *screen)
501 {
502 struct nouveau_pushbuf *push = screen->base.pushbuf;
503 struct nv04_fifo *fifo;
504 unsigned i;
505
506 fifo = (struct nv04_fifo *)screen->base.channel->data;
507
508 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
509 PUSH_DATA (push, screen->m2mf->handle);
510 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
511 PUSH_DATA (push, screen->sync->handle);
512 PUSH_DATA (push, fifo->vram);
513 PUSH_DATA (push, fifo->vram);
514
515 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
516 PUSH_DATA (push, screen->eng2d->handle);
517 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
518 PUSH_DATA (push, screen->sync->handle);
519 PUSH_DATA (push, fifo->vram);
520 PUSH_DATA (push, fifo->vram);
521 PUSH_DATA (push, fifo->vram);
522 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
523 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
524 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
525 PUSH_DATA (push, 0);
526 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
527 PUSH_DATA (push, 0);
528 BEGIN_NV04(push, SUBC_2D(0x0888), 1);
529 PUSH_DATA (push, 1);
530 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
531 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
532
533 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
534 PUSH_DATA (push, screen->tesla->handle);
535
536 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
537 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
538
539 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
540 PUSH_DATA (push, screen->sync->handle);
541 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
542 for (i = 0; i < 11; ++i)
543 PUSH_DATA(push, fifo->vram);
544 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
545 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
546 PUSH_DATA(push, fifo->vram);
547
548 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
549 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
550 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
551 PUSH_DATA (push, 0xf);
552
553 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
554 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
555 PUSH_DATA (push, 0x18);
556 }
557
558 BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
559 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
560
561 BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
562 for (i = 0; i < 8; ++i)
563 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
564
565 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
566 PUSH_DATA (push, 1);
567
568 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
569 PUSH_DATA (push, 0);
570 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
571 PUSH_DATA (push, 0);
572 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
573 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
574 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
575 PUSH_DATA (push, 0);
576 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
577 PUSH_DATA (push, 1);
578 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
579 PUSH_DATA (push, 1);
580
581 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
582 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
583 PUSH_DATA (push, 0);
584 }
585
586 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
587 PUSH_DATA (push, 0);
588 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
589 PUSH_DATA (push, 0);
590 PUSH_DATA (push, 0);
591 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
592 PUSH_DATA (push, 0x3f);
593
594 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
595 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
596 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
597
598 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
599 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
600 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
601
602 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
603 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
604 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
605
606 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
607 PUSH_DATAh(push, screen->tls_bo->offset);
608 PUSH_DATA (push, screen->tls_bo->offset);
609 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
610
611 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
612 PUSH_DATAh(push, screen->stack_bo->offset);
613 PUSH_DATA (push, screen->stack_bo->offset);
614 PUSH_DATA (push, 4);
615
616 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
617 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
618 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
619 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
620
621 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
622 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
623 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
624 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
625
626 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
627 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
628 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
629 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
630
631 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
632 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
633 PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
634 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
635
636 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
637 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
638 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
639 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
640
641 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
642 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
643 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
644 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
645 PUSH_DATAf(push, 0.0f);
646 PUSH_DATAf(push, 0.0f);
647 PUSH_DATAf(push, 0.0f);
648 PUSH_DATAf(push, 0.0f);
649 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
650 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
651 PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
652
653 nv50_upload_ms_info(push);
654
655 /* max TIC (bits 4:8) & TSC bindings, per program type */
656 for (i = 0; i < 3; ++i) {
657 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
658 PUSH_DATA (push, 0x54);
659 }
660
661 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
662 PUSH_DATAh(push, screen->txc->offset);
663 PUSH_DATA (push, screen->txc->offset);
664 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
665
666 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
667 PUSH_DATAh(push, screen->txc->offset + 65536);
668 PUSH_DATA (push, screen->txc->offset + 65536);
669 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
670
671 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
672 PUSH_DATA (push, 0);
673
674 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
675 PUSH_DATA (push, 0);
676 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
677 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
678 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
679 for (i = 0; i < 8 * 2; ++i)
680 PUSH_DATA(push, 0);
681 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
682 PUSH_DATA (push, 0);
683
684 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
685 PUSH_DATA (push, 1);
686 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
687 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
688 PUSH_DATAf(push, 0.0f);
689 PUSH_DATAf(push, 1.0f);
690 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
691 PUSH_DATA (push, 8192 << 16);
692 PUSH_DATA (push, 8192 << 16);
693 }
694
695 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
696 #ifdef NV50_SCISSORS_CLIPPING
697 PUSH_DATA (push, 0x0000);
698 #else
699 PUSH_DATA (push, 0x1080);
700 #endif
701
702 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
703 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
704
705 /* We use scissors instead of exact view volume clipping,
706 * so they're always enabled.
707 */
708 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
709 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
710 PUSH_DATA (push, 1);
711 PUSH_DATA (push, 8192 << 16);
712 PUSH_DATA (push, 8192 << 16);
713 }
714
715 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
716 PUSH_DATA (push, 1);
717 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
718 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
719 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
720 PUSH_DATA (push, 0x11111111);
721 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
722 PUSH_DATA (push, 1);
723
724 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
725 PUSH_DATA (push, 0);
726 if (screen->base.class_3d >= NV84_3D_CLASS) {
727 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
728 PUSH_DATA (push, 0);
729 }
730
731 PUSH_KICK (push);
732 }
733
734 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
735 uint64_t *tls_size)
736 {
737 struct nouveau_device *dev = screen->base.device;
738 int ret;
739
740 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
741 ONE_TEMP_SIZE;
742 if (nouveau_mesa_debug)
743 debug_printf("allocating space for %u temps\n",
744 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
745 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
746 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
747
748 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
749 *tls_size, NULL, &screen->tls_bo);
750 if (ret) {
751 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
752 return ret;
753 }
754
755 return 0;
756 }
757
758 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
759 {
760 struct nouveau_pushbuf *push = screen->base.pushbuf;
761 int ret;
762 uint64_t tls_size;
763
764 if (tls_space < screen->cur_tls_space)
765 return 0;
766 if (tls_space > screen->max_tls_space) {
767 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
768 * LOCAL_WARPS_NO_CLAMP) */
769 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
770 (unsigned)(tls_space / ONE_TEMP_SIZE),
771 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
772 return -ENOMEM;
773 }
774
775 nouveau_bo_ref(NULL, &screen->tls_bo);
776 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
777 if (ret)
778 return ret;
779
780 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
781 PUSH_DATAh(push, screen->tls_bo->offset);
782 PUSH_DATA (push, screen->tls_bo->offset);
783 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
784
785 return 1;
786 }
787
788 struct nouveau_screen *
789 nv50_screen_create(struct nouveau_device *dev)
790 {
791 struct nv50_screen *screen;
792 struct pipe_screen *pscreen;
793 struct nouveau_object *chan;
794 uint64_t value;
795 uint32_t tesla_class;
796 unsigned stack_size;
797 int ret;
798
799 screen = CALLOC_STRUCT(nv50_screen);
800 if (!screen)
801 return NULL;
802 pscreen = &screen->base.base;
803 pscreen->destroy = nv50_screen_destroy;
804
805 ret = nouveau_screen_init(&screen->base, dev);
806 if (ret) {
807 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
808 goto fail;
809 }
810
811 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
812 * admit them to VRAM.
813 */
814 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
815 PIPE_BIND_VERTEX_BUFFER;
816 screen->base.sysmem_bindings |=
817 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
818
819 screen->base.pushbuf->user_priv = screen;
820 screen->base.pushbuf->rsvd_kick = 5;
821
822 chan = screen->base.channel;
823
824 pscreen->context_create = nv50_create;
825 pscreen->is_format_supported = nv50_screen_is_format_supported;
826 pscreen->get_param = nv50_screen_get_param;
827 pscreen->get_shader_param = nv50_screen_get_shader_param;
828 pscreen->get_paramf = nv50_screen_get_paramf;
829 pscreen->get_compute_param = nv50_screen_get_compute_param;
830 pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
831 pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
832
833 nv50_screen_init_resource_functions(pscreen);
834
835 if (screen->base.device->chipset < 0x84 ||
836 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
837 /* PMPEG */
838 nouveau_screen_init_vdec(&screen->base);
839 } else if (screen->base.device->chipset < 0x98 ||
840 screen->base.device->chipset == 0xa0) {
841 /* VP2 */
842 screen->base.base.get_video_param = nv84_screen_get_video_param;
843 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
844 } else {
845 /* VP3/4 */
846 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
847 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
848 }
849
850 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
851 NULL, &screen->fence.bo);
852 if (ret) {
853 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
854 goto fail;
855 }
856
857 nouveau_bo_map(screen->fence.bo, 0, NULL);
858 screen->fence.map = screen->fence.bo->map;
859 screen->base.fence.emit = nv50_screen_fence_emit;
860 screen->base.fence.update = nv50_screen_fence_update;
861
862 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
863 &(struct nv04_notify){ .length = 32 },
864 sizeof(struct nv04_notify), &screen->sync);
865 if (ret) {
866 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
867 goto fail;
868 }
869
870 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
871 NULL, 0, &screen->m2mf);
872 if (ret) {
873 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
874 goto fail;
875 }
876
877 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
878 NULL, 0, &screen->eng2d);
879 if (ret) {
880 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
881 goto fail;
882 }
883
884 switch (dev->chipset & 0xf0) {
885 case 0x50:
886 tesla_class = NV50_3D_CLASS;
887 break;
888 case 0x80:
889 case 0x90:
890 tesla_class = NV84_3D_CLASS;
891 break;
892 case 0xa0:
893 switch (dev->chipset) {
894 case 0xa0:
895 case 0xaa:
896 case 0xac:
897 tesla_class = NVA0_3D_CLASS;
898 break;
899 case 0xaf:
900 tesla_class = NVAF_3D_CLASS;
901 break;
902 default:
903 tesla_class = NVA3_3D_CLASS;
904 break;
905 }
906 break;
907 default:
908 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
909 goto fail;
910 }
911 screen->base.class_3d = tesla_class;
912
913 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
914 NULL, 0, &screen->tesla);
915 if (ret) {
916 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
917 goto fail;
918 }
919
920 /* This over-allocates by a page. The GP, which would execute at the end of
921 * the last page, would trigger faults. The going theory is that it
922 * prefetches up to a certain amount.
923 */
924 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
925 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
926 NULL, &screen->code);
927 if (ret) {
928 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
929 goto fail;
930 }
931
932 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
933 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
934 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
935
936 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
937
938 screen->TPs = util_bitcount(value & 0xffff);
939 screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
940
941 screen->mp_count = screen->TPs * screen->MPsInTP;
942
943 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
944 STACK_WARPS_ALLOC * 64 * 8;
945
946 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
947 &screen->stack_bo);
948 if (ret) {
949 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
950 goto fail;
951 }
952
953 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
954 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
955 ONE_TEMP_SIZE;
956 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
957 screen->max_tls_space /= 2; /* half of vram */
958
959 /* hw can address max 64 KiB */
960 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
961
962 uint64_t tls_size;
963 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
964 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
965 if (ret)
966 goto fail;
967
968 if (nouveau_mesa_debug)
969 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
970 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
971
972 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
973 &screen->uniforms);
974 if (ret) {
975 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
976 goto fail;
977 }
978
979 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
980 &screen->txc);
981 if (ret) {
982 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
983 goto fail;
984 }
985
986 screen->tic.entries = CALLOC(4096, sizeof(void *));
987 screen->tsc.entries = screen->tic.entries + 2048;
988
989 if (!nv50_blitter_create(screen))
990 goto fail;
991
992 nv50_screen_init_hwctx(screen);
993
994 ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
995 if (ret) {
996 NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
997 goto fail;
998 }
999
1000 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1001
1002 return &screen->base;
1003
1004 fail:
1005 screen->base.base.context_create = NULL;
1006 return &screen->base;
1007 }
1008
1009 int
1010 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1011 {
1012 int i = screen->tic.next;
1013
1014 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1015 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1016
1017 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1018
1019 if (screen->tic.entries[i])
1020 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1021
1022 screen->tic.entries[i] = entry;
1023 return i;
1024 }
1025
1026 int
1027 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1028 {
1029 int i = screen->tsc.next;
1030
1031 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1032 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1033
1034 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1035
1036 if (screen->tsc.entries[i])
1037 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1038
1039 screen->tsc.entries[i] = entry;
1040 return i;
1041 }