2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
33 #include "nouveau_vp3_video.h"
35 #include "nv_object.xml.h"
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
42 #define THREADS_IN_WARP 32
45 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
46 enum pipe_format format
,
47 enum pipe_texture_target target
,
48 unsigned sample_count
,
53 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
55 if (sample_count
== 8 && util_format_get_blocksizebits(format
) >= 128)
58 if (!util_format_is_supported(format
, bindings
))
62 case PIPE_FORMAT_Z16_UNORM
:
63 if (nv50_screen(pscreen
)->tesla
->oclass
< NVA0_3D_CLASS
)
70 if (bindings
& PIPE_BIND_LINEAR
)
71 if (util_format_is_depth_or_stencil(format
) ||
72 (target
!= PIPE_TEXTURE_1D
&&
73 target
!= PIPE_TEXTURE_2D
&&
74 target
!= PIPE_TEXTURE_RECT
) ||
78 /* shared is always supported */
79 bindings
&= ~(PIPE_BIND_LINEAR
|
82 return (( nv50_format_table
[format
].usage
|
83 nv50_vertex_format
[format
].usage
) & bindings
) == bindings
;
87 nv50_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
89 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
90 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
93 /* non-boolean caps */
94 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
96 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
98 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
100 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
102 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
103 case PIPE_CAP_MIN_TEXEL_OFFSET
:
105 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
106 case PIPE_CAP_MAX_TEXEL_OFFSET
:
108 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
109 return 128 * 1024 * 1024;
110 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
112 case PIPE_CAP_MAX_RENDER_TARGETS
:
114 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
116 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
118 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
119 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
121 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
122 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
124 case PIPE_CAP_MAX_VERTEX_STREAMS
:
126 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
128 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
130 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
131 return 16; /* 256 for binding as RT, but that's not possible in GL */
132 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
133 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
134 case PIPE_CAP_MAX_VIEWPORTS
:
135 return NV50_MAX_VIEWPORTS
;
136 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
137 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50
;
138 case PIPE_CAP_ENDIANNESS
:
139 return PIPE_ENDIAN_LITTLE
;
140 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
141 return (class_3d
>= NVA3_3D_CLASS
) ? 4 : 0;
142 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
143 return NV50_MAX_WINDOW_RECTANGLES
;
146 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
147 case PIPE_CAP_TEXTURE_SWIZZLE
:
148 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
149 case PIPE_CAP_NPOT_TEXTURES
:
150 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
151 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
152 case PIPE_CAP_ANISOTROPIC_FILTER
:
153 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
154 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
155 case PIPE_CAP_TWO_SIDED_STENCIL
:
156 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
157 case PIPE_CAP_POINT_SPRITE
:
159 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
160 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
161 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
162 case PIPE_CAP_QUERY_TIMESTAMP
:
163 case PIPE_CAP_QUERY_TIME_ELAPSED
:
164 case PIPE_CAP_OCCLUSION_QUERY
:
165 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
166 case PIPE_CAP_INDEP_BLEND_ENABLE
:
167 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
168 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
169 case PIPE_CAP_PRIMITIVE_RESTART
:
170 case PIPE_CAP_TGSI_INSTANCEID
:
171 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
172 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
173 case PIPE_CAP_CONDITIONAL_RENDER
:
174 case PIPE_CAP_TEXTURE_BARRIER
:
175 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
176 case PIPE_CAP_START_INSTANCE
:
177 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
178 case PIPE_CAP_USER_VERTEX_BUFFERS
:
179 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
180 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
181 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
182 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
183 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
184 case PIPE_CAP_CLIP_HALFZ
:
185 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
186 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
187 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
188 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
189 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
190 case PIPE_CAP_TGSI_TXQS
:
191 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
192 case PIPE_CAP_SHAREABLE_SHADERS
:
193 case PIPE_CAP_CLEAR_TEXTURE
:
194 case PIPE_CAP_COMPUTE
:
195 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
196 case PIPE_CAP_INVALIDATE_BUFFER
:
197 case PIPE_CAP_STRING_MARKER
:
198 case PIPE_CAP_CULL_DISTANCE
:
199 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
200 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
201 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
202 case PIPE_CAP_TGSI_CLOCK
:
203 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
204 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
206 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
207 return 1; /* class_3d >= NVA0_3D_CLASS; */
208 /* supported on nva0+ */
209 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
210 return class_3d
>= NVA0_3D_CLASS
;
211 /* supported on nva3+ */
212 case PIPE_CAP_CUBE_MAP_ARRAY
:
213 case PIPE_CAP_INDEP_BLEND_FUNC
:
214 case PIPE_CAP_TEXTURE_QUERY_LOD
:
215 case PIPE_CAP_SAMPLE_SHADING
:
216 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
217 return class_3d
>= NVA3_3D_CLASS
;
219 /* unsupported caps */
220 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
221 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
222 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
223 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
224 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
225 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
226 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
227 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
228 case PIPE_CAP_TGSI_TEXCOORD
:
229 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
230 case PIPE_CAP_TEXTURE_GATHER_SM5
:
231 case PIPE_CAP_FAKE_SW_MSAA
:
232 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
233 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
234 case PIPE_CAP_DRAW_INDIRECT
:
235 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
236 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
237 case PIPE_CAP_VERTEXID_NOBASE
:
238 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
: /* potentially supported on some hw */
239 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
240 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
241 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
242 case PIPE_CAP_DRAW_PARAMETERS
:
243 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
244 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
245 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
246 case PIPE_CAP_GENERATE_MIPMAP
:
247 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
248 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
249 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
250 case PIPE_CAP_QUERY_MEMORY_INFO
:
251 case PIPE_CAP_PCI_GROUP
:
252 case PIPE_CAP_PCI_BUS
:
253 case PIPE_CAP_PCI_DEVICE
:
254 case PIPE_CAP_PCI_FUNCTION
:
255 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
256 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
257 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
258 case PIPE_CAP_TGSI_VOTE
:
259 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
260 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
261 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
262 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
263 case PIPE_CAP_NATIVE_FENCE_FD
:
264 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
265 case PIPE_CAP_TGSI_FS_FBFETCH
:
266 case PIPE_CAP_DOUBLES
:
268 case PIPE_CAP_INT64_DIVMOD
:
269 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
270 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
271 case PIPE_CAP_TGSI_BALLOT
:
272 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
275 case PIPE_CAP_VENDOR_ID
:
277 case PIPE_CAP_DEVICE_ID
: {
279 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
280 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
285 case PIPE_CAP_ACCELERATED
:
287 case PIPE_CAP_VIDEO_MEMORY
:
288 return dev
->vram_size
>> 20;
293 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
298 nv50_screen_get_shader_param(struct pipe_screen
*pscreen
,
299 enum pipe_shader_type shader
,
300 enum pipe_shader_cap param
)
303 case PIPE_SHADER_VERTEX
:
304 case PIPE_SHADER_GEOMETRY
:
305 case PIPE_SHADER_FRAGMENT
:
307 case PIPE_SHADER_COMPUTE
:
313 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
314 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
315 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
316 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
318 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
320 case PIPE_SHADER_CAP_MAX_INPUTS
:
321 if (shader
== PIPE_SHADER_VERTEX
)
324 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
326 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
328 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
329 return NV50_MAX_PIPE_CONSTBUFS
;
330 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
331 return shader
!= PIPE_SHADER_FRAGMENT
;
332 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
333 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
334 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
336 case PIPE_SHADER_CAP_MAX_TEMPS
:
337 return nv50_screen(pscreen
)->max_tls_space
/ ONE_TEMP_SIZE
;
338 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
340 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
342 case PIPE_SHADER_CAP_SUBROUTINES
:
343 return 0; /* please inline, or provide function declarations */
344 case PIPE_SHADER_CAP_INTEGERS
:
346 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
348 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
349 /* The chip could handle more sampler views than samplers */
350 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
351 return MIN2(16, PIPE_MAX_SAMPLERS
);
352 case PIPE_SHADER_CAP_PREFERRED_IR
:
353 return PIPE_SHADER_IR_TGSI
;
354 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
356 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
357 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
358 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
359 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
360 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
361 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
362 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
363 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
366 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
372 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
375 case PIPE_CAPF_MAX_LINE_WIDTH
:
376 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
378 case PIPE_CAPF_MAX_POINT_WIDTH
:
379 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
381 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
383 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
385 case PIPE_CAPF_GUARD_BAND_LEFT
:
386 case PIPE_CAPF_GUARD_BAND_TOP
:
388 case PIPE_CAPF_GUARD_BAND_RIGHT
:
389 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
390 return 0.0f
; /* that or infinity */
393 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param
);
398 nv50_screen_get_compute_param(struct pipe_screen
*pscreen
,
399 enum pipe_shader_ir ir_type
,
400 enum pipe_compute_cap param
, void *data
)
402 struct nv50_screen
*screen
= nv50_screen(pscreen
);
404 #define RET(x) do { \
406 memcpy(data, x, sizeof(x)); \
411 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
412 RET((uint64_t []) { 2 });
413 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
414 RET(((uint64_t []) { 65535, 65535 }));
415 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
416 RET(((uint64_t []) { 512, 512, 64 }));
417 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
418 RET((uint64_t []) { 512 });
419 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
: /* g0-15[] */
420 RET((uint64_t []) { 1ULL << 32 });
421 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
: /* s[] */
422 RET((uint64_t []) { 16 << 10 });
423 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
: /* l[] */
424 RET((uint64_t []) { 16 << 10 });
425 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
: /* c[], arbitrary limit */
426 RET((uint64_t []) { 4096 });
427 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
428 RET((uint32_t []) { 32 });
429 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
430 RET((uint64_t []) { 1ULL << 40 });
431 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
432 RET((uint32_t []) { 0 });
433 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
434 RET((uint32_t []) { screen
->mp_count
});
435 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
436 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
437 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
438 RET((uint32_t []) { 32 });
439 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
440 RET((uint64_t []) { 0 });
449 nv50_screen_destroy(struct pipe_screen
*pscreen
)
451 struct nv50_screen
*screen
= nv50_screen(pscreen
);
453 if (!nouveau_drm_screen_unref(&screen
->base
))
456 if (screen
->base
.fence
.current
) {
457 struct nouveau_fence
*current
= NULL
;
459 /* nouveau_fence_wait will create a new current fence, so wait on the
460 * _current_ one, and remove both.
462 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
463 nouveau_fence_wait(current
, NULL
);
464 nouveau_fence_ref(NULL
, ¤t
);
465 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
467 if (screen
->base
.pushbuf
)
468 screen
->base
.pushbuf
->user_priv
= NULL
;
471 nv50_blitter_destroy(screen
);
472 if (screen
->pm
.prog
) {
473 screen
->pm
.prog
->code
= NULL
; /* hardcoded, don't FREE */
474 nv50_program_destroy(NULL
, screen
->pm
.prog
);
475 FREE(screen
->pm
.prog
);
478 nouveau_bo_ref(NULL
, &screen
->code
);
479 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
480 nouveau_bo_ref(NULL
, &screen
->stack_bo
);
481 nouveau_bo_ref(NULL
, &screen
->txc
);
482 nouveau_bo_ref(NULL
, &screen
->uniforms
);
483 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
485 nouveau_heap_destroy(&screen
->vp_code_heap
);
486 nouveau_heap_destroy(&screen
->gp_code_heap
);
487 nouveau_heap_destroy(&screen
->fp_code_heap
);
489 FREE(screen
->tic
.entries
);
491 nouveau_object_del(&screen
->tesla
);
492 nouveau_object_del(&screen
->eng2d
);
493 nouveau_object_del(&screen
->m2mf
);
494 nouveau_object_del(&screen
->compute
);
495 nouveau_object_del(&screen
->sync
);
497 nouveau_screen_fini(&screen
->base
);
503 nv50_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
505 struct nv50_screen
*screen
= nv50_screen(pscreen
);
506 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
508 /* we need to do it after possible flush in MARK_RING */
509 *sequence
= ++screen
->base
.fence
.sequence
;
511 assert(PUSH_AVAIL(push
) + push
->rsvd_kick
>= 5);
512 PUSH_DATA (push
, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH
), 4));
513 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
514 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
515 PUSH_DATA (push
, *sequence
);
516 PUSH_DATA (push
, NV50_3D_QUERY_GET_MODE_WRITE_UNK0
|
517 NV50_3D_QUERY_GET_UNK4
|
518 NV50_3D_QUERY_GET_UNIT_CROP
|
519 NV50_3D_QUERY_GET_TYPE_QUERY
|
520 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO
|
521 NV50_3D_QUERY_GET_SHORT
);
525 nv50_screen_fence_update(struct pipe_screen
*pscreen
)
527 return nv50_screen(pscreen
)->fence
.map
[0];
531 nv50_screen_init_hwctx(struct nv50_screen
*screen
)
533 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
534 struct nv04_fifo
*fifo
;
537 fifo
= (struct nv04_fifo
*)screen
->base
.channel
->data
;
539 BEGIN_NV04(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
540 PUSH_DATA (push
, screen
->m2mf
->handle
);
541 BEGIN_NV04(push
, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY
), 3);
542 PUSH_DATA (push
, screen
->sync
->handle
);
543 PUSH_DATA (push
, fifo
->vram
);
544 PUSH_DATA (push
, fifo
->vram
);
546 BEGIN_NV04(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
547 PUSH_DATA (push
, screen
->eng2d
->handle
);
548 BEGIN_NV04(push
, NV50_2D(DMA_NOTIFY
), 4);
549 PUSH_DATA (push
, screen
->sync
->handle
);
550 PUSH_DATA (push
, fifo
->vram
);
551 PUSH_DATA (push
, fifo
->vram
);
552 PUSH_DATA (push
, fifo
->vram
);
553 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
554 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
555 BEGIN_NV04(push
, NV50_2D(CLIP_ENABLE
), 1);
557 BEGIN_NV04(push
, NV50_2D(COLOR_KEY_ENABLE
), 1);
559 BEGIN_NV04(push
, SUBC_2D(0x0888), 1);
561 BEGIN_NV04(push
, NV50_2D(COND_MODE
), 1);
562 PUSH_DATA (push
, NV50_2D_COND_MODE_ALWAYS
);
564 BEGIN_NV04(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
565 PUSH_DATA (push
, screen
->tesla
->handle
);
567 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
568 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
570 BEGIN_NV04(push
, NV50_3D(DMA_NOTIFY
), 1);
571 PUSH_DATA (push
, screen
->sync
->handle
);
572 BEGIN_NV04(push
, NV50_3D(DMA_ZETA
), 11);
573 for (i
= 0; i
< 11; ++i
)
574 PUSH_DATA(push
, fifo
->vram
);
575 BEGIN_NV04(push
, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN
);
576 for (i
= 0; i
< NV50_3D_DMA_COLOR__LEN
; ++i
)
577 PUSH_DATA(push
, fifo
->vram
);
579 BEGIN_NV04(push
, NV50_3D(REG_MODE
), 1);
580 PUSH_DATA (push
, NV50_3D_REG_MODE_STRIPED
);
581 BEGIN_NV04(push
, NV50_3D(UNK1400_LANES
), 1);
582 PUSH_DATA (push
, 0xf);
584 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
585 BEGIN_NV04(push
, NV50_3D(WATCHDOG_TIMER
), 1);
586 PUSH_DATA (push
, 0x18);
589 BEGIN_NV04(push
, NV50_3D(ZETA_COMP_ENABLE
), 1);
590 PUSH_DATA(push
, screen
->base
.drm
->version
>= 0x01000101);
592 BEGIN_NV04(push
, NV50_3D(RT_COMP_ENABLE(0)), 8);
593 for (i
= 0; i
< 8; ++i
)
594 PUSH_DATA(push
, screen
->base
.drm
->version
>= 0x01000101);
596 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
599 BEGIN_NV04(push
, NV50_3D(CSAA_ENABLE
), 1);
601 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_ENABLE
), 1);
603 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
604 PUSH_DATA (push
, NV50_3D_MULTISAMPLE_MODE_MS1
);
605 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_CTRL
), 1);
607 BEGIN_NV04(push
, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS
), 1);
609 BEGIN_NV04(push
, NV50_3D(BLEND_SEPARATE_ALPHA
), 1);
612 if (screen
->tesla
->oclass
>= NVA0_3D_CLASS
) {
613 BEGIN_NV04(push
, SUBC_3D(NVA0_3D_TEX_MISC
), 1);
617 BEGIN_NV04(push
, NV50_3D(SCREEN_Y_CONTROL
), 1);
619 BEGIN_NV04(push
, NV50_3D(WINDOW_OFFSET_X
), 2);
622 BEGIN_NV04(push
, NV50_3D(ZCULL_REGION
), 1);
623 PUSH_DATA (push
, 0x3f);
625 BEGIN_NV04(push
, NV50_3D(VP_ADDRESS_HIGH
), 2);
626 PUSH_DATAh(push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
627 PUSH_DATA (push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
629 BEGIN_NV04(push
, NV50_3D(FP_ADDRESS_HIGH
), 2);
630 PUSH_DATAh(push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
631 PUSH_DATA (push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
633 BEGIN_NV04(push
, NV50_3D(GP_ADDRESS_HIGH
), 2);
634 PUSH_DATAh(push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
635 PUSH_DATA (push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
637 BEGIN_NV04(push
, NV50_3D(LOCAL_ADDRESS_HIGH
), 3);
638 PUSH_DATAh(push
, screen
->tls_bo
->offset
);
639 PUSH_DATA (push
, screen
->tls_bo
->offset
);
640 PUSH_DATA (push
, util_logbase2(screen
->cur_tls_space
/ 8));
642 BEGIN_NV04(push
, NV50_3D(STACK_ADDRESS_HIGH
), 3);
643 PUSH_DATAh(push
, screen
->stack_bo
->offset
);
644 PUSH_DATA (push
, screen
->stack_bo
->offset
);
647 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
648 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (0 << 16));
649 PUSH_DATA (push
, screen
->uniforms
->offset
+ (0 << 16));
650 PUSH_DATA (push
, (NV50_CB_PVP
<< 16) | 0x0000);
652 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
653 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (1 << 16));
654 PUSH_DATA (push
, screen
->uniforms
->offset
+ (1 << 16));
655 PUSH_DATA (push
, (NV50_CB_PGP
<< 16) | 0x0000);
657 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
658 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (2 << 16));
659 PUSH_DATA (push
, screen
->uniforms
->offset
+ (2 << 16));
660 PUSH_DATA (push
, (NV50_CB_PFP
<< 16) | 0x0000);
662 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
663 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (3 << 16));
664 PUSH_DATA (push
, screen
->uniforms
->offset
+ (3 << 16));
665 PUSH_DATA (push
, (NV50_CB_AUX
<< 16) | (NV50_CB_AUX_SIZE
& 0xffff));
667 BEGIN_NI04(push
, NV50_3D(SET_PROGRAM_CB
), 3);
668 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf01);
669 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf21);
670 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf31);
672 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
673 BEGIN_NV04(push
, NV50_3D(CB_ADDR
), 1);
674 PUSH_DATA (push
, (NV50_CB_AUX_RUNOUT_OFFSET
<< (8 - 2)) | NV50_CB_AUX
);
675 BEGIN_NI04(push
, NV50_3D(CB_DATA(0)), 4);
676 PUSH_DATAf(push
, 0.0f
);
677 PUSH_DATAf(push
, 0.0f
);
678 PUSH_DATAf(push
, 0.0f
);
679 PUSH_DATAf(push
, 0.0f
);
680 BEGIN_NV04(push
, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
681 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET
);
682 PUSH_DATA (push
, screen
->uniforms
->offset
+ (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET
);
684 nv50_upload_ms_info(push
);
686 /* max TIC (bits 4:8) & TSC bindings, per program type */
687 for (i
= 0; i
< 3; ++i
) {
688 BEGIN_NV04(push
, NV50_3D(TEX_LIMITS(i
)), 1);
689 PUSH_DATA (push
, 0x54);
692 BEGIN_NV04(push
, NV50_3D(TIC_ADDRESS_HIGH
), 3);
693 PUSH_DATAh(push
, screen
->txc
->offset
);
694 PUSH_DATA (push
, screen
->txc
->offset
);
695 PUSH_DATA (push
, NV50_TIC_MAX_ENTRIES
- 1);
697 BEGIN_NV04(push
, NV50_3D(TSC_ADDRESS_HIGH
), 3);
698 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
699 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
700 PUSH_DATA (push
, NV50_TSC_MAX_ENTRIES
- 1);
702 BEGIN_NV04(push
, NV50_3D(LINKED_TSC
), 1);
705 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_EN
), 1);
707 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_MODE
), 1);
708 PUSH_DATA (push
, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
709 BEGIN_NV04(push
, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
710 for (i
= 0; i
< 8 * 2; ++i
)
712 BEGIN_NV04(push
, NV50_3D(CLIPID_ENABLE
), 1);
715 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
717 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
718 BEGIN_NV04(push
, NV50_3D(DEPTH_RANGE_NEAR(i
)), 2);
719 PUSH_DATAf(push
, 0.0f
);
720 PUSH_DATAf(push
, 1.0f
);
721 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(i
)), 2);
722 PUSH_DATA (push
, 8192 << 16);
723 PUSH_DATA (push
, 8192 << 16);
726 BEGIN_NV04(push
, NV50_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
727 #ifdef NV50_SCISSORS_CLIPPING
728 PUSH_DATA (push
, 0x0000);
730 PUSH_DATA (push
, 0x1080);
733 BEGIN_NV04(push
, NV50_3D(CLEAR_FLAGS
), 1);
734 PUSH_DATA (push
, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT
);
736 /* We use scissors instead of exact view volume clipping,
737 * so they're always enabled.
739 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
740 BEGIN_NV04(push
, NV50_3D(SCISSOR_ENABLE(i
)), 3);
742 PUSH_DATA (push
, 8192 << 16);
743 PUSH_DATA (push
, 8192 << 16);
746 BEGIN_NV04(push
, NV50_3D(RASTERIZE_ENABLE
), 1);
748 BEGIN_NV04(push
, NV50_3D(POINT_RASTER_RULES
), 1);
749 PUSH_DATA (push
, NV50_3D_POINT_RASTER_RULES_OGL
);
750 BEGIN_NV04(push
, NV50_3D(FRAG_COLOR_CLAMP_EN
), 1);
751 PUSH_DATA (push
, 0x11111111);
752 BEGIN_NV04(push
, NV50_3D(EDGEFLAG
), 1);
755 BEGIN_NV04(push
, NV50_3D(VB_ELEMENT_BASE
), 1);
757 if (screen
->base
.class_3d
>= NV84_3D_CLASS
) {
758 BEGIN_NV04(push
, NV84_3D(VERTEX_ID_BASE
), 1);
765 static int nv50_tls_alloc(struct nv50_screen
*screen
, unsigned tls_space
,
768 struct nouveau_device
*dev
= screen
->base
.device
;
771 screen
->cur_tls_space
= util_next_power_of_two(tls_space
/ ONE_TEMP_SIZE
) *
773 if (nouveau_mesa_debug
)
774 debug_printf("allocating space for %u temps\n",
775 util_next_power_of_two(tls_space
/ ONE_TEMP_SIZE
));
776 *tls_size
= screen
->cur_tls_space
* util_next_power_of_two(screen
->TPs
) *
777 screen
->MPsInTP
* LOCAL_WARPS_ALLOC
* THREADS_IN_WARP
;
779 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
780 *tls_size
, NULL
, &screen
->tls_bo
);
782 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret
);
789 int nv50_tls_realloc(struct nv50_screen
*screen
, unsigned tls_space
)
791 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
795 if (tls_space
< screen
->cur_tls_space
)
797 if (tls_space
> screen
->max_tls_space
) {
798 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
799 * LOCAL_WARPS_NO_CLAMP) */
800 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
801 (unsigned)(tls_space
/ ONE_TEMP_SIZE
),
802 (unsigned)(screen
->max_tls_space
/ ONE_TEMP_SIZE
));
806 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
807 ret
= nv50_tls_alloc(screen
, tls_space
, &tls_size
);
811 BEGIN_NV04(push
, NV50_3D(LOCAL_ADDRESS_HIGH
), 3);
812 PUSH_DATAh(push
, screen
->tls_bo
->offset
);
813 PUSH_DATA (push
, screen
->tls_bo
->offset
);
814 PUSH_DATA (push
, util_logbase2(screen
->cur_tls_space
/ 8));
819 struct nouveau_screen
*
820 nv50_screen_create(struct nouveau_device
*dev
)
822 struct nv50_screen
*screen
;
823 struct pipe_screen
*pscreen
;
824 struct nouveau_object
*chan
;
826 uint32_t tesla_class
;
830 screen
= CALLOC_STRUCT(nv50_screen
);
833 pscreen
= &screen
->base
.base
;
834 pscreen
->destroy
= nv50_screen_destroy
;
836 ret
= nouveau_screen_init(&screen
->base
, dev
);
838 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret
);
842 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
843 * admit them to VRAM.
845 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
846 PIPE_BIND_VERTEX_BUFFER
;
847 screen
->base
.sysmem_bindings
|=
848 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
850 screen
->base
.pushbuf
->user_priv
= screen
;
851 screen
->base
.pushbuf
->rsvd_kick
= 5;
853 chan
= screen
->base
.channel
;
855 pscreen
->context_create
= nv50_create
;
856 pscreen
->is_format_supported
= nv50_screen_is_format_supported
;
857 pscreen
->get_param
= nv50_screen_get_param
;
858 pscreen
->get_shader_param
= nv50_screen_get_shader_param
;
859 pscreen
->get_paramf
= nv50_screen_get_paramf
;
860 pscreen
->get_compute_param
= nv50_screen_get_compute_param
;
861 pscreen
->get_driver_query_info
= nv50_screen_get_driver_query_info
;
862 pscreen
->get_driver_query_group_info
= nv50_screen_get_driver_query_group_info
;
864 nv50_screen_init_resource_functions(pscreen
);
866 if (screen
->base
.device
->chipset
< 0x84 ||
867 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
869 nouveau_screen_init_vdec(&screen
->base
);
870 } else if (screen
->base
.device
->chipset
< 0x98 ||
871 screen
->base
.device
->chipset
== 0xa0) {
873 screen
->base
.base
.get_video_param
= nv84_screen_get_video_param
;
874 screen
->base
.base
.is_video_format_supported
= nv84_screen_video_supported
;
877 screen
->base
.base
.get_video_param
= nouveau_vp3_screen_get_video_param
;
878 screen
->base
.base
.is_video_format_supported
= nouveau_vp3_screen_video_supported
;
881 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096,
882 NULL
, &screen
->fence
.bo
);
884 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret
);
888 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
889 screen
->fence
.map
= screen
->fence
.bo
->map
;
890 screen
->base
.fence
.emit
= nv50_screen_fence_emit
;
891 screen
->base
.fence
.update
= nv50_screen_fence_update
;
893 ret
= nouveau_object_new(chan
, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS
,
894 &(struct nv04_notify
){ .length
= 32 },
895 sizeof(struct nv04_notify
), &screen
->sync
);
897 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret
);
901 ret
= nouveau_object_new(chan
, 0xbeef5039, NV50_M2MF_CLASS
,
902 NULL
, 0, &screen
->m2mf
);
904 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret
);
908 ret
= nouveau_object_new(chan
, 0xbeef502d, NV50_2D_CLASS
,
909 NULL
, 0, &screen
->eng2d
);
911 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret
);
915 switch (dev
->chipset
& 0xf0) {
917 tesla_class
= NV50_3D_CLASS
;
921 tesla_class
= NV84_3D_CLASS
;
924 switch (dev
->chipset
) {
928 tesla_class
= NVA0_3D_CLASS
;
931 tesla_class
= NVAF_3D_CLASS
;
934 tesla_class
= NVA3_3D_CLASS
;
939 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev
->chipset
);
942 screen
->base
.class_3d
= tesla_class
;
944 ret
= nouveau_object_new(chan
, 0xbeef5097, tesla_class
,
945 NULL
, 0, &screen
->tesla
);
947 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret
);
951 /* This over-allocates by a page. The GP, which would execute at the end of
952 * the last page, would trigger faults. The going theory is that it
953 * prefetches up to a certain amount.
955 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
956 (3 << NV50_CODE_BO_SIZE_LOG2
) + 0x1000,
957 NULL
, &screen
->code
);
959 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret
);
963 nouveau_heap_init(&screen
->vp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
964 nouveau_heap_init(&screen
->gp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
965 nouveau_heap_init(&screen
->fp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
967 nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
969 screen
->TPs
= util_bitcount(value
& 0xffff);
970 screen
->MPsInTP
= util_bitcount((value
>> 24) & 0xf);
972 screen
->mp_count
= screen
->TPs
* screen
->MPsInTP
;
974 stack_size
= util_next_power_of_two(screen
->TPs
) * screen
->MPsInTP
*
975 STACK_WARPS_ALLOC
* 64 * 8;
977 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, stack_size
, NULL
,
980 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret
);
984 uint64_t size_of_one_temp
= util_next_power_of_two(screen
->TPs
) *
985 screen
->MPsInTP
* LOCAL_WARPS_ALLOC
* THREADS_IN_WARP
*
987 screen
->max_tls_space
= dev
->vram_size
/ size_of_one_temp
* ONE_TEMP_SIZE
;
988 screen
->max_tls_space
/= 2; /* half of vram */
990 /* hw can address max 64 KiB */
991 screen
->max_tls_space
= MIN2(screen
->max_tls_space
, 64 << 10);
994 unsigned tls_space
= 4/*temps*/ * ONE_TEMP_SIZE
;
995 ret
= nv50_tls_alloc(screen
, tls_space
, &tls_size
);
999 if (nouveau_mesa_debug
)
1000 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64
" MiB, tls_size = %"PRIu64
" KiB\n",
1001 screen
->TPs
, screen
->MPsInTP
, dev
->vram_size
>> 20, tls_size
>> 10);
1003 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 4 << 16, NULL
,
1006 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret
);
1010 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 3 << 16, NULL
,
1013 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret
);
1017 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
1018 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
1020 if (!nv50_blitter_create(screen
))
1023 nv50_screen_init_hwctx(screen
);
1025 ret
= nv50_screen_compute_setup(screen
, screen
->base
.pushbuf
);
1027 NOUVEAU_ERR("Failed to init compute context: %d\n", ret
);
1031 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
);
1033 return &screen
->base
;
1036 screen
->base
.base
.context_create
= NULL
;
1037 return &screen
->base
;
1041 nv50_screen_tic_alloc(struct nv50_screen
*screen
, void *entry
)
1043 int i
= screen
->tic
.next
;
1045 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
1046 i
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
1048 screen
->tic
.next
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
1050 if (screen
->tic
.entries
[i
])
1051 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
1053 screen
->tic
.entries
[i
] = entry
;
1058 nv50_screen_tsc_alloc(struct nv50_screen
*screen
, void *entry
)
1060 int i
= screen
->tsc
.next
;
1062 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
1063 i
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
1065 screen
->tsc
.next
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
1067 if (screen
->tsc
.entries
[i
])
1068 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
1070 screen
->tsc
.entries
[i
] = entry
;