src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30
  31 #include "nv50/nv50_context.h"
  32 #include "nv50/nv50_screen.h"
  33
  34 #include "nouveau_vp3_video.h"
  35
  36 #include "nv_object.xml.h"
  37
  38 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  39 #define LOCAL_WARPS_ALLOC 32
  40 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  41 #define STACK_WARPS_ALLOC 32
  42
  43 #define THREADS_IN_WARP 32
  44
  45 static boolean
  46 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  47                                 enum pipe_format format,
  48                                 enum pipe_texture_target target,
  49                                 unsigned sample_count,
  50                                 unsigned storage_sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (sample_count > 8)
  54       return false;
  55    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  56       return false;
  57    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  58       return false;
  59
  60    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  61       return false;
  62
  63    switch (format) {
  64    case PIPE_FORMAT_Z16_UNORM:
  65       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  66          return false;
  67       break;
  68    default:
  69       break;
  70    }
  71
  72    if (bindings & PIPE_BIND_LINEAR)
  73       if (util_format_is_depth_or_stencil(format) ||
  74           (target != PIPE_TEXTURE_1D &&
  75            target != PIPE_TEXTURE_2D &&
  76            target != PIPE_TEXTURE_RECT) ||
  77           sample_count > 1)
  78          return false;
  79
  80    /* shared is always supported */
  81    bindings &= ~(PIPE_BIND_LINEAR |
  82                  PIPE_BIND_SHARED);
  83
  84    return (( nv50_format_table[format].usage |
  85             nv50_vertex_format[format].usage) & bindings) == bindings;
  86 }
  87
  88 static int
  89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  90 {
  91    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  92    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  93
  94    switch (param) {
  95    /* non-boolean caps */
  96    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  97       return 14;
  98    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  99       return 12;
 100    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 101       return 14;
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103       return 512;
 104    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 105    case PIPE_CAP_MIN_TEXEL_OFFSET:
 106       return -8;
 107    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109       return 7;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 128 * 1024 * 1024;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 113       return 330;
 114    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 115       return 330;
 116    case PIPE_CAP_MAX_RENDER_TARGETS:
 117       return 8;
 118    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 119       return 1;
 120    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 121    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 122       return 8;
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124       return 4;
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 127       return 64;
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130       return 1024;
 131    case PIPE_CAP_MAX_VERTEX_STREAMS:
 132       return 1;
 133    case PIPE_CAP_MAX_GS_INVOCATIONS:
 134       return 0;
 135    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 136       return 0;
 137    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 138       return 2048;
 139    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 140       return 2047;
 141    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 142       return 256;
 143    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 144       return 16; /* 256 for binding as RT, but that's not possible in GL */
 145    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 146       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 147    case PIPE_CAP_MAX_VIEWPORTS:
 148       return NV50_MAX_VIEWPORTS;
 149    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 150       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 151    case PIPE_CAP_ENDIANNESS:
 152       return PIPE_ENDIAN_LITTLE;
 153    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 154       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 155    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 156       return NV50_MAX_WINDOW_RECTANGLES;
 157    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 158       return 16 * 1024 * 1024;
 159    case PIPE_CAP_MAX_VARYINGS:
 160       return 15;
 161
 162    /* supported caps */
 163    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 164    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 165    case PIPE_CAP_TEXTURE_SWIZZLE:
 166    case PIPE_CAP_NPOT_TEXTURES:
 167    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 168    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 169    case PIPE_CAP_ANISOTROPIC_FILTER:
 170    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 171    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 172    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 173    case PIPE_CAP_POINT_SPRITE:
 174    case PIPE_CAP_SM3:
 175    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 176    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 177    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 178    case PIPE_CAP_QUERY_TIMESTAMP:
 179    case PIPE_CAP_QUERY_TIME_ELAPSED:
 180    case PIPE_CAP_OCCLUSION_QUERY:
 181    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 182    case PIPE_CAP_INDEP_BLEND_ENABLE:
 183    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 184    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 185    case PIPE_CAP_PRIMITIVE_RESTART:
 186    case PIPE_CAP_TGSI_INSTANCEID:
 187    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 188    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 189    case PIPE_CAP_CONDITIONAL_RENDER:
 190    case PIPE_CAP_TEXTURE_BARRIER:
 191    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 192    case PIPE_CAP_START_INSTANCE:
 193    case PIPE_CAP_USER_VERTEX_BUFFERS:
 194    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 195    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 196    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 197    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 198    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 199    case PIPE_CAP_CLIP_HALFZ:
 200    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 201    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 202    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 203    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 204    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 205    case PIPE_CAP_TGSI_TXQS:
 206    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 207    case PIPE_CAP_SHAREABLE_SHADERS:
 208    case PIPE_CAP_CLEAR_TEXTURE:
 209    case PIPE_CAP_COMPUTE:
 210    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 211    case PIPE_CAP_INVALIDATE_BUFFER:
 212    case PIPE_CAP_STRING_MARKER:
 213    case PIPE_CAP_CULL_DISTANCE:
 214    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 215    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 216    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 217    case PIPE_CAP_TGSI_CLOCK:
 218    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 219    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 220    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 221       return 1;
 222    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 223       return 1; /* class_3d >= NVA0_3D_CLASS; */
 224    /* supported on nva0+ */
 225    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 226       return class_3d >= NVA0_3D_CLASS;
 227    /* supported on nva3+ */
 228    case PIPE_CAP_CUBE_MAP_ARRAY:
 229    case PIPE_CAP_INDEP_BLEND_FUNC:
 230    case PIPE_CAP_TEXTURE_QUERY_LOD:
 231    case PIPE_CAP_SAMPLE_SHADING:
 232    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 233       return class_3d >= NVA3_3D_CLASS;
 234
 235    /* unsupported caps */
 236    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 237    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 238    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 239    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 240    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 241    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 242    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 243    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 244    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 245    case PIPE_CAP_TGSI_TEXCOORD:
 246    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 247    case PIPE_CAP_TEXTURE_GATHER_SM5:
 248    case PIPE_CAP_FAKE_SW_MSAA:
 249    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 250    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 251    case PIPE_CAP_DRAW_INDIRECT:
 252    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 253    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 254    case PIPE_CAP_VERTEXID_NOBASE:
 255    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 256    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 257    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 258    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 259    case PIPE_CAP_DRAW_PARAMETERS:
 260    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 261    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 262    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 263    case PIPE_CAP_GENERATE_MIPMAP:
 264    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 265    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 266    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 267    case PIPE_CAP_QUERY_MEMORY_INFO:
 268    case PIPE_CAP_PCI_GROUP:
 269    case PIPE_CAP_PCI_BUS:
 270    case PIPE_CAP_PCI_DEVICE:
 271    case PIPE_CAP_PCI_FUNCTION:
 272    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 273    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 274    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 275    case PIPE_CAP_TGSI_VOTE:
 276    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 277    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 278    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 279    case PIPE_CAP_NATIVE_FENCE_FD:
 280    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 281    case PIPE_CAP_TGSI_FS_FBFETCH:
 282    case PIPE_CAP_DOUBLES:
 283    case PIPE_CAP_INT64:
 284    case PIPE_CAP_INT64_DIVMOD:
 285    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 286    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 287    case PIPE_CAP_TGSI_BALLOT:
 288    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 289    case PIPE_CAP_POST_DEPTH_COVERAGE:
 290    case PIPE_CAP_BINDLESS_TEXTURE:
 291    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 292    case PIPE_CAP_QUERY_SO_OVERFLOW:
 293    case PIPE_CAP_MEMOBJ:
 294    case PIPE_CAP_LOAD_CONSTBUF:
 295    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 296    case PIPE_CAP_TILE_RASTER_ORDER:
 297    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 298    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 299    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 300    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 301    case PIPE_CAP_FENCE_SIGNAL:
 302    case PIPE_CAP_CONSTBUF0_FLAGS:
 303    case PIPE_CAP_PACKED_UNIFORMS:
 304    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 305    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 306    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 307    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 308    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 309    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 310    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 311    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 312    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 313    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 314    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 315    case PIPE_CAP_TGSI_ATOMFADD:
 316    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 317    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 318    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 319    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 320       return 0;
 321
 322    case PIPE_CAP_VENDOR_ID:
 323       return 0x10de;
 324    case PIPE_CAP_DEVICE_ID: {
 325       uint64_t device_id;
 326       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 327          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 328          return -1;
 329       }
 330       return device_id;
 331    }
 332    case PIPE_CAP_ACCELERATED:
 333       return 1;
 334    case PIPE_CAP_VIDEO_MEMORY:
 335       return dev->vram_size >> 20;
 336    case PIPE_CAP_UMA:
 337       return 0;
 338    default:
 339       debug_printf("%s: unhandled cap %d\n", __func__, param);
 340       return u_pipe_screen_get_param_defaults(pscreen, param);
 341    }
 342 }
 343
 344 static int
 345 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 346                              enum pipe_shader_type shader,
 347                              enum pipe_shader_cap param)
 348 {
 349    switch (shader) {
 350    case PIPE_SHADER_VERTEX:
 351    case PIPE_SHADER_GEOMETRY:
 352    case PIPE_SHADER_FRAGMENT:
 353       break;
 354    case PIPE_SHADER_COMPUTE:
 355    default:
 356       return 0;
 357    }
 358
 359    switch (param) {
 360    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 361    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 362    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 363    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 364       return 16384;
 365    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 366       return 4;
 367    case PIPE_SHADER_CAP_MAX_INPUTS:
 368       if (shader == PIPE_SHADER_VERTEX)
 369          return 32;
 370       return 15;
 371    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 372       return 16;
 373    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 374       return 65536;
 375    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 376       return NV50_MAX_PIPE_CONSTBUFS;
 377    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 378       return shader != PIPE_SHADER_FRAGMENT;
 379    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 380    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 381    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 382       return 1;
 383    case PIPE_SHADER_CAP_MAX_TEMPS:
 384       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 385    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 386       return 1;
 387    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 388       return 1;
 389    case PIPE_SHADER_CAP_INT64_ATOMICS:
 390    case PIPE_SHADER_CAP_FP16:
 391    case PIPE_SHADER_CAP_SUBROUTINES:
 392       return 0; /* please inline, or provide function declarations */
 393    case PIPE_SHADER_CAP_INTEGERS:
 394       return 1;
 395    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 396       return 1;
 397    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 398       /* The chip could handle more sampler views than samplers */
 399    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 400       return MIN2(16, PIPE_MAX_SAMPLERS);
 401    case PIPE_SHADER_CAP_PREFERRED_IR:
 402       return PIPE_SHADER_IR_TGSI;
 403    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 404       return 32;
 405    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 406    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 407    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 408    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 409    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 410    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 411    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 412    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 413    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 414    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 415    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 416       return 0;
 417    case PIPE_SHADER_CAP_SCALAR_ISA:
 418       return 1;
 419    default:
 420       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 421       return 0;
 422    }
 423 }
 424
 425 static float
 426 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 427 {
 428    switch (param) {
 429    case PIPE_CAPF_MAX_LINE_WIDTH:
 430    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 431       return 10.0f;
 432    case PIPE_CAPF_MAX_POINT_WIDTH:
 433    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 434       return 64.0f;
 435    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 436       return 16.0f;
 437    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 438       return 4.0f;
 439    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 440    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 441    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 442       return 0.0f;
 443    }
 444
 445    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 446    return 0.0f;
 447 }
 448
 449 static int
 450 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 451                               enum pipe_shader_ir ir_type,
 452                               enum pipe_compute_cap param, void *data)
 453 {
 454    struct nv50_screen *screen = nv50_screen(pscreen);
 455
 456 #define RET(x) do {                  \
 457    if (data)                         \
 458       memcpy(data, x, sizeof(x));    \
 459    return sizeof(x);                 \
 460 } while (0)
 461
 462    switch (param) {
 463    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 464       RET((uint64_t []) { 2 });
 465    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 466       RET(((uint64_t []) { 65535, 65535 }));
 467    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 468       RET(((uint64_t []) { 512, 512, 64 }));
 469    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 470       RET((uint64_t []) { 512 });
 471    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 472       RET((uint64_t []) { 1ULL << 32 });
 473    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 474       RET((uint64_t []) { 16 << 10 });
 475    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 476       RET((uint64_t []) { 16 << 10 });
 477    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 478       RET((uint64_t []) { 4096 });
 479    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 480       RET((uint32_t []) { 32 });
 481    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 482       RET((uint64_t []) { 1ULL << 40 });
 483    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 484       RET((uint32_t []) { 0 });
 485    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 486       RET((uint32_t []) { screen->mp_count });
 487    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 488       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 489    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 490       RET((uint32_t []) { 32 });
 491    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 492       RET((uint64_t []) { 0 });
 493    default:
 494       return 0;
 495    }
 496
 497 #undef RET
 498 }
 499
 500 static void
 501 nv50_screen_destroy(struct pipe_screen *pscreen)
 502 {
 503    struct nv50_screen *screen = nv50_screen(pscreen);
 504
 505    if (!nouveau_drm_screen_unref(&screen->base))
 506       return;
 507
 508    if (screen->base.fence.current) {
 509       struct nouveau_fence *current = NULL;
 510
 511       /* nouveau_fence_wait will create a new current fence, so wait on the
 512        * _current_ one, and remove both.
 513        */
 514       nouveau_fence_ref(screen->base.fence.current, &current);
 515       nouveau_fence_wait(current, NULL);
 516       nouveau_fence_ref(NULL, &current);
 517       nouveau_fence_ref(NULL, &screen->base.fence.current);
 518    }
 519    if (screen->base.pushbuf)
 520       screen->base.pushbuf->user_priv = NULL;
 521
 522    if (screen->blitter)
 523       nv50_blitter_destroy(screen);
 524    if (screen->pm.prog) {
 525       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 526       nv50_program_destroy(NULL, screen->pm.prog);
 527       FREE(screen->pm.prog);
 528    }
 529
 530    nouveau_bo_ref(NULL, &screen->code);
 531    nouveau_bo_ref(NULL, &screen->tls_bo);
 532    nouveau_bo_ref(NULL, &screen->stack_bo);
 533    nouveau_bo_ref(NULL, &screen->txc);
 534    nouveau_bo_ref(NULL, &screen->uniforms);
 535    nouveau_bo_ref(NULL, &screen->fence.bo);
 536
 537    nouveau_heap_destroy(&screen->vp_code_heap);
 538    nouveau_heap_destroy(&screen->gp_code_heap);
 539    nouveau_heap_destroy(&screen->fp_code_heap);
 540
 541    FREE(screen->tic.entries);
 542
 543    nouveau_object_del(&screen->tesla);
 544    nouveau_object_del(&screen->eng2d);
 545    nouveau_object_del(&screen->m2mf);
 546    nouveau_object_del(&screen->compute);
 547    nouveau_object_del(&screen->sync);
 548
 549    nouveau_screen_fini(&screen->base);
 550
 551    FREE(screen);
 552 }
 553
 554 static void
 555 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 556 {
 557    struct nv50_screen *screen = nv50_screen(pscreen);
 558    struct nouveau_pushbuf *push = screen->base.pushbuf;
 559
 560    /* we need to do it after possible flush in MARK_RING */
 561    *sequence = ++screen->base.fence.sequence;
 562
 563    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 564    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 565    PUSH_DATAh(push, screen->fence.bo->offset);
 566    PUSH_DATA (push, screen->fence.bo->offset);
 567    PUSH_DATA (push, *sequence);
 568    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 569                     NV50_3D_QUERY_GET_UNK4 |
 570                     NV50_3D_QUERY_GET_UNIT_CROP |
 571                     NV50_3D_QUERY_GET_TYPE_QUERY |
 572                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 573                     NV50_3D_QUERY_GET_SHORT);
 574 }
 575
 576 static u32
 577 nv50_screen_fence_update(struct pipe_screen *pscreen)
 578 {
 579    return nv50_screen(pscreen)->fence.map[0];
 580 }
 581
 582 static void
 583 nv50_screen_init_hwctx(struct nv50_screen *screen)
 584 {
 585    struct nouveau_pushbuf *push = screen->base.pushbuf;
 586    struct nv04_fifo *fifo;
 587    unsigned i;
 588
 589    fifo = (struct nv04_fifo *)screen->base.channel->data;
 590
 591    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 592    PUSH_DATA (push, screen->m2mf->handle);
 593    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 594    PUSH_DATA (push, screen->sync->handle);
 595    PUSH_DATA (push, fifo->vram);
 596    PUSH_DATA (push, fifo->vram);
 597
 598    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 599    PUSH_DATA (push, screen->eng2d->handle);
 600    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 601    PUSH_DATA (push, screen->sync->handle);
 602    PUSH_DATA (push, fifo->vram);
 603    PUSH_DATA (push, fifo->vram);
 604    PUSH_DATA (push, fifo->vram);
 605    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 606    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 607    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 608    PUSH_DATA (push, 0);
 609    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 610    PUSH_DATA (push, 0);
 611    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 612    PUSH_DATA (push, 1);
 613    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 614    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 615
 616    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 617    PUSH_DATA (push, screen->tesla->handle);
 618
 619    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 620    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 621
 622    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 623    PUSH_DATA (push, screen->sync->handle);
 624    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 625    for (i = 0; i < 11; ++i)
 626       PUSH_DATA(push, fifo->vram);
 627    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 628    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 629       PUSH_DATA(push, fifo->vram);
 630
 631    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 632    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 633    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 634    PUSH_DATA (push, 0xf);
 635
 636    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 637       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 638       PUSH_DATA (push, 0x18);
 639    }
 640
 641    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 642    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 643
 644    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 645    for (i = 0; i < 8; ++i)
 646       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 647
 648    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 649    PUSH_DATA (push, 1);
 650
 651    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 652    PUSH_DATA (push, 0);
 653    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 654    PUSH_DATA (push, 0);
 655    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 656    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 657    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 658    PUSH_DATA (push, 0);
 659    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 660    PUSH_DATA (push, 1);
 661    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 662    PUSH_DATA (push, 1);
 663
 664    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 665       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 666       PUSH_DATA (push, 0);
 667    }
 668
 669    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 670    PUSH_DATA (push, 0);
 671    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 672    PUSH_DATA (push, 0);
 673    PUSH_DATA (push, 0);
 674    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 675    PUSH_DATA (push, 0x3f);
 676
 677    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 678    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 679    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 680
 681    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 682    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 683    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 684
 685    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 686    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 687    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 688
 689    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 690    PUSH_DATAh(push, screen->tls_bo->offset);
 691    PUSH_DATA (push, screen->tls_bo->offset);
 692    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 693
 694    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 695    PUSH_DATAh(push, screen->stack_bo->offset);
 696    PUSH_DATA (push, screen->stack_bo->offset);
 697    PUSH_DATA (push, 4);
 698
 699    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 700    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 701    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 702    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 703
 704    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 705    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 706    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 707    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 708
 709    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 710    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 711    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 712    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 713
 714    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 715    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 716    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 717    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 718
 719    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 720    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 721    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 722    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 723
 724    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 725    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 726    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 727    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 728    PUSH_DATAf(push, 0.0f);
 729    PUSH_DATAf(push, 0.0f);
 730    PUSH_DATAf(push, 0.0f);
 731    PUSH_DATAf(push, 0.0f);
 732    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 733    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 734    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 735
 736    nv50_upload_ms_info(push);
 737
 738    /* max TIC (bits 4:8) & TSC bindings, per program type */
 739    for (i = 0; i < 3; ++i) {
 740       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 741       PUSH_DATA (push, 0x54);
 742    }
 743
 744    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 745    PUSH_DATAh(push, screen->txc->offset);
 746    PUSH_DATA (push, screen->txc->offset);
 747    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 748
 749    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 750    PUSH_DATAh(push, screen->txc->offset + 65536);
 751    PUSH_DATA (push, screen->txc->offset + 65536);
 752    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 753
 754    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 755    PUSH_DATA (push, 0);
 756
 757    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 758    PUSH_DATA (push, 0);
 759    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 760    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 761    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 762    for (i = 0; i < 8 * 2; ++i)
 763       PUSH_DATA(push, 0);
 764    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 765    PUSH_DATA (push, 0);
 766
 767    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 768    PUSH_DATA (push, 1);
 769    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 770       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 771       PUSH_DATAf(push, 0.0f);
 772       PUSH_DATAf(push, 1.0f);
 773       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 774       PUSH_DATA (push, 8192 << 16);
 775       PUSH_DATA (push, 8192 << 16);
 776    }
 777
 778    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 779 #ifdef NV50_SCISSORS_CLIPPING
 780    PUSH_DATA (push, 0x0000);
 781 #else
 782    PUSH_DATA (push, 0x1080);
 783 #endif
 784
 785    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 786    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 787
 788    /* We use scissors instead of exact view volume clipping,
 789     * so they're always enabled.
 790     */
 791    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 792       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 793       PUSH_DATA (push, 1);
 794       PUSH_DATA (push, 8192 << 16);
 795       PUSH_DATA (push, 8192 << 16);
 796    }
 797
 798    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 799    PUSH_DATA (push, 1);
 800    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 801    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 802    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 803    PUSH_DATA (push, 0x11111111);
 804    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 805    PUSH_DATA (push, 1);
 806
 807    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 808    PUSH_DATA (push, 0);
 809    if (screen->base.class_3d >= NV84_3D_CLASS) {
 810       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 811       PUSH_DATA (push, 0);
 812    }
 813
 814    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 815    PUSH_DATA (push, 1);
 816    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 817    PUSH_DATA (push, 1);
 818
 819    PUSH_KICK (push);
 820 }
 821
 822 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 823       uint64_t *tls_size)
 824 {
 825    struct nouveau_device *dev = screen->base.device;
 826    int ret;
 827
 828    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 829          ONE_TEMP_SIZE;
 830    if (nouveau_mesa_debug)
 831       debug_printf("allocating space for %u temps\n",
 832             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 833    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 834          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 835
 836    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 837                         *tls_size, NULL, &screen->tls_bo);
 838    if (ret) {
 839       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 840       return ret;
 841    }
 842
 843    return 0;
 844 }
 845
 846 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 847 {
 848    struct nouveau_pushbuf *push = screen->base.pushbuf;
 849    int ret;
 850    uint64_t tls_size;
 851
 852    if (tls_space < screen->cur_tls_space)
 853       return 0;
 854    if (tls_space > screen->max_tls_space) {
 855       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 856        * LOCAL_WARPS_NO_CLAMP) */
 857       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 858             (unsigned)(tls_space / ONE_TEMP_SIZE),
 859             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 860       return -ENOMEM;
 861    }
 862
 863    nouveau_bo_ref(NULL, &screen->tls_bo);
 864    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 865    if (ret)
 866       return ret;
 867
 868    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 869    PUSH_DATAh(push, screen->tls_bo->offset);
 870    PUSH_DATA (push, screen->tls_bo->offset);
 871    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 872
 873    return 1;
 874 }
 875
 876 struct nouveau_screen *
 877 nv50_screen_create(struct nouveau_device *dev)
 878 {
 879    struct nv50_screen *screen;
 880    struct pipe_screen *pscreen;
 881    struct nouveau_object *chan;
 882    uint64_t value;
 883    uint32_t tesla_class;
 884    unsigned stack_size;
 885    int ret;
 886
 887    screen = CALLOC_STRUCT(nv50_screen);
 888    if (!screen)
 889       return NULL;
 890    pscreen = &screen->base.base;
 891    pscreen->destroy = nv50_screen_destroy;
 892
 893    ret = nouveau_screen_init(&screen->base, dev);
 894    if (ret) {
 895       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 896       goto fail;
 897    }
 898
 899    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 900     *  admit them to VRAM.
 901     */
 902    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 903       PIPE_BIND_VERTEX_BUFFER;
 904    screen->base.sysmem_bindings |=
 905       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 906
 907    screen->base.pushbuf->user_priv = screen;
 908    screen->base.pushbuf->rsvd_kick = 5;
 909
 910    chan = screen->base.channel;
 911
 912    pscreen->context_create = nv50_create;
 913    pscreen->is_format_supported = nv50_screen_is_format_supported;
 914    pscreen->get_param = nv50_screen_get_param;
 915    pscreen->get_shader_param = nv50_screen_get_shader_param;
 916    pscreen->get_paramf = nv50_screen_get_paramf;
 917    pscreen->get_compute_param = nv50_screen_get_compute_param;
 918    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 919    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 920
 921    nv50_screen_init_resource_functions(pscreen);
 922
 923    if (screen->base.device->chipset < 0x84 ||
 924        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 925       /* PMPEG */
 926       nouveau_screen_init_vdec(&screen->base);
 927    } else if (screen->base.device->chipset < 0x98 ||
 928               screen->base.device->chipset == 0xa0) {
 929       /* VP2 */
 930       screen->base.base.get_video_param = nv84_screen_get_video_param;
 931       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 932    } else {
 933       /* VP3/4 */
 934       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 935       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 936    }
 937
 938    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 939                         NULL, &screen->fence.bo);
 940    if (ret) {
 941       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 942       goto fail;
 943    }
 944
 945    nouveau_bo_map(screen->fence.bo, 0, NULL);
 946    screen->fence.map = screen->fence.bo->map;
 947    screen->base.fence.emit = nv50_screen_fence_emit;
 948    screen->base.fence.update = nv50_screen_fence_update;
 949
 950    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 951                             &(struct nv04_notify){ .length = 32 },
 952                             sizeof(struct nv04_notify), &screen->sync);
 953    if (ret) {
 954       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 955       goto fail;
 956    }
 957
 958    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 959                             NULL, 0, &screen->m2mf);
 960    if (ret) {
 961       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 962       goto fail;
 963    }
 964
 965    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 966                             NULL, 0, &screen->eng2d);
 967    if (ret) {
 968       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 969       goto fail;
 970    }
 971
 972    switch (dev->chipset & 0xf0) {
 973    case 0x50:
 974       tesla_class = NV50_3D_CLASS;
 975       break;
 976    case 0x80:
 977    case 0x90:
 978       tesla_class = NV84_3D_CLASS;
 979       break;
 980    case 0xa0:
 981       switch (dev->chipset) {
 982       case 0xa0:
 983       case 0xaa:
 984       case 0xac:
 985          tesla_class = NVA0_3D_CLASS;
 986          break;
 987       case 0xaf:
 988          tesla_class = NVAF_3D_CLASS;
 989          break;
 990       default:
 991          tesla_class = NVA3_3D_CLASS;
 992          break;
 993       }
 994       break;
 995    default:
 996       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 997       goto fail;
 998    }
 999    screen->base.class_3d = tesla_class;
1000
1001    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
1002                             NULL, 0, &screen->tesla);
1003    if (ret) {
1004       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
1005       goto fail;
1006    }
1007
1008    /* This over-allocates by a page. The GP, which would execute at the end of
1009     * the last page, would trigger faults. The going theory is that it
1010     * prefetches up to a certain amount.
1011     */
1012    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
1013                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
1014                         NULL, &screen->code);
1015    if (ret) {
1016       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
1017       goto fail;
1018    }
1019
1020    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1021    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1022    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1023
1024    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1025
1026    screen->TPs = util_bitcount(value & 0xffff);
1027    screen->MPsInTP = util_bitcount(value & 0x0f000000);
1028
1029    screen->mp_count = screen->TPs * screen->MPsInTP;
1030
1031    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1032          STACK_WARPS_ALLOC * 64 * 8;
1033
1034    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1035                         &screen->stack_bo);
1036    if (ret) {
1037       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1038       goto fail;
1039    }
1040
1041    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1042          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1043          ONE_TEMP_SIZE;
1044    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1045    screen->max_tls_space /= 2; /* half of vram */
1046
1047    /* hw can address max 64 KiB */
1048    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1049
1050    uint64_t tls_size;
1051    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1052    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1053    if (ret)
1054       goto fail;
1055
1056    if (nouveau_mesa_debug)
1057       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1058             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1059
1060    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1061                         &screen->uniforms);
1062    if (ret) {
1063       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1064       goto fail;
1065    }
1066
1067    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1068                         &screen->txc);
1069    if (ret) {
1070       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1071       goto fail;
1072    }
1073
1074    screen->tic.entries = CALLOC(4096, sizeof(void *));
1075    screen->tsc.entries = screen->tic.entries + 2048;
1076
1077    if (!nv50_blitter_create(screen))
1078       goto fail;
1079
1080    nv50_screen_init_hwctx(screen);
1081
1082    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1083    if (ret) {
1084       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1085       goto fail;
1086    }
1087
1088    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1089
1090    return &screen->base;
1091
1092 fail:
1093    screen->base.base.context_create = NULL;
1094    return &screen->base;
1095 }
1096
1097 int
1098 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1099 {
1100    int i = screen->tic.next;
1101
1102    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1103       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1104
1105    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1106
1107    if (screen->tic.entries[i])
1108       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1109
1110    screen->tic.entries[i] = entry;
1111    return i;
1112 }
1113
1114 int
1115 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1116 {
1117    int i = screen->tsc.next;
1118
1119    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1120       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1121
1122    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1123
1124    if (screen->tsc.entries[i])
1125       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1126
1127    screen->tsc.entries[i] = entry;
1128    return i;
1129 }