src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* transfers & shared are always supported */
  79    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  80                  PIPE_BIND_TRANSFER_WRITE |
  81                  PIPE_BIND_LINEAR |
  82                  PIPE_BIND_SHARED);
  83
  84    return (( nv50_format_table[format].usage |
  85             nv50_vertex_format[format].usage) & bindings) == bindings;
  86 }
  87
  88 static int
  89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  90 {
  91    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  92    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  93
  94    switch (param) {
  95    /* non-boolean caps */
  96    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  97       return 14;
  98    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  99       return 12;
 100    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 101       return 14;
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103       return 512;
 104    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 105    case PIPE_CAP_MIN_TEXEL_OFFSET:
 106       return -8;
 107    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109       return 7;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 128 * 1024 * 1024;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 113       return 330;
 114    case PIPE_CAP_MAX_RENDER_TARGETS:
 115       return 8;
 116    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 117       return 1;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 119       return 4;
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122       return 64;
 123    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 124    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 125       return 1024;
 126    case PIPE_CAP_MAX_VERTEX_STREAMS:
 127       return 1;
 128    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 129       return 2048;
 130    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 131       return 256;
 132    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 133       return 16; /* 256 for binding as RT, but that's not possible in GL */
 134    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 135       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 136    case PIPE_CAP_MAX_VIEWPORTS:
 137       return NV50_MAX_VIEWPORTS;
 138    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 139       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 140    case PIPE_CAP_ENDIANNESS:
 141       return PIPE_ENDIAN_LITTLE;
 142    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 143       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 144
 145    /* supported caps */
 146    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 147    case PIPE_CAP_TEXTURE_SWIZZLE:
 148    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 149    case PIPE_CAP_NPOT_TEXTURES:
 150    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151    case PIPE_CAP_ANISOTROPIC_FILTER:
 152    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 153    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 154    case PIPE_CAP_TWO_SIDED_STENCIL:
 155    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 156    case PIPE_CAP_POINT_SPRITE:
 157    case PIPE_CAP_SM3:
 158    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 159    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 160    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 161    case PIPE_CAP_QUERY_TIMESTAMP:
 162    case PIPE_CAP_QUERY_TIME_ELAPSED:
 163    case PIPE_CAP_OCCLUSION_QUERY:
 164    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 165    case PIPE_CAP_INDEP_BLEND_ENABLE:
 166    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 167    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 168    case PIPE_CAP_PRIMITIVE_RESTART:
 169    case PIPE_CAP_TGSI_INSTANCEID:
 170    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 171    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 172    case PIPE_CAP_CONDITIONAL_RENDER:
 173    case PIPE_CAP_TEXTURE_BARRIER:
 174    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 175    case PIPE_CAP_START_INSTANCE:
 176    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 177    case PIPE_CAP_USER_INDEX_BUFFERS:
 178    case PIPE_CAP_USER_VERTEX_BUFFERS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 181    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 182    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 183    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 184    case PIPE_CAP_CLIP_HALFZ:
 185    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 186    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 187    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 188    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 189    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 190    case PIPE_CAP_TGSI_TXQS:
 191    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 192    case PIPE_CAP_SHAREABLE_SHADERS:
 193    case PIPE_CAP_CLEAR_TEXTURE:
 194    case PIPE_CAP_COMPUTE:
 195    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 196    case PIPE_CAP_INVALIDATE_BUFFER:
 197    case PIPE_CAP_STRING_MARKER:
 198    case PIPE_CAP_CULL_DISTANCE:
 199       return 1;
 200    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 201       return 1; /* class_3d >= NVA0_3D_CLASS; */
 202    /* supported on nva0+ */
 203    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 204       return class_3d >= NVA0_3D_CLASS;
 205    /* supported on nva3+ */
 206    case PIPE_CAP_CUBE_MAP_ARRAY:
 207    case PIPE_CAP_INDEP_BLEND_FUNC:
 208    case PIPE_CAP_TEXTURE_QUERY_LOD:
 209    case PIPE_CAP_SAMPLE_SHADING:
 210    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 211       return class_3d >= NVA3_3D_CLASS;
 212
 213    /* unsupported caps */
 214    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 215    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 216    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 217    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 218    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 219    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 220    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 221    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 222    case PIPE_CAP_TGSI_TEXCOORD:
 223    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 224    case PIPE_CAP_TEXTURE_GATHER_SM5:
 225    case PIPE_CAP_FAKE_SW_MSAA:
 226    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 227    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 228    case PIPE_CAP_DRAW_INDIRECT:
 229    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 230    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 231    case PIPE_CAP_VERTEXID_NOBASE:
 232    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 233    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 234    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 235    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 236    case PIPE_CAP_DRAW_PARAMETERS:
 237    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 238    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 239    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 240    case PIPE_CAP_GENERATE_MIPMAP:
 241    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 242    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 243    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 244    case PIPE_CAP_QUERY_MEMORY_INFO:
 245    case PIPE_CAP_PCI_GROUP:
 246    case PIPE_CAP_PCI_BUS:
 247    case PIPE_CAP_PCI_DEVICE:
 248    case PIPE_CAP_PCI_FUNCTION:
 249    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 250    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 251    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 252       return 0;
 253
 254    case PIPE_CAP_VENDOR_ID:
 255       return 0x10de;
 256    case PIPE_CAP_DEVICE_ID: {
 257       uint64_t device_id;
 258       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 259          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 260          return -1;
 261       }
 262       return device_id;
 263    }
 264    case PIPE_CAP_ACCELERATED:
 265       return 1;
 266    case PIPE_CAP_VIDEO_MEMORY:
 267       return dev->vram_size >> 20;
 268    case PIPE_CAP_UMA:
 269       return 0;
 270    }
 271
 272    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 273    return 0;
 274 }
 275
 276 static int
 277 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 278                              enum pipe_shader_cap param)
 279 {
 280    switch (shader) {
 281    case PIPE_SHADER_VERTEX:
 282    case PIPE_SHADER_GEOMETRY:
 283    case PIPE_SHADER_FRAGMENT:
 284       break;
 285    case PIPE_SHADER_COMPUTE:
 286    default:
 287       return 0;
 288    }
 289
 290    switch (param) {
 291    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 292    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 293    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 294    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 295       return 16384;
 296    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 297       return 4;
 298    case PIPE_SHADER_CAP_MAX_INPUTS:
 299       if (shader == PIPE_SHADER_VERTEX)
 300          return 32;
 301       return 15;
 302    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 303       return 16;
 304    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 305       return 65536;
 306    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 307       return NV50_MAX_PIPE_CONSTBUFS;
 308    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 309    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 310       return shader != PIPE_SHADER_FRAGMENT;
 311    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 312    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 313       return 1;
 314    case PIPE_SHADER_CAP_MAX_PREDS:
 315       return 0;
 316    case PIPE_SHADER_CAP_MAX_TEMPS:
 317       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 318    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 319       return 1;
 320    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 321       return 1;
 322    case PIPE_SHADER_CAP_SUBROUTINES:
 323       return 0; /* please inline, or provide function declarations */
 324    case PIPE_SHADER_CAP_INTEGERS:
 325       return 1;
 326    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 327       /* The chip could handle more sampler views than samplers */
 328    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 329       return MIN2(16, PIPE_MAX_SAMPLERS);
 330    case PIPE_SHADER_CAP_PREFERRED_IR:
 331       return PIPE_SHADER_IR_TGSI;
 332    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 333       return 32;
 334    case PIPE_SHADER_CAP_DOUBLES:
 335    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 336    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 337    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 338    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 339    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 340    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 341    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 342       return 0;
 343    default:
 344       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 345       return 0;
 346    }
 347 }
 348
 349 static float
 350 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 351 {
 352    switch (param) {
 353    case PIPE_CAPF_MAX_LINE_WIDTH:
 354    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 355       return 10.0f;
 356    case PIPE_CAPF_MAX_POINT_WIDTH:
 357    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 358       return 64.0f;
 359    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 360       return 16.0f;
 361    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 362       return 4.0f;
 363    case PIPE_CAPF_GUARD_BAND_LEFT:
 364    case PIPE_CAPF_GUARD_BAND_TOP:
 365       return 0.0f;
 366    case PIPE_CAPF_GUARD_BAND_RIGHT:
 367    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 368       return 0.0f; /* that or infinity */
 369    }
 370
 371    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 372    return 0.0f;
 373 }
 374
 375 static int
 376 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 377                               enum pipe_shader_ir ir_type,
 378                               enum pipe_compute_cap param, void *data)
 379 {
 380    struct nv50_screen *screen = nv50_screen(pscreen);
 381
 382 #define RET(x) do {                  \
 383    if (data)                         \
 384       memcpy(data, x, sizeof(x));    \
 385    return sizeof(x);                 \
 386 } while (0)
 387
 388    switch (param) {
 389    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 390       RET((uint64_t []) { 2 });
 391    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 392       RET(((uint64_t []) { 65535, 65535 }));
 393    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 394       RET(((uint64_t []) { 512, 512, 64 }));
 395    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 396       RET((uint64_t []) { 512 });
 397    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 398       RET((uint64_t []) { 1ULL << 32 });
 399    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 400       RET((uint64_t []) { 16 << 10 });
 401    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 402       RET((uint64_t []) { 16 << 10 });
 403    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 404       RET((uint64_t []) { 4096 });
 405    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 406       RET((uint32_t []) { 32 });
 407    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 408       RET((uint64_t []) { 1ULL << 40 });
 409    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 410       RET((uint32_t []) { 0 });
 411    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 412       RET((uint32_t []) { screen->mp_count });
 413    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 414       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 415    default:
 416       return 0;
 417    }
 418
 419 #undef RET
 420 }
 421
 422 static void
 423 nv50_screen_destroy(struct pipe_screen *pscreen)
 424 {
 425    struct nv50_screen *screen = nv50_screen(pscreen);
 426
 427    if (!nouveau_drm_screen_unref(&screen->base))
 428       return;
 429
 430    if (screen->base.fence.current) {
 431       struct nouveau_fence *current = NULL;
 432
 433       /* nouveau_fence_wait will create a new current fence, so wait on the
 434        * _current_ one, and remove both.
 435        */
 436       nouveau_fence_ref(screen->base.fence.current, &current);
 437       nouveau_fence_wait(current, NULL);
 438       nouveau_fence_ref(NULL, &current);
 439       nouveau_fence_ref(NULL, &screen->base.fence.current);
 440    }
 441    if (screen->base.pushbuf)
 442       screen->base.pushbuf->user_priv = NULL;
 443
 444    if (screen->blitter)
 445       nv50_blitter_destroy(screen);
 446    if (screen->pm.prog) {
 447       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 448       nv50_program_destroy(NULL, screen->pm.prog);
 449       FREE(screen->pm.prog);
 450    }
 451
 452    nouveau_bo_ref(NULL, &screen->code);
 453    nouveau_bo_ref(NULL, &screen->tls_bo);
 454    nouveau_bo_ref(NULL, &screen->stack_bo);
 455    nouveau_bo_ref(NULL, &screen->txc);
 456    nouveau_bo_ref(NULL, &screen->uniforms);
 457    nouveau_bo_ref(NULL, &screen->fence.bo);
 458
 459    nouveau_heap_destroy(&screen->vp_code_heap);
 460    nouveau_heap_destroy(&screen->gp_code_heap);
 461    nouveau_heap_destroy(&screen->fp_code_heap);
 462
 463    FREE(screen->tic.entries);
 464
 465    nouveau_object_del(&screen->tesla);
 466    nouveau_object_del(&screen->eng2d);
 467    nouveau_object_del(&screen->m2mf);
 468    nouveau_object_del(&screen->compute);
 469    nouveau_object_del(&screen->sync);
 470
 471    nouveau_screen_fini(&screen->base);
 472
 473    FREE(screen);
 474 }
 475
 476 static void
 477 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 478 {
 479    struct nv50_screen *screen = nv50_screen(pscreen);
 480    struct nouveau_pushbuf *push = screen->base.pushbuf;
 481
 482    /* we need to do it after possible flush in MARK_RING */
 483    *sequence = ++screen->base.fence.sequence;
 484
 485    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 486    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 487    PUSH_DATAh(push, screen->fence.bo->offset);
 488    PUSH_DATA (push, screen->fence.bo->offset);
 489    PUSH_DATA (push, *sequence);
 490    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 491                     NV50_3D_QUERY_GET_UNK4 |
 492                     NV50_3D_QUERY_GET_UNIT_CROP |
 493                     NV50_3D_QUERY_GET_TYPE_QUERY |
 494                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 495                     NV50_3D_QUERY_GET_SHORT);
 496 }
 497
 498 static u32
 499 nv50_screen_fence_update(struct pipe_screen *pscreen)
 500 {
 501    return nv50_screen(pscreen)->fence.map[0];
 502 }
 503
 504 static void
 505 nv50_screen_init_hwctx(struct nv50_screen *screen)
 506 {
 507    struct nouveau_pushbuf *push = screen->base.pushbuf;
 508    struct nv04_fifo *fifo;
 509    unsigned i;
 510
 511    fifo = (struct nv04_fifo *)screen->base.channel->data;
 512
 513    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 514    PUSH_DATA (push, screen->m2mf->handle);
 515    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 516    PUSH_DATA (push, screen->sync->handle);
 517    PUSH_DATA (push, fifo->vram);
 518    PUSH_DATA (push, fifo->vram);
 519
 520    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 521    PUSH_DATA (push, screen->eng2d->handle);
 522    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 523    PUSH_DATA (push, screen->sync->handle);
 524    PUSH_DATA (push, fifo->vram);
 525    PUSH_DATA (push, fifo->vram);
 526    PUSH_DATA (push, fifo->vram);
 527    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 528    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 529    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 530    PUSH_DATA (push, 0);
 531    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 532    PUSH_DATA (push, 0);
 533    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 534    PUSH_DATA (push, 1);
 535    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 536    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 537
 538    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 539    PUSH_DATA (push, screen->tesla->handle);
 540
 541    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 542    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 543
 544    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 545    PUSH_DATA (push, screen->sync->handle);
 546    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 547    for (i = 0; i < 11; ++i)
 548       PUSH_DATA(push, fifo->vram);
 549    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 550    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 551       PUSH_DATA(push, fifo->vram);
 552
 553    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 554    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 555    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 556    PUSH_DATA (push, 0xf);
 557
 558    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 559       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 560       PUSH_DATA (push, 0x18);
 561    }
 562
 563    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 564    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 565
 566    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 567    for (i = 0; i < 8; ++i)
 568       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 569
 570    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 571    PUSH_DATA (push, 1);
 572
 573    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 574    PUSH_DATA (push, 0);
 575    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 576    PUSH_DATA (push, 0);
 577    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 578    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 579    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 580    PUSH_DATA (push, 0);
 581    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 582    PUSH_DATA (push, 1);
 583    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 584    PUSH_DATA (push, 1);
 585
 586    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 587       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 588       PUSH_DATA (push, 0);
 589    }
 590
 591    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 592    PUSH_DATA (push, 0);
 593    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 594    PUSH_DATA (push, 0);
 595    PUSH_DATA (push, 0);
 596    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 597    PUSH_DATA (push, 0x3f);
 598
 599    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 600    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 601    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 602
 603    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 604    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 605    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 606
 607    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 608    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 609    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 610
 611    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 612    PUSH_DATAh(push, screen->tls_bo->offset);
 613    PUSH_DATA (push, screen->tls_bo->offset);
 614    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 615
 616    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 617    PUSH_DATAh(push, screen->stack_bo->offset);
 618    PUSH_DATA (push, screen->stack_bo->offset);
 619    PUSH_DATA (push, 4);
 620
 621    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 622    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 623    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 624    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 625
 626    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 627    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 628    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 629    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 630
 631    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 632    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 633    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 634    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 635
 636    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 637    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 638    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 639    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 640
 641    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 642    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 643    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 644    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 645
 646    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 647    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 648    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 649    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 650    PUSH_DATAf(push, 0.0f);
 651    PUSH_DATAf(push, 0.0f);
 652    PUSH_DATAf(push, 0.0f);
 653    PUSH_DATAf(push, 0.0f);
 654    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 655    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 656    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 657
 658    nv50_upload_ms_info(push);
 659
 660    /* max TIC (bits 4:8) & TSC bindings, per program type */
 661    for (i = 0; i < 3; ++i) {
 662       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 663       PUSH_DATA (push, 0x54);
 664    }
 665
 666    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 667    PUSH_DATAh(push, screen->txc->offset);
 668    PUSH_DATA (push, screen->txc->offset);
 669    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 670
 671    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 672    PUSH_DATAh(push, screen->txc->offset + 65536);
 673    PUSH_DATA (push, screen->txc->offset + 65536);
 674    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 675
 676    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 677    PUSH_DATA (push, 0);
 678
 679    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 680    PUSH_DATA (push, 0);
 681    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 682    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 683    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 684    for (i = 0; i < 8 * 2; ++i)
 685       PUSH_DATA(push, 0);
 686    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 687    PUSH_DATA (push, 0);
 688
 689    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 690    PUSH_DATA (push, 1);
 691    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 692       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 693       PUSH_DATAf(push, 0.0f);
 694       PUSH_DATAf(push, 1.0f);
 695       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 696       PUSH_DATA (push, 8192 << 16);
 697       PUSH_DATA (push, 8192 << 16);
 698    }
 699
 700    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 701 #ifdef NV50_SCISSORS_CLIPPING
 702    PUSH_DATA (push, 0x0000);
 703 #else
 704    PUSH_DATA (push, 0x1080);
 705 #endif
 706
 707    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 708    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 709
 710    /* We use scissors instead of exact view volume clipping,
 711     * so they're always enabled.
 712     */
 713    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 714       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 715       PUSH_DATA (push, 1);
 716       PUSH_DATA (push, 8192 << 16);
 717       PUSH_DATA (push, 8192 << 16);
 718    }
 719
 720    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 721    PUSH_DATA (push, 1);
 722    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 723    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 724    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 725    PUSH_DATA (push, 0x11111111);
 726    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 727    PUSH_DATA (push, 1);
 728
 729    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 730    PUSH_DATA (push, 0);
 731    if (screen->base.class_3d >= NV84_3D_CLASS) {
 732       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 733       PUSH_DATA (push, 0);
 734    }
 735
 736    PUSH_KICK (push);
 737 }
 738
 739 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 740       uint64_t *tls_size)
 741 {
 742    struct nouveau_device *dev = screen->base.device;
 743    int ret;
 744
 745    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 746          ONE_TEMP_SIZE;
 747    if (nouveau_mesa_debug)
 748       debug_printf("allocating space for %u temps\n",
 749             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 750    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 751          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 752
 753    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 754                         *tls_size, NULL, &screen->tls_bo);
 755    if (ret) {
 756       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 757       return ret;
 758    }
 759
 760    return 0;
 761 }
 762
 763 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 764 {
 765    struct nouveau_pushbuf *push = screen->base.pushbuf;
 766    int ret;
 767    uint64_t tls_size;
 768
 769    if (tls_space < screen->cur_tls_space)
 770       return 0;
 771    if (tls_space > screen->max_tls_space) {
 772       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 773        * LOCAL_WARPS_NO_CLAMP) */
 774       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 775             (unsigned)(tls_space / ONE_TEMP_SIZE),
 776             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 777       return -ENOMEM;
 778    }
 779
 780    nouveau_bo_ref(NULL, &screen->tls_bo);
 781    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 782    if (ret)
 783       return ret;
 784
 785    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 786    PUSH_DATAh(push, screen->tls_bo->offset);
 787    PUSH_DATA (push, screen->tls_bo->offset);
 788    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 789
 790    return 1;
 791 }
 792
 793 struct nouveau_screen *
 794 nv50_screen_create(struct nouveau_device *dev)
 795 {
 796    struct nv50_screen *screen;
 797    struct pipe_screen *pscreen;
 798    struct nouveau_object *chan;
 799    uint64_t value;
 800    uint32_t tesla_class;
 801    unsigned stack_size;
 802    int ret;
 803
 804    screen = CALLOC_STRUCT(nv50_screen);
 805    if (!screen)
 806       return NULL;
 807    pscreen = &screen->base.base;
 808    pscreen->destroy = nv50_screen_destroy;
 809
 810    ret = nouveau_screen_init(&screen->base, dev);
 811    if (ret) {
 812       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 813       goto fail;
 814    }
 815
 816    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 817     *  admit them to VRAM.
 818     */
 819    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 820       PIPE_BIND_VERTEX_BUFFER;
 821    screen->base.sysmem_bindings |=
 822       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 823
 824    screen->base.pushbuf->user_priv = screen;
 825    screen->base.pushbuf->rsvd_kick = 5;
 826
 827    chan = screen->base.channel;
 828
 829    pscreen->context_create = nv50_create;
 830    pscreen->is_format_supported = nv50_screen_is_format_supported;
 831    pscreen->get_param = nv50_screen_get_param;
 832    pscreen->get_shader_param = nv50_screen_get_shader_param;
 833    pscreen->get_paramf = nv50_screen_get_paramf;
 834    pscreen->get_compute_param = nv50_screen_get_compute_param;
 835    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 836    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 837
 838    nv50_screen_init_resource_functions(pscreen);
 839
 840    if (screen->base.device->chipset < 0x84 ||
 841        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 842       /* PMPEG */
 843       nouveau_screen_init_vdec(&screen->base);
 844    } else if (screen->base.device->chipset < 0x98 ||
 845               screen->base.device->chipset == 0xa0) {
 846       /* VP2 */
 847       screen->base.base.get_video_param = nv84_screen_get_video_param;
 848       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 849    } else {
 850       /* VP3/4 */
 851       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 852       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 853    }
 854
 855    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 856                         NULL, &screen->fence.bo);
 857    if (ret) {
 858       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 859       goto fail;
 860    }
 861
 862    nouveau_bo_map(screen->fence.bo, 0, NULL);
 863    screen->fence.map = screen->fence.bo->map;
 864    screen->base.fence.emit = nv50_screen_fence_emit;
 865    screen->base.fence.update = nv50_screen_fence_update;
 866
 867    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 868                             &(struct nv04_notify){ .length = 32 },
 869                             sizeof(struct nv04_notify), &screen->sync);
 870    if (ret) {
 871       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 872       goto fail;
 873    }
 874
 875    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 876                             NULL, 0, &screen->m2mf);
 877    if (ret) {
 878       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 879       goto fail;
 880    }
 881
 882    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 883                             NULL, 0, &screen->eng2d);
 884    if (ret) {
 885       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 886       goto fail;
 887    }
 888
 889    switch (dev->chipset & 0xf0) {
 890    case 0x50:
 891       tesla_class = NV50_3D_CLASS;
 892       break;
 893    case 0x80:
 894    case 0x90:
 895       tesla_class = NV84_3D_CLASS;
 896       break;
 897    case 0xa0:
 898       switch (dev->chipset) {
 899       case 0xa0:
 900       case 0xaa:
 901       case 0xac:
 902          tesla_class = NVA0_3D_CLASS;
 903          break;
 904       case 0xaf:
 905          tesla_class = NVAF_3D_CLASS;
 906          break;
 907       default:
 908          tesla_class = NVA3_3D_CLASS;
 909          break;
 910       }
 911       break;
 912    default:
 913       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 914       goto fail;
 915    }
 916    screen->base.class_3d = tesla_class;
 917
 918    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 919                             NULL, 0, &screen->tesla);
 920    if (ret) {
 921       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 922       goto fail;
 923    }
 924
 925    /* This over-allocates by a page. The GP, which would execute at the end of
 926     * the last page, would trigger faults. The going theory is that it
 927     * prefetches up to a certain amount.
 928     */
 929    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 930                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 931                         NULL, &screen->code);
 932    if (ret) {
 933       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 934       goto fail;
 935    }
 936
 937    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 938    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 939    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 940
 941    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 942
 943    screen->TPs = util_bitcount(value & 0xffff);
 944    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 945
 946    screen->mp_count = screen->TPs * screen->MPsInTP;
 947
 948    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 949          STACK_WARPS_ALLOC * 64 * 8;
 950
 951    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 952                         &screen->stack_bo);
 953    if (ret) {
 954       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 955       goto fail;
 956    }
 957
 958    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 959          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 960          ONE_TEMP_SIZE;
 961    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 962    screen->max_tls_space /= 2; /* half of vram */
 963
 964    /* hw can address max 64 KiB */
 965    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 966
 967    uint64_t tls_size;
 968    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 969    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 970    if (ret)
 971       goto fail;
 972
 973    if (nouveau_mesa_debug)
 974       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 975             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 976
 977    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 978                         &screen->uniforms);
 979    if (ret) {
 980       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 981       goto fail;
 982    }
 983
 984    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 985                         &screen->txc);
 986    if (ret) {
 987       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 988       goto fail;
 989    }
 990
 991    screen->tic.entries = CALLOC(4096, sizeof(void *));
 992    screen->tsc.entries = screen->tic.entries + 2048;
 993
 994    if (!nv50_blitter_create(screen))
 995       goto fail;
 996
 997    nv50_screen_init_hwctx(screen);
 998
 999    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1000    if (ret) {
1001       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1002       goto fail;
1003    }
1004
1005    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1006
1007    return &screen->base;
1008
1009 fail:
1010    screen->base.base.context_create = NULL;
1011    return &screen->base;
1012 }
1013
1014 int
1015 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1016 {
1017    int i = screen->tic.next;
1018
1019    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1020       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1021
1022    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1023
1024    if (screen->tic.entries[i])
1025       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1026
1027    screen->tic.entries[i] = entry;
1028    return i;
1029 }
1030
1031 int
1032 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1033 {
1034    int i = screen->tsc.next;
1035
1036    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1037       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1038
1039    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1040
1041    if (screen->tsc.entries[i])
1042       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1043
1044    screen->tsc.entries[i] = entry;
1045    return i;
1046 }