src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* shared is always supported */
  79    bindings &= ~(PIPE_BIND_LINEAR |
  80                  PIPE_BIND_SHARED);
  81
  82    return (( nv50_format_table[format].usage |
  83             nv50_vertex_format[format].usage) & bindings) == bindings;
  84 }
  85
  86 static int
  87 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  88 {
  89    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  90    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  91
  92    switch (param) {
  93    /* non-boolean caps */
  94    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  97       return 12;
  98    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  99       return 14;
 100    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 101       return 512;
 102    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 103    case PIPE_CAP_MIN_TEXEL_OFFSET:
 104       return -8;
 105    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MAX_TEXEL_OFFSET:
 107       return 7;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 128 * 1024 * 1024;
 110    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 111       return 330;
 112    case PIPE_CAP_MAX_RENDER_TARGETS:
 113       return 8;
 114    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 115       return 1;
 116    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 117       return 4;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 120       return 64;
 121    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 122    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 123       return 1024;
 124    case PIPE_CAP_MAX_VERTEX_STREAMS:
 125       return 1;
 126    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 127       return 2048;
 128    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 129       return 256;
 130    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 131       return 16; /* 256 for binding as RT, but that's not possible in GL */
 132    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 133       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 134    case PIPE_CAP_MAX_VIEWPORTS:
 135       return NV50_MAX_VIEWPORTS;
 136    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 137       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 138    case PIPE_CAP_ENDIANNESS:
 139       return PIPE_ENDIAN_LITTLE;
 140    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 141       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 142    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 143       return NV50_MAX_WINDOW_RECTANGLES;
 144
 145    /* supported caps */
 146    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 147    case PIPE_CAP_TEXTURE_SWIZZLE:
 148    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 149    case PIPE_CAP_NPOT_TEXTURES:
 150    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 152    case PIPE_CAP_ANISOTROPIC_FILTER:
 153    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 154    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 155    case PIPE_CAP_TWO_SIDED_STENCIL:
 156    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 157    case PIPE_CAP_POINT_SPRITE:
 158    case PIPE_CAP_SM3:
 159    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 160    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 161    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 162    case PIPE_CAP_QUERY_TIMESTAMP:
 163    case PIPE_CAP_QUERY_TIME_ELAPSED:
 164    case PIPE_CAP_OCCLUSION_QUERY:
 165    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 166    case PIPE_CAP_INDEP_BLEND_ENABLE:
 167    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 168    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 169    case PIPE_CAP_PRIMITIVE_RESTART:
 170    case PIPE_CAP_TGSI_INSTANCEID:
 171    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 172    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173    case PIPE_CAP_CONDITIONAL_RENDER:
 174    case PIPE_CAP_TEXTURE_BARRIER:
 175    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 176    case PIPE_CAP_START_INSTANCE:
 177    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 178    case PIPE_CAP_USER_VERTEX_BUFFERS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 181    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 182    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 183    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 184    case PIPE_CAP_CLIP_HALFZ:
 185    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 186    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 187    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 188    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 189    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 190    case PIPE_CAP_TGSI_TXQS:
 191    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 192    case PIPE_CAP_SHAREABLE_SHADERS:
 193    case PIPE_CAP_CLEAR_TEXTURE:
 194    case PIPE_CAP_COMPUTE:
 195    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 196    case PIPE_CAP_INVALIDATE_BUFFER:
 197    case PIPE_CAP_STRING_MARKER:
 198    case PIPE_CAP_CULL_DISTANCE:
 199    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 200    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 201    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 202    case PIPE_CAP_TGSI_CLOCK:
 203    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 204       return 1;
 205    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 206       return 1; /* class_3d >= NVA0_3D_CLASS; */
 207    /* supported on nva0+ */
 208    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 209       return class_3d >= NVA0_3D_CLASS;
 210    /* supported on nva3+ */
 211    case PIPE_CAP_CUBE_MAP_ARRAY:
 212    case PIPE_CAP_INDEP_BLEND_FUNC:
 213    case PIPE_CAP_TEXTURE_QUERY_LOD:
 214    case PIPE_CAP_SAMPLE_SHADING:
 215    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 216       return class_3d >= NVA3_3D_CLASS;
 217
 218    /* unsupported caps */
 219    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 220    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 221    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 222    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 223    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 224    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 225    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 226    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 227    case PIPE_CAP_TGSI_TEXCOORD:
 228    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 229    case PIPE_CAP_TEXTURE_GATHER_SM5:
 230    case PIPE_CAP_FAKE_SW_MSAA:
 231    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 232    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 233    case PIPE_CAP_DRAW_INDIRECT:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 235    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 236    case PIPE_CAP_VERTEXID_NOBASE:
 237    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 238    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 239    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 240    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 241    case PIPE_CAP_DRAW_PARAMETERS:
 242    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 243    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 244    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 245    case PIPE_CAP_GENERATE_MIPMAP:
 246    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 247    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 248    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 249    case PIPE_CAP_QUERY_MEMORY_INFO:
 250    case PIPE_CAP_PCI_GROUP:
 251    case PIPE_CAP_PCI_BUS:
 252    case PIPE_CAP_PCI_DEVICE:
 253    case PIPE_CAP_PCI_FUNCTION:
 254    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 255    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 256    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 257    case PIPE_CAP_TGSI_VOTE:
 258    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 259    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 260    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 261    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 262    case PIPE_CAP_NATIVE_FENCE_FD:
 263    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 264    case PIPE_CAP_TGSI_FS_FBFETCH:
 265    case PIPE_CAP_DOUBLES:
 266    case PIPE_CAP_INT64:
 267    case PIPE_CAP_INT64_DIVMOD:
 268    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 269    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 270    case PIPE_CAP_TGSI_BALLOT:
 271    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 272       return 0;
 273
 274    case PIPE_CAP_VENDOR_ID:
 275       return 0x10de;
 276    case PIPE_CAP_DEVICE_ID: {
 277       uint64_t device_id;
 278       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 279          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 280          return -1;
 281       }
 282       return device_id;
 283    }
 284    case PIPE_CAP_ACCELERATED:
 285       return 1;
 286    case PIPE_CAP_VIDEO_MEMORY:
 287       return dev->vram_size >> 20;
 288    case PIPE_CAP_UMA:
 289       return 0;
 290    }
 291
 292    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 293    return 0;
 294 }
 295
 296 static int
 297 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 298                              enum pipe_shader_type shader,
 299                              enum pipe_shader_cap param)
 300 {
 301    switch (shader) {
 302    case PIPE_SHADER_VERTEX:
 303    case PIPE_SHADER_GEOMETRY:
 304    case PIPE_SHADER_FRAGMENT:
 305       break;
 306    case PIPE_SHADER_COMPUTE:
 307    default:
 308       return 0;
 309    }
 310
 311    switch (param) {
 312    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 313    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 314    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 315    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 316       return 16384;
 317    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 318       return 4;
 319    case PIPE_SHADER_CAP_MAX_INPUTS:
 320       if (shader == PIPE_SHADER_VERTEX)
 321          return 32;
 322       return 15;
 323    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 324       return 16;
 325    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 326       return 65536;
 327    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 328       return NV50_MAX_PIPE_CONSTBUFS;
 329    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 330       return shader != PIPE_SHADER_FRAGMENT;
 331    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 332    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 333    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 334       return 1;
 335    case PIPE_SHADER_CAP_MAX_TEMPS:
 336       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 337    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 338       return 1;
 339    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 340       return 1;
 341    case PIPE_SHADER_CAP_SUBROUTINES:
 342       return 0; /* please inline, or provide function declarations */
 343    case PIPE_SHADER_CAP_INTEGERS:
 344       return 1;
 345    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 346       return 1;
 347    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 348       /* The chip could handle more sampler views than samplers */
 349    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 350       return MIN2(16, PIPE_MAX_SAMPLERS);
 351    case PIPE_SHADER_CAP_PREFERRED_IR:
 352       return PIPE_SHADER_IR_TGSI;
 353    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 354       return 32;
 355    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 356    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 357    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 358    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 359    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 360    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 361    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 362    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 363       return 0;
 364    default:
 365       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 366       return 0;
 367    }
 368 }
 369
 370 static float
 371 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 372 {
 373    switch (param) {
 374    case PIPE_CAPF_MAX_LINE_WIDTH:
 375    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 376       return 10.0f;
 377    case PIPE_CAPF_MAX_POINT_WIDTH:
 378    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 379       return 64.0f;
 380    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 381       return 16.0f;
 382    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 383       return 4.0f;
 384    case PIPE_CAPF_GUARD_BAND_LEFT:
 385    case PIPE_CAPF_GUARD_BAND_TOP:
 386       return 0.0f;
 387    case PIPE_CAPF_GUARD_BAND_RIGHT:
 388    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 389       return 0.0f; /* that or infinity */
 390    }
 391
 392    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 393    return 0.0f;
 394 }
 395
 396 static int
 397 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 398                               enum pipe_shader_ir ir_type,
 399                               enum pipe_compute_cap param, void *data)
 400 {
 401    struct nv50_screen *screen = nv50_screen(pscreen);
 402
 403 #define RET(x) do {                  \
 404    if (data)                         \
 405       memcpy(data, x, sizeof(x));    \
 406    return sizeof(x);                 \
 407 } while (0)
 408
 409    switch (param) {
 410    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 411       RET((uint64_t []) { 2 });
 412    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 413       RET(((uint64_t []) { 65535, 65535 }));
 414    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 415       RET(((uint64_t []) { 512, 512, 64 }));
 416    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 417       RET((uint64_t []) { 512 });
 418    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 419       RET((uint64_t []) { 1ULL << 32 });
 420    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 421       RET((uint64_t []) { 16 << 10 });
 422    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 423       RET((uint64_t []) { 16 << 10 });
 424    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 425       RET((uint64_t []) { 4096 });
 426    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 427       RET((uint32_t []) { 32 });
 428    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 429       RET((uint64_t []) { 1ULL << 40 });
 430    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 431       RET((uint32_t []) { 0 });
 432    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 433       RET((uint32_t []) { screen->mp_count });
 434    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 435       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 436    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 437       RET((uint32_t []) { 32 });
 438    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 439       RET((uint64_t []) { 0 });
 440    default:
 441       return 0;
 442    }
 443
 444 #undef RET
 445 }
 446
 447 static void
 448 nv50_screen_destroy(struct pipe_screen *pscreen)
 449 {
 450    struct nv50_screen *screen = nv50_screen(pscreen);
 451
 452    if (!nouveau_drm_screen_unref(&screen->base))
 453       return;
 454
 455    if (screen->base.fence.current) {
 456       struct nouveau_fence *current = NULL;
 457
 458       /* nouveau_fence_wait will create a new current fence, so wait on the
 459        * _current_ one, and remove both.
 460        */
 461       nouveau_fence_ref(screen->base.fence.current, &current);
 462       nouveau_fence_wait(current, NULL);
 463       nouveau_fence_ref(NULL, &current);
 464       nouveau_fence_ref(NULL, &screen->base.fence.current);
 465    }
 466    if (screen->base.pushbuf)
 467       screen->base.pushbuf->user_priv = NULL;
 468
 469    if (screen->blitter)
 470       nv50_blitter_destroy(screen);
 471    if (screen->pm.prog) {
 472       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 473       nv50_program_destroy(NULL, screen->pm.prog);
 474       FREE(screen->pm.prog);
 475    }
 476
 477    nouveau_bo_ref(NULL, &screen->code);
 478    nouveau_bo_ref(NULL, &screen->tls_bo);
 479    nouveau_bo_ref(NULL, &screen->stack_bo);
 480    nouveau_bo_ref(NULL, &screen->txc);
 481    nouveau_bo_ref(NULL, &screen->uniforms);
 482    nouveau_bo_ref(NULL, &screen->fence.bo);
 483
 484    nouveau_heap_destroy(&screen->vp_code_heap);
 485    nouveau_heap_destroy(&screen->gp_code_heap);
 486    nouveau_heap_destroy(&screen->fp_code_heap);
 487
 488    FREE(screen->tic.entries);
 489
 490    nouveau_object_del(&screen->tesla);
 491    nouveau_object_del(&screen->eng2d);
 492    nouveau_object_del(&screen->m2mf);
 493    nouveau_object_del(&screen->compute);
 494    nouveau_object_del(&screen->sync);
 495
 496    nouveau_screen_fini(&screen->base);
 497
 498    FREE(screen);
 499 }
 500
 501 static void
 502 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 503 {
 504    struct nv50_screen *screen = nv50_screen(pscreen);
 505    struct nouveau_pushbuf *push = screen->base.pushbuf;
 506
 507    /* we need to do it after possible flush in MARK_RING */
 508    *sequence = ++screen->base.fence.sequence;
 509
 510    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 511    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 512    PUSH_DATAh(push, screen->fence.bo->offset);
 513    PUSH_DATA (push, screen->fence.bo->offset);
 514    PUSH_DATA (push, *sequence);
 515    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 516                     NV50_3D_QUERY_GET_UNK4 |
 517                     NV50_3D_QUERY_GET_UNIT_CROP |
 518                     NV50_3D_QUERY_GET_TYPE_QUERY |
 519                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 520                     NV50_3D_QUERY_GET_SHORT);
 521 }
 522
 523 static u32
 524 nv50_screen_fence_update(struct pipe_screen *pscreen)
 525 {
 526    return nv50_screen(pscreen)->fence.map[0];
 527 }
 528
 529 static void
 530 nv50_screen_init_hwctx(struct nv50_screen *screen)
 531 {
 532    struct nouveau_pushbuf *push = screen->base.pushbuf;
 533    struct nv04_fifo *fifo;
 534    unsigned i;
 535
 536    fifo = (struct nv04_fifo *)screen->base.channel->data;
 537
 538    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 539    PUSH_DATA (push, screen->m2mf->handle);
 540    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 541    PUSH_DATA (push, screen->sync->handle);
 542    PUSH_DATA (push, fifo->vram);
 543    PUSH_DATA (push, fifo->vram);
 544
 545    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 546    PUSH_DATA (push, screen->eng2d->handle);
 547    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 548    PUSH_DATA (push, screen->sync->handle);
 549    PUSH_DATA (push, fifo->vram);
 550    PUSH_DATA (push, fifo->vram);
 551    PUSH_DATA (push, fifo->vram);
 552    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 553    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 554    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 555    PUSH_DATA (push, 0);
 556    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 557    PUSH_DATA (push, 0);
 558    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 559    PUSH_DATA (push, 1);
 560    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 561    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 562
 563    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 564    PUSH_DATA (push, screen->tesla->handle);
 565
 566    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 567    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 568
 569    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 570    PUSH_DATA (push, screen->sync->handle);
 571    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 572    for (i = 0; i < 11; ++i)
 573       PUSH_DATA(push, fifo->vram);
 574    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 575    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 576       PUSH_DATA(push, fifo->vram);
 577
 578    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 579    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 580    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 581    PUSH_DATA (push, 0xf);
 582
 583    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 584       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 585       PUSH_DATA (push, 0x18);
 586    }
 587
 588    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 589    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 590
 591    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 592    for (i = 0; i < 8; ++i)
 593       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 594
 595    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 596    PUSH_DATA (push, 1);
 597
 598    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 599    PUSH_DATA (push, 0);
 600    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 601    PUSH_DATA (push, 0);
 602    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 603    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 604    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 605    PUSH_DATA (push, 0);
 606    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 607    PUSH_DATA (push, 1);
 608    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 609    PUSH_DATA (push, 1);
 610
 611    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 612       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 613       PUSH_DATA (push, 0);
 614    }
 615
 616    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 617    PUSH_DATA (push, 0);
 618    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 619    PUSH_DATA (push, 0);
 620    PUSH_DATA (push, 0);
 621    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 622    PUSH_DATA (push, 0x3f);
 623
 624    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 625    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 626    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 627
 628    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 629    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 630    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 631
 632    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 633    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 634    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 635
 636    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 637    PUSH_DATAh(push, screen->tls_bo->offset);
 638    PUSH_DATA (push, screen->tls_bo->offset);
 639    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 640
 641    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 642    PUSH_DATAh(push, screen->stack_bo->offset);
 643    PUSH_DATA (push, screen->stack_bo->offset);
 644    PUSH_DATA (push, 4);
 645
 646    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 647    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 648    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 649    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 650
 651    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 652    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 653    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 654    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 655
 656    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 657    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 658    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 659    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 660
 661    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 662    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 663    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 664    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 665
 666    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 667    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 668    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 669    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 670
 671    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 672    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 673    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 674    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 675    PUSH_DATAf(push, 0.0f);
 676    PUSH_DATAf(push, 0.0f);
 677    PUSH_DATAf(push, 0.0f);
 678    PUSH_DATAf(push, 0.0f);
 679    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 680    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 681    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 682
 683    nv50_upload_ms_info(push);
 684
 685    /* max TIC (bits 4:8) & TSC bindings, per program type */
 686    for (i = 0; i < 3; ++i) {
 687       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 688       PUSH_DATA (push, 0x54);
 689    }
 690
 691    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 692    PUSH_DATAh(push, screen->txc->offset);
 693    PUSH_DATA (push, screen->txc->offset);
 694    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 695
 696    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 697    PUSH_DATAh(push, screen->txc->offset + 65536);
 698    PUSH_DATA (push, screen->txc->offset + 65536);
 699    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 700
 701    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 702    PUSH_DATA (push, 0);
 703
 704    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 705    PUSH_DATA (push, 0);
 706    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 707    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 708    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 709    for (i = 0; i < 8 * 2; ++i)
 710       PUSH_DATA(push, 0);
 711    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 712    PUSH_DATA (push, 0);
 713
 714    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 715    PUSH_DATA (push, 1);
 716    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 717       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 718       PUSH_DATAf(push, 0.0f);
 719       PUSH_DATAf(push, 1.0f);
 720       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 721       PUSH_DATA (push, 8192 << 16);
 722       PUSH_DATA (push, 8192 << 16);
 723    }
 724
 725    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 726 #ifdef NV50_SCISSORS_CLIPPING
 727    PUSH_DATA (push, 0x0000);
 728 #else
 729    PUSH_DATA (push, 0x1080);
 730 #endif
 731
 732    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 733    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 734
 735    /* We use scissors instead of exact view volume clipping,
 736     * so they're always enabled.
 737     */
 738    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 739       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 740       PUSH_DATA (push, 1);
 741       PUSH_DATA (push, 8192 << 16);
 742       PUSH_DATA (push, 8192 << 16);
 743    }
 744
 745    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 746    PUSH_DATA (push, 1);
 747    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 748    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 749    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 750    PUSH_DATA (push, 0x11111111);
 751    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 752    PUSH_DATA (push, 1);
 753
 754    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 755    PUSH_DATA (push, 0);
 756    if (screen->base.class_3d >= NV84_3D_CLASS) {
 757       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 758       PUSH_DATA (push, 0);
 759    }
 760
 761    PUSH_KICK (push);
 762 }
 763
 764 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 765       uint64_t *tls_size)
 766 {
 767    struct nouveau_device *dev = screen->base.device;
 768    int ret;
 769
 770    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 771          ONE_TEMP_SIZE;
 772    if (nouveau_mesa_debug)
 773       debug_printf("allocating space for %u temps\n",
 774             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 775    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 776          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 777
 778    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 779                         *tls_size, NULL, &screen->tls_bo);
 780    if (ret) {
 781       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 782       return ret;
 783    }
 784
 785    return 0;
 786 }
 787
 788 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 789 {
 790    struct nouveau_pushbuf *push = screen->base.pushbuf;
 791    int ret;
 792    uint64_t tls_size;
 793
 794    if (tls_space < screen->cur_tls_space)
 795       return 0;
 796    if (tls_space > screen->max_tls_space) {
 797       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 798        * LOCAL_WARPS_NO_CLAMP) */
 799       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 800             (unsigned)(tls_space / ONE_TEMP_SIZE),
 801             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 802       return -ENOMEM;
 803    }
 804
 805    nouveau_bo_ref(NULL, &screen->tls_bo);
 806    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 807    if (ret)
 808       return ret;
 809
 810    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 811    PUSH_DATAh(push, screen->tls_bo->offset);
 812    PUSH_DATA (push, screen->tls_bo->offset);
 813    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 814
 815    return 1;
 816 }
 817
 818 struct nouveau_screen *
 819 nv50_screen_create(struct nouveau_device *dev)
 820 {
 821    struct nv50_screen *screen;
 822    struct pipe_screen *pscreen;
 823    struct nouveau_object *chan;
 824    uint64_t value;
 825    uint32_t tesla_class;
 826    unsigned stack_size;
 827    int ret;
 828
 829    screen = CALLOC_STRUCT(nv50_screen);
 830    if (!screen)
 831       return NULL;
 832    pscreen = &screen->base.base;
 833    pscreen->destroy = nv50_screen_destroy;
 834
 835    ret = nouveau_screen_init(&screen->base, dev);
 836    if (ret) {
 837       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 838       goto fail;
 839    }
 840
 841    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 842     *  admit them to VRAM.
 843     */
 844    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 845       PIPE_BIND_VERTEX_BUFFER;
 846    screen->base.sysmem_bindings |=
 847       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 848
 849    screen->base.pushbuf->user_priv = screen;
 850    screen->base.pushbuf->rsvd_kick = 5;
 851
 852    chan = screen->base.channel;
 853
 854    pscreen->context_create = nv50_create;
 855    pscreen->is_format_supported = nv50_screen_is_format_supported;
 856    pscreen->get_param = nv50_screen_get_param;
 857    pscreen->get_shader_param = nv50_screen_get_shader_param;
 858    pscreen->get_paramf = nv50_screen_get_paramf;
 859    pscreen->get_compute_param = nv50_screen_get_compute_param;
 860    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 861    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 862
 863    nv50_screen_init_resource_functions(pscreen);
 864
 865    if (screen->base.device->chipset < 0x84 ||
 866        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 867       /* PMPEG */
 868       nouveau_screen_init_vdec(&screen->base);
 869    } else if (screen->base.device->chipset < 0x98 ||
 870               screen->base.device->chipset == 0xa0) {
 871       /* VP2 */
 872       screen->base.base.get_video_param = nv84_screen_get_video_param;
 873       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 874    } else {
 875       /* VP3/4 */
 876       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 877       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 878    }
 879
 880    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 881                         NULL, &screen->fence.bo);
 882    if (ret) {
 883       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 884       goto fail;
 885    }
 886
 887    nouveau_bo_map(screen->fence.bo, 0, NULL);
 888    screen->fence.map = screen->fence.bo->map;
 889    screen->base.fence.emit = nv50_screen_fence_emit;
 890    screen->base.fence.update = nv50_screen_fence_update;
 891
 892    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 893                             &(struct nv04_notify){ .length = 32 },
 894                             sizeof(struct nv04_notify), &screen->sync);
 895    if (ret) {
 896       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 897       goto fail;
 898    }
 899
 900    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 901                             NULL, 0, &screen->m2mf);
 902    if (ret) {
 903       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 904       goto fail;
 905    }
 906
 907    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 908                             NULL, 0, &screen->eng2d);
 909    if (ret) {
 910       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 911       goto fail;
 912    }
 913
 914    switch (dev->chipset & 0xf0) {
 915    case 0x50:
 916       tesla_class = NV50_3D_CLASS;
 917       break;
 918    case 0x80:
 919    case 0x90:
 920       tesla_class = NV84_3D_CLASS;
 921       break;
 922    case 0xa0:
 923       switch (dev->chipset) {
 924       case 0xa0:
 925       case 0xaa:
 926       case 0xac:
 927          tesla_class = NVA0_3D_CLASS;
 928          break;
 929       case 0xaf:
 930          tesla_class = NVAF_3D_CLASS;
 931          break;
 932       default:
 933          tesla_class = NVA3_3D_CLASS;
 934          break;
 935       }
 936       break;
 937    default:
 938       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 939       goto fail;
 940    }
 941    screen->base.class_3d = tesla_class;
 942
 943    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 944                             NULL, 0, &screen->tesla);
 945    if (ret) {
 946       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 947       goto fail;
 948    }
 949
 950    /* This over-allocates by a page. The GP, which would execute at the end of
 951     * the last page, would trigger faults. The going theory is that it
 952     * prefetches up to a certain amount.
 953     */
 954    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 955                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 956                         NULL, &screen->code);
 957    if (ret) {
 958       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 959       goto fail;
 960    }
 961
 962    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 963    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 964    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 965
 966    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 967
 968    screen->TPs = util_bitcount(value & 0xffff);
 969    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 970
 971    screen->mp_count = screen->TPs * screen->MPsInTP;
 972
 973    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 974          STACK_WARPS_ALLOC * 64 * 8;
 975
 976    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 977                         &screen->stack_bo);
 978    if (ret) {
 979       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 980       goto fail;
 981    }
 982
 983    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 984          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 985          ONE_TEMP_SIZE;
 986    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 987    screen->max_tls_space /= 2; /* half of vram */
 988
 989    /* hw can address max 64 KiB */
 990    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 991
 992    uint64_t tls_size;
 993    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 994    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 995    if (ret)
 996       goto fail;
 997
 998    if (nouveau_mesa_debug)
 999       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1000             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1001
1002    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1003                         &screen->uniforms);
1004    if (ret) {
1005       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1006       goto fail;
1007    }
1008
1009    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1010                         &screen->txc);
1011    if (ret) {
1012       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1013       goto fail;
1014    }
1015
1016    screen->tic.entries = CALLOC(4096, sizeof(void *));
1017    screen->tsc.entries = screen->tic.entries + 2048;
1018
1019    if (!nv50_blitter_create(screen))
1020       goto fail;
1021
1022    nv50_screen_init_hwctx(screen);
1023
1024    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1025    if (ret) {
1026       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1027       goto fail;
1028    }
1029
1030    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1031
1032    return &screen->base;
1033
1034 fail:
1035    screen->base.base.context_create = NULL;
1036    return &screen->base;
1037 }
1038
1039 int
1040 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1041 {
1042    int i = screen->tic.next;
1043
1044    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1045       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1046
1047    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1048
1049    if (screen->tic.entries[i])
1050       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1051
1052    screen->tic.entries[i] = entry;
1053    return i;
1054 }
1055
1056 int
1057 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1058 {
1059    int i = screen->tsc.next;
1060
1061    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1062       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1063
1064    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1065
1066    if (screen->tsc.entries[i])
1067       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1068
1069    screen->tsc.entries[i] = entry;
1070    return i;
1071 }