src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* transfers & shared are always supported */
  79    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  80                  PIPE_BIND_TRANSFER_WRITE |
  81                  PIPE_BIND_LINEAR |
  82                  PIPE_BIND_SHARED);
  83
  84    return (( nv50_format_table[format].usage |
  85             nv50_vertex_format[format].usage) & bindings) == bindings;
  86 }
  87
  88 static int
  89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  90 {
  91    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  92    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  93
  94    switch (param) {
  95    /* non-boolean caps */
  96    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  97       return 14;
  98    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  99       return 12;
 100    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 101       return 14;
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103       return 512;
 104    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 105    case PIPE_CAP_MIN_TEXEL_OFFSET:
 106       return -8;
 107    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109       return 7;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 128 * 1024 * 1024;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 113       return 330;
 114    case PIPE_CAP_MAX_RENDER_TARGETS:
 115       return 8;
 116    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 117       return 1;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 119       return 4;
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122       return 64;
 123    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 124    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 125       return 1024;
 126    case PIPE_CAP_MAX_VERTEX_STREAMS:
 127       return 1;
 128    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 129       return 2048;
 130    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 131       return 256;
 132    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 133       return 16; /* 256 for binding as RT, but that's not possible in GL */
 134    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 135       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 136    case PIPE_CAP_MAX_VIEWPORTS:
 137       return NV50_MAX_VIEWPORTS;
 138    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 139       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 140    case PIPE_CAP_ENDIANNESS:
 141       return PIPE_ENDIAN_LITTLE;
 142    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 143       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 144
 145    /* supported caps */
 146    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 147    case PIPE_CAP_TEXTURE_SWIZZLE:
 148    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 149    case PIPE_CAP_NPOT_TEXTURES:
 150    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151    case PIPE_CAP_ANISOTROPIC_FILTER:
 152    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 153    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 154    case PIPE_CAP_TWO_SIDED_STENCIL:
 155    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 156    case PIPE_CAP_POINT_SPRITE:
 157    case PIPE_CAP_SM3:
 158    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 159    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 160    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 161    case PIPE_CAP_QUERY_TIMESTAMP:
 162    case PIPE_CAP_QUERY_TIME_ELAPSED:
 163    case PIPE_CAP_OCCLUSION_QUERY:
 164    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 165    case PIPE_CAP_INDEP_BLEND_ENABLE:
 166    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 167    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 168    case PIPE_CAP_PRIMITIVE_RESTART:
 169    case PIPE_CAP_TGSI_INSTANCEID:
 170    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 171    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 172    case PIPE_CAP_CONDITIONAL_RENDER:
 173    case PIPE_CAP_TEXTURE_BARRIER:
 174    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 175    case PIPE_CAP_START_INSTANCE:
 176    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 177    case PIPE_CAP_USER_INDEX_BUFFERS:
 178    case PIPE_CAP_USER_VERTEX_BUFFERS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 181    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 182    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 183    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 184    case PIPE_CAP_CLIP_HALFZ:
 185    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 186    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 187    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 188    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 189    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 190    case PIPE_CAP_TGSI_TXQS:
 191    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 192    case PIPE_CAP_SHAREABLE_SHADERS:
 193    case PIPE_CAP_CLEAR_TEXTURE:
 194    case PIPE_CAP_COMPUTE:
 195    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 196    case PIPE_CAP_INVALIDATE_BUFFER:
 197    case PIPE_CAP_STRING_MARKER:
 198       return 1;
 199    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 200       return 1; /* class_3d >= NVA0_3D_CLASS; */
 201    /* supported on nva0+ */
 202    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 203       return class_3d >= NVA0_3D_CLASS;
 204    /* supported on nva3+ */
 205    case PIPE_CAP_CUBE_MAP_ARRAY:
 206    case PIPE_CAP_INDEP_BLEND_FUNC:
 207    case PIPE_CAP_TEXTURE_QUERY_LOD:
 208    case PIPE_CAP_SAMPLE_SHADING:
 209    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 210       return class_3d >= NVA3_3D_CLASS;
 211
 212    /* unsupported caps */
 213    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 214    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 215    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 216    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 217    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 218    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 219    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 220    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 221    case PIPE_CAP_TGSI_TEXCOORD:
 222    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 223    case PIPE_CAP_TEXTURE_GATHER_SM5:
 224    case PIPE_CAP_FAKE_SW_MSAA:
 225    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 226    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 227    case PIPE_CAP_DRAW_INDIRECT:
 228    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 229    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 230    case PIPE_CAP_VERTEXID_NOBASE:
 231    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 232    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 233    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 234    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 235    case PIPE_CAP_DRAW_PARAMETERS:
 236    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 237    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 238    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 239    case PIPE_CAP_GENERATE_MIPMAP:
 240    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 241    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 242    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 243    case PIPE_CAP_QUERY_MEMORY_INFO:
 244    case PIPE_CAP_PCI_GROUP:
 245    case PIPE_CAP_PCI_BUS:
 246    case PIPE_CAP_PCI_DEVICE:
 247    case PIPE_CAP_PCI_FUNCTION:
 248    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 249    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 250       return 0;
 251
 252    case PIPE_CAP_VENDOR_ID:
 253       return 0x10de;
 254    case PIPE_CAP_DEVICE_ID: {
 255       uint64_t device_id;
 256       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 257          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 258          return -1;
 259       }
 260       return device_id;
 261    }
 262    case PIPE_CAP_ACCELERATED:
 263       return 1;
 264    case PIPE_CAP_VIDEO_MEMORY:
 265       return dev->vram_size >> 20;
 266    case PIPE_CAP_UMA:
 267       return 0;
 268    }
 269
 270    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 271    return 0;
 272 }
 273
 274 static int
 275 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 276                              enum pipe_shader_cap param)
 277 {
 278    switch (shader) {
 279    case PIPE_SHADER_VERTEX:
 280    case PIPE_SHADER_GEOMETRY:
 281    case PIPE_SHADER_FRAGMENT:
 282       break;
 283    case PIPE_SHADER_COMPUTE:
 284    default:
 285       return 0;
 286    }
 287
 288    switch (param) {
 289    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 290    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 291    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 292    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 293       return 16384;
 294    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 295       return 4;
 296    case PIPE_SHADER_CAP_MAX_INPUTS:
 297       if (shader == PIPE_SHADER_VERTEX)
 298          return 32;
 299       return 15;
 300    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 301       return 16;
 302    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 303       return 65536;
 304    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 305       return NV50_MAX_PIPE_CONSTBUFS;
 306    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 307    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 308       return shader != PIPE_SHADER_FRAGMENT;
 309    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 310    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 311       return 1;
 312    case PIPE_SHADER_CAP_MAX_PREDS:
 313       return 0;
 314    case PIPE_SHADER_CAP_MAX_TEMPS:
 315       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 316    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 317       return 1;
 318    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 319       return 1;
 320    case PIPE_SHADER_CAP_SUBROUTINES:
 321       return 0; /* please inline, or provide function declarations */
 322    case PIPE_SHADER_CAP_INTEGERS:
 323       return 1;
 324    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 325       /* The chip could handle more sampler views than samplers */
 326    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 327       return MIN2(16, PIPE_MAX_SAMPLERS);
 328    case PIPE_SHADER_CAP_DOUBLES:
 329    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 330    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 331    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 332    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 333    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 334    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 335    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 336       return 0;
 337    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 338       return 32;
 339    default:
 340       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 341       return 0;
 342    }
 343 }
 344
 345 static float
 346 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 347 {
 348    switch (param) {
 349    case PIPE_CAPF_MAX_LINE_WIDTH:
 350    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 351       return 10.0f;
 352    case PIPE_CAPF_MAX_POINT_WIDTH:
 353    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 354       return 64.0f;
 355    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 356       return 16.0f;
 357    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 358       return 4.0f;
 359    case PIPE_CAPF_GUARD_BAND_LEFT:
 360    case PIPE_CAPF_GUARD_BAND_TOP:
 361       return 0.0f;
 362    case PIPE_CAPF_GUARD_BAND_RIGHT:
 363    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 364       return 0.0f; /* that or infinity */
 365    }
 366
 367    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 368    return 0.0f;
 369 }
 370
 371 static int
 372 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 373                               enum pipe_shader_ir ir_type,
 374                               enum pipe_compute_cap param, void *data)
 375 {
 376    struct nv50_screen *screen = nv50_screen(pscreen);
 377
 378 #define RET(x) do {                  \
 379    if (data)                         \
 380       memcpy(data, x, sizeof(x));    \
 381    return sizeof(x);                 \
 382 } while (0)
 383
 384    switch (param) {
 385    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 386       RET((uint64_t []) { 2 });
 387    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 388       RET(((uint64_t []) { 65535, 65535 }));
 389    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 390       RET(((uint64_t []) { 512, 512, 64 }));
 391    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 392       RET((uint64_t []) { 512 });
 393    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 394       RET((uint64_t []) { 1ULL << 32 });
 395    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 396       RET((uint64_t []) { 16 << 10 });
 397    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 398       RET((uint64_t []) { 16 << 10 });
 399    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 400       RET((uint64_t []) { 4096 });
 401    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 402       RET((uint32_t []) { 32 });
 403    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 404       RET((uint64_t []) { 1ULL << 40 });
 405    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 406       RET((uint32_t []) { 0 });
 407    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 408       RET((uint32_t []) { screen->mp_count });
 409    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 410       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 411    default:
 412       return 0;
 413    }
 414
 415 #undef RET
 416 }
 417
 418 static void
 419 nv50_screen_destroy(struct pipe_screen *pscreen)
 420 {
 421    struct nv50_screen *screen = nv50_screen(pscreen);
 422
 423    if (!nouveau_drm_screen_unref(&screen->base))
 424       return;
 425
 426    if (screen->base.fence.current) {
 427       struct nouveau_fence *current = NULL;
 428
 429       /* nouveau_fence_wait will create a new current fence, so wait on the
 430        * _current_ one, and remove both.
 431        */
 432       nouveau_fence_ref(screen->base.fence.current, &current);
 433       nouveau_fence_wait(current, NULL);
 434       nouveau_fence_ref(NULL, &current);
 435       nouveau_fence_ref(NULL, &screen->base.fence.current);
 436    }
 437    if (screen->base.pushbuf)
 438       screen->base.pushbuf->user_priv = NULL;
 439
 440    if (screen->blitter)
 441       nv50_blitter_destroy(screen);
 442    if (screen->pm.prog) {
 443       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 444       nv50_program_destroy(NULL, screen->pm.prog);
 445       FREE(screen->pm.prog);
 446    }
 447
 448    nouveau_bo_ref(NULL, &screen->code);
 449    nouveau_bo_ref(NULL, &screen->tls_bo);
 450    nouveau_bo_ref(NULL, &screen->stack_bo);
 451    nouveau_bo_ref(NULL, &screen->txc);
 452    nouveau_bo_ref(NULL, &screen->uniforms);
 453    nouveau_bo_ref(NULL, &screen->fence.bo);
 454
 455    nouveau_heap_destroy(&screen->vp_code_heap);
 456    nouveau_heap_destroy(&screen->gp_code_heap);
 457    nouveau_heap_destroy(&screen->fp_code_heap);
 458
 459    FREE(screen->tic.entries);
 460
 461    nouveau_object_del(&screen->tesla);
 462    nouveau_object_del(&screen->eng2d);
 463    nouveau_object_del(&screen->m2mf);
 464    nouveau_object_del(&screen->compute);
 465    nouveau_object_del(&screen->sync);
 466
 467    nouveau_screen_fini(&screen->base);
 468
 469    FREE(screen);
 470 }
 471
 472 static void
 473 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 474 {
 475    struct nv50_screen *screen = nv50_screen(pscreen);
 476    struct nouveau_pushbuf *push = screen->base.pushbuf;
 477
 478    /* we need to do it after possible flush in MARK_RING */
 479    *sequence = ++screen->base.fence.sequence;
 480
 481    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 482    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 483    PUSH_DATAh(push, screen->fence.bo->offset);
 484    PUSH_DATA (push, screen->fence.bo->offset);
 485    PUSH_DATA (push, *sequence);
 486    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 487                     NV50_3D_QUERY_GET_UNK4 |
 488                     NV50_3D_QUERY_GET_UNIT_CROP |
 489                     NV50_3D_QUERY_GET_TYPE_QUERY |
 490                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 491                     NV50_3D_QUERY_GET_SHORT);
 492 }
 493
 494 static u32
 495 nv50_screen_fence_update(struct pipe_screen *pscreen)
 496 {
 497    return nv50_screen(pscreen)->fence.map[0];
 498 }
 499
 500 static void
 501 nv50_screen_init_hwctx(struct nv50_screen *screen)
 502 {
 503    struct nouveau_pushbuf *push = screen->base.pushbuf;
 504    struct nv04_fifo *fifo;
 505    unsigned i;
 506
 507    fifo = (struct nv04_fifo *)screen->base.channel->data;
 508
 509    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 510    PUSH_DATA (push, screen->m2mf->handle);
 511    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 512    PUSH_DATA (push, screen->sync->handle);
 513    PUSH_DATA (push, fifo->vram);
 514    PUSH_DATA (push, fifo->vram);
 515
 516    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 517    PUSH_DATA (push, screen->eng2d->handle);
 518    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 519    PUSH_DATA (push, screen->sync->handle);
 520    PUSH_DATA (push, fifo->vram);
 521    PUSH_DATA (push, fifo->vram);
 522    PUSH_DATA (push, fifo->vram);
 523    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 524    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 525    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 526    PUSH_DATA (push, 0);
 527    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 528    PUSH_DATA (push, 0);
 529    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 530    PUSH_DATA (push, 1);
 531    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 532    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 533
 534    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 535    PUSH_DATA (push, screen->tesla->handle);
 536
 537    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 538    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 539
 540    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 541    PUSH_DATA (push, screen->sync->handle);
 542    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 543    for (i = 0; i < 11; ++i)
 544       PUSH_DATA(push, fifo->vram);
 545    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 546    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 547       PUSH_DATA(push, fifo->vram);
 548
 549    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 550    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 551    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 552    PUSH_DATA (push, 0xf);
 553
 554    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 555       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 556       PUSH_DATA (push, 0x18);
 557    }
 558
 559    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 560    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 561
 562    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 563    for (i = 0; i < 8; ++i)
 564       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 565
 566    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 567    PUSH_DATA (push, 1);
 568
 569    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 570    PUSH_DATA (push, 0);
 571    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 572    PUSH_DATA (push, 0);
 573    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 574    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 575    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 576    PUSH_DATA (push, 0);
 577    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 578    PUSH_DATA (push, 1);
 579    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 580    PUSH_DATA (push, 1);
 581
 582    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 583       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 584       PUSH_DATA (push, 0);
 585    }
 586
 587    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 588    PUSH_DATA (push, 0);
 589    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 590    PUSH_DATA (push, 0);
 591    PUSH_DATA (push, 0);
 592    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 593    PUSH_DATA (push, 0x3f);
 594
 595    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 596    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 597    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 598
 599    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 600    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 601    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 602
 603    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 604    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 605    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 606
 607    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 608    PUSH_DATAh(push, screen->tls_bo->offset);
 609    PUSH_DATA (push, screen->tls_bo->offset);
 610    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 611
 612    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 613    PUSH_DATAh(push, screen->stack_bo->offset);
 614    PUSH_DATA (push, screen->stack_bo->offset);
 615    PUSH_DATA (push, 4);
 616
 617    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 618    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 619    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 620    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 621
 622    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 623    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 624    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 625    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 626
 627    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 628    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 629    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 630    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 631
 632    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 633    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 634    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 635    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 636
 637    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 638    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 639    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 640    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 641
 642    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 643    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 644    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 645    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 646    PUSH_DATAf(push, 0.0f);
 647    PUSH_DATAf(push, 0.0f);
 648    PUSH_DATAf(push, 0.0f);
 649    PUSH_DATAf(push, 0.0f);
 650    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 651    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 652    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 653
 654    nv50_upload_ms_info(push);
 655
 656    /* max TIC (bits 4:8) & TSC bindings, per program type */
 657    for (i = 0; i < 3; ++i) {
 658       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 659       PUSH_DATA (push, 0x54);
 660    }
 661
 662    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 663    PUSH_DATAh(push, screen->txc->offset);
 664    PUSH_DATA (push, screen->txc->offset);
 665    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 666
 667    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 668    PUSH_DATAh(push, screen->txc->offset + 65536);
 669    PUSH_DATA (push, screen->txc->offset + 65536);
 670    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 671
 672    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 673    PUSH_DATA (push, 0);
 674
 675    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 676    PUSH_DATA (push, 0);
 677    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 678    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 679    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 680    for (i = 0; i < 8 * 2; ++i)
 681       PUSH_DATA(push, 0);
 682    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 683    PUSH_DATA (push, 0);
 684
 685    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 686    PUSH_DATA (push, 1);
 687    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 688       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 689       PUSH_DATAf(push, 0.0f);
 690       PUSH_DATAf(push, 1.0f);
 691       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 692       PUSH_DATA (push, 8192 << 16);
 693       PUSH_DATA (push, 8192 << 16);
 694    }
 695
 696    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 697 #ifdef NV50_SCISSORS_CLIPPING
 698    PUSH_DATA (push, 0x0000);
 699 #else
 700    PUSH_DATA (push, 0x1080);
 701 #endif
 702
 703    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 704    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 705
 706    /* We use scissors instead of exact view volume clipping,
 707     * so they're always enabled.
 708     */
 709    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 710       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 711       PUSH_DATA (push, 1);
 712       PUSH_DATA (push, 8192 << 16);
 713       PUSH_DATA (push, 8192 << 16);
 714    }
 715
 716    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 717    PUSH_DATA (push, 1);
 718    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 719    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 720    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 721    PUSH_DATA (push, 0x11111111);
 722    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 723    PUSH_DATA (push, 1);
 724
 725    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 726    PUSH_DATA (push, 0);
 727    if (screen->base.class_3d >= NV84_3D_CLASS) {
 728       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 729       PUSH_DATA (push, 0);
 730    }
 731
 732    PUSH_KICK (push);
 733 }
 734
 735 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 736       uint64_t *tls_size)
 737 {
 738    struct nouveau_device *dev = screen->base.device;
 739    int ret;
 740
 741    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 742          ONE_TEMP_SIZE;
 743    if (nouveau_mesa_debug)
 744       debug_printf("allocating space for %u temps\n",
 745             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 746    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 747          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 748
 749    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 750                         *tls_size, NULL, &screen->tls_bo);
 751    if (ret) {
 752       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 753       return ret;
 754    }
 755
 756    return 0;
 757 }
 758
 759 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 760 {
 761    struct nouveau_pushbuf *push = screen->base.pushbuf;
 762    int ret;
 763    uint64_t tls_size;
 764
 765    if (tls_space < screen->cur_tls_space)
 766       return 0;
 767    if (tls_space > screen->max_tls_space) {
 768       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 769        * LOCAL_WARPS_NO_CLAMP) */
 770       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 771             (unsigned)(tls_space / ONE_TEMP_SIZE),
 772             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 773       return -ENOMEM;
 774    }
 775
 776    nouveau_bo_ref(NULL, &screen->tls_bo);
 777    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 778    if (ret)
 779       return ret;
 780
 781    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 782    PUSH_DATAh(push, screen->tls_bo->offset);
 783    PUSH_DATA (push, screen->tls_bo->offset);
 784    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 785
 786    return 1;
 787 }
 788
 789 struct nouveau_screen *
 790 nv50_screen_create(struct nouveau_device *dev)
 791 {
 792    struct nv50_screen *screen;
 793    struct pipe_screen *pscreen;
 794    struct nouveau_object *chan;
 795    uint64_t value;
 796    uint32_t tesla_class;
 797    unsigned stack_size;
 798    int ret;
 799
 800    screen = CALLOC_STRUCT(nv50_screen);
 801    if (!screen)
 802       return NULL;
 803    pscreen = &screen->base.base;
 804    pscreen->destroy = nv50_screen_destroy;
 805
 806    ret = nouveau_screen_init(&screen->base, dev);
 807    if (ret) {
 808       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 809       goto fail;
 810    }
 811
 812    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 813     *  admit them to VRAM.
 814     */
 815    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 816       PIPE_BIND_VERTEX_BUFFER;
 817    screen->base.sysmem_bindings |=
 818       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 819
 820    screen->base.pushbuf->user_priv = screen;
 821    screen->base.pushbuf->rsvd_kick = 5;
 822
 823    chan = screen->base.channel;
 824
 825    pscreen->context_create = nv50_create;
 826    pscreen->is_format_supported = nv50_screen_is_format_supported;
 827    pscreen->get_param = nv50_screen_get_param;
 828    pscreen->get_shader_param = nv50_screen_get_shader_param;
 829    pscreen->get_paramf = nv50_screen_get_paramf;
 830    pscreen->get_compute_param = nv50_screen_get_compute_param;
 831    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 832    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 833
 834    nv50_screen_init_resource_functions(pscreen);
 835
 836    if (screen->base.device->chipset < 0x84 ||
 837        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 838       /* PMPEG */
 839       nouveau_screen_init_vdec(&screen->base);
 840    } else if (screen->base.device->chipset < 0x98 ||
 841               screen->base.device->chipset == 0xa0) {
 842       /* VP2 */
 843       screen->base.base.get_video_param = nv84_screen_get_video_param;
 844       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 845    } else {
 846       /* VP3/4 */
 847       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 848       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 849    }
 850
 851    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 852                         NULL, &screen->fence.bo);
 853    if (ret) {
 854       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 855       goto fail;
 856    }
 857
 858    nouveau_bo_map(screen->fence.bo, 0, NULL);
 859    screen->fence.map = screen->fence.bo->map;
 860    screen->base.fence.emit = nv50_screen_fence_emit;
 861    screen->base.fence.update = nv50_screen_fence_update;
 862
 863    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 864                             &(struct nv04_notify){ .length = 32 },
 865                             sizeof(struct nv04_notify), &screen->sync);
 866    if (ret) {
 867       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 868       goto fail;
 869    }
 870
 871    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 872                             NULL, 0, &screen->m2mf);
 873    if (ret) {
 874       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 875       goto fail;
 876    }
 877
 878    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 879                             NULL, 0, &screen->eng2d);
 880    if (ret) {
 881       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 882       goto fail;
 883    }
 884
 885    switch (dev->chipset & 0xf0) {
 886    case 0x50:
 887       tesla_class = NV50_3D_CLASS;
 888       break;
 889    case 0x80:
 890    case 0x90:
 891       tesla_class = NV84_3D_CLASS;
 892       break;
 893    case 0xa0:
 894       switch (dev->chipset) {
 895       case 0xa0:
 896       case 0xaa:
 897       case 0xac:
 898          tesla_class = NVA0_3D_CLASS;
 899          break;
 900       case 0xaf:
 901          tesla_class = NVAF_3D_CLASS;
 902          break;
 903       default:
 904          tesla_class = NVA3_3D_CLASS;
 905          break;
 906       }
 907       break;
 908    default:
 909       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 910       goto fail;
 911    }
 912    screen->base.class_3d = tesla_class;
 913
 914    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 915                             NULL, 0, &screen->tesla);
 916    if (ret) {
 917       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 918       goto fail;
 919    }
 920
 921    /* This over-allocates by a page. The GP, which would execute at the end of
 922     * the last page, would trigger faults. The going theory is that it
 923     * prefetches up to a certain amount.
 924     */
 925    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 926                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 927                         NULL, &screen->code);
 928    if (ret) {
 929       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 930       goto fail;
 931    }
 932
 933    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 934    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 935    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 936
 937    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 938
 939    screen->TPs = util_bitcount(value & 0xffff);
 940    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 941
 942    screen->mp_count = screen->TPs * screen->MPsInTP;
 943
 944    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 945          STACK_WARPS_ALLOC * 64 * 8;
 946
 947    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 948                         &screen->stack_bo);
 949    if (ret) {
 950       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 951       goto fail;
 952    }
 953
 954    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 955          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 956          ONE_TEMP_SIZE;
 957    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 958    screen->max_tls_space /= 2; /* half of vram */
 959
 960    /* hw can address max 64 KiB */
 961    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 962
 963    uint64_t tls_size;
 964    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 965    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 966    if (ret)
 967       goto fail;
 968
 969    if (nouveau_mesa_debug)
 970       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 971             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 972
 973    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 974                         &screen->uniforms);
 975    if (ret) {
 976       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 977       goto fail;
 978    }
 979
 980    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 981                         &screen->txc);
 982    if (ret) {
 983       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 984       goto fail;
 985    }
 986
 987    screen->tic.entries = CALLOC(4096, sizeof(void *));
 988    screen->tsc.entries = screen->tic.entries + 2048;
 989
 990    if (!nv50_blitter_create(screen))
 991       goto fail;
 992
 993    nv50_screen_init_hwctx(screen);
 994
 995    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
 996    if (ret) {
 997       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
 998       goto fail;
 999    }
1000
1001    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1002
1003    return &screen->base;
1004
1005 fail:
1006    screen->base.base.context_create = NULL;
1007    return &screen->base;
1008 }
1009
1010 int
1011 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1012 {
1013    int i = screen->tic.next;
1014
1015    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1016       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1017
1018    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1019
1020    if (screen->tic.entries[i])
1021       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1022
1023    screen->tic.entries[i] = entry;
1024    return i;
1025 }
1026
1027 int
1028 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1029 {
1030    int i = screen->tsc.next;
1031
1032    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1033       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1034
1035    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1036
1037    if (screen->tsc.entries[i])
1038       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1039
1040    screen->tsc.entries[i] = entry;
1041    return i;
1042 }