src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  45
  46 static boolean
  47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  48                                 enum pipe_format format,
  49                                 enum pipe_texture_target target,
  50                                 unsigned sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (sample_count > 8)
  54       return false;
  55    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  56       return false;
  57    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  58       return false;
  59
  60    if (!util_format_is_supported(format, bindings))
  61       return false;
  62
  63    switch (format) {
  64    case PIPE_FORMAT_Z16_UNORM:
  65       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  66          return false;
  67       break;
  68    default:
  69       break;
  70    }
  71
  72    /* transfers & shared are always supported */
  73    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  74                  PIPE_BIND_TRANSFER_WRITE |
  75                  PIPE_BIND_SHARED);
  76
  77    return (nv50_format_table[format].usage & bindings) == bindings;
  78 }
  79
  80 static int
  81 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  82 {
  83    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  84    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  85
  86    switch (param) {
  87    /* non-boolean caps */
  88    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  89       return 14;
  90    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  91       return 12;
  92    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  93       return 14;
  94    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  95       return 512;
  96    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  97    case PIPE_CAP_MIN_TEXEL_OFFSET:
  98       return -8;
  99    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 100    case PIPE_CAP_MAX_TEXEL_OFFSET:
 101       return 7;
 102    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 103       return 128 * 1024 * 1024;
 104    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 105       return 330;
 106    case PIPE_CAP_MAX_RENDER_TARGETS:
 107       return 8;
 108    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 109       return 1;
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 111       return 4;
 112    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 113    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 114       return 64;
 115    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 116    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 117       return 1024;
 118    case PIPE_CAP_MAX_VERTEX_STREAMS:
 119       return 1;
 120    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 121       return 2048;
 122    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 123       return 256;
 124    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 125       return 1; /* 256 for binding as RT, but that's not possible in GL */
 126    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 127       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 128    case PIPE_CAP_MAX_VIEWPORTS:
 129       return NV50_MAX_VIEWPORTS;
 130    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 131       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 132    case PIPE_CAP_ENDIANNESS:
 133       return PIPE_ENDIAN_LITTLE;
 134    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 135       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 136
 137    /* supported caps */
 138    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 139    case PIPE_CAP_TEXTURE_SWIZZLE:
 140    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 141    case PIPE_CAP_NPOT_TEXTURES:
 142    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 143    case PIPE_CAP_ANISOTROPIC_FILTER:
 144    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 145    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 146    case PIPE_CAP_TWO_SIDED_STENCIL:
 147    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 148    case PIPE_CAP_POINT_SPRITE:
 149    case PIPE_CAP_SM3:
 150    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 151    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 152    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 153    case PIPE_CAP_QUERY_TIMESTAMP:
 154    case PIPE_CAP_QUERY_TIME_ELAPSED:
 155    case PIPE_CAP_OCCLUSION_QUERY:
 156    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 157    case PIPE_CAP_INDEP_BLEND_ENABLE:
 158    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 159    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 160    case PIPE_CAP_PRIMITIVE_RESTART:
 161    case PIPE_CAP_TGSI_INSTANCEID:
 162    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 163    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 164    case PIPE_CAP_CONDITIONAL_RENDER:
 165    case PIPE_CAP_TEXTURE_BARRIER:
 166    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 167    case PIPE_CAP_START_INSTANCE:
 168    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 169    case PIPE_CAP_USER_INDEX_BUFFERS:
 170    case PIPE_CAP_USER_VERTEX_BUFFERS:
 171    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 172    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 173    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 174    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 175    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 176    case PIPE_CAP_CLIP_HALFZ:
 177    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 178    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 179    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 180    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 181    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 182    case PIPE_CAP_TGSI_TXQS:
 183       return 1;
 184    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 185       return 1; /* class_3d >= NVA0_3D_CLASS; */
 186    /* supported on nva0+ */
 187    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 188       return class_3d >= NVA0_3D_CLASS;
 189    /* supported on nva3+ */
 190    case PIPE_CAP_CUBE_MAP_ARRAY:
 191    case PIPE_CAP_INDEP_BLEND_FUNC:
 192    case PIPE_CAP_TEXTURE_QUERY_LOD:
 193    case PIPE_CAP_SAMPLE_SHADING:
 194       return class_3d >= NVA3_3D_CLASS;
 195
 196    /* unsupported caps */
 197    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 198    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 199    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 200    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 201    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 202    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 203    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 204    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 205    case PIPE_CAP_TGSI_TEXCOORD:
 206    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 207    case PIPE_CAP_TEXTURE_GATHER_SM5:
 208    case PIPE_CAP_FAKE_SW_MSAA:
 209    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 210    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 211    case PIPE_CAP_COMPUTE:
 212    case PIPE_CAP_DRAW_INDIRECT:
 213    case PIPE_CAP_VERTEXID_NOBASE:
 214    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 215    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 216    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 217    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 218       return 0;
 219
 220    case PIPE_CAP_VENDOR_ID:
 221       return 0x10de;
 222    case PIPE_CAP_DEVICE_ID: {
 223       uint64_t device_id;
 224       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 225          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 226          return -1;
 227       }
 228       return device_id;
 229    }
 230    case PIPE_CAP_ACCELERATED:
 231       return 1;
 232    case PIPE_CAP_VIDEO_MEMORY:
 233       return dev->vram_size >> 20;
 234    case PIPE_CAP_UMA:
 235       return 0;
 236    }
 237
 238    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 239    return 0;
 240 }
 241
 242 static int
 243 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 244                              enum pipe_shader_cap param)
 245 {
 246    switch (shader) {
 247    case PIPE_SHADER_VERTEX:
 248    case PIPE_SHADER_GEOMETRY:
 249    case PIPE_SHADER_FRAGMENT:
 250       break;
 251    default:
 252       return 0;
 253    }
 254
 255    switch (param) {
 256    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 257    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 258    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 259    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 260       return 16384;
 261    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 262       return 4;
 263    case PIPE_SHADER_CAP_MAX_INPUTS:
 264       if (shader == PIPE_SHADER_VERTEX)
 265          return 32;
 266       return 15;
 267    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 268       return 16;
 269    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 270       return 65536;
 271    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 272       return NV50_MAX_PIPE_CONSTBUFS;
 273    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 274    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 275       return shader != PIPE_SHADER_FRAGMENT;
 276    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 277    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 278       return 1;
 279    case PIPE_SHADER_CAP_MAX_PREDS:
 280       return 0;
 281    case PIPE_SHADER_CAP_MAX_TEMPS:
 282       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 283    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 284       return 1;
 285    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 286       return 0;
 287    case PIPE_SHADER_CAP_SUBROUTINES:
 288       return 0; /* please inline, or provide function declarations */
 289    case PIPE_SHADER_CAP_INTEGERS:
 290       return 1;
 291    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 292       /* The chip could handle more sampler views than samplers */
 293    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 294       return MIN2(16, PIPE_MAX_SAMPLERS);
 295    case PIPE_SHADER_CAP_DOUBLES:
 296    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 297    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 298    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 299    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 300       return 0;
 301    default:
 302       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 303       return 0;
 304    }
 305 }
 306
 307 static float
 308 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 309 {
 310    switch (param) {
 311    case PIPE_CAPF_MAX_LINE_WIDTH:
 312    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 313       return 10.0f;
 314    case PIPE_CAPF_MAX_POINT_WIDTH:
 315    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 316       return 64.0f;
 317    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 318       return 16.0f;
 319    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 320       return 4.0f;
 321    case PIPE_CAPF_GUARD_BAND_LEFT:
 322    case PIPE_CAPF_GUARD_BAND_TOP:
 323       return 0.0f;
 324    case PIPE_CAPF_GUARD_BAND_RIGHT:
 325    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 326       return 0.0f; /* that or infinity */
 327    }
 328
 329    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 330    return 0.0f;
 331 }
 332
 333 static void
 334 nv50_screen_destroy(struct pipe_screen *pscreen)
 335 {
 336    struct nv50_screen *screen = nv50_screen(pscreen);
 337
 338    if (!nouveau_drm_screen_unref(&screen->base))
 339       return;
 340
 341    if (screen->base.fence.current) {
 342       struct nouveau_fence *current = NULL;
 343
 344       /* nouveau_fence_wait will create a new current fence, so wait on the
 345        * _current_ one, and remove both.
 346        */
 347       nouveau_fence_ref(screen->base.fence.current, &current);
 348       nouveau_fence_wait(current);
 349       nouveau_fence_ref(NULL, &current);
 350       nouveau_fence_ref(NULL, &screen->base.fence.current);
 351    }
 352    if (screen->base.pushbuf)
 353       screen->base.pushbuf->user_priv = NULL;
 354
 355    if (screen->blitter)
 356       nv50_blitter_destroy(screen);
 357
 358    nouveau_bo_ref(NULL, &screen->code);
 359    nouveau_bo_ref(NULL, &screen->tls_bo);
 360    nouveau_bo_ref(NULL, &screen->stack_bo);
 361    nouveau_bo_ref(NULL, &screen->txc);
 362    nouveau_bo_ref(NULL, &screen->uniforms);
 363    nouveau_bo_ref(NULL, &screen->fence.bo);
 364
 365    nouveau_heap_destroy(&screen->vp_code_heap);
 366    nouveau_heap_destroy(&screen->gp_code_heap);
 367    nouveau_heap_destroy(&screen->fp_code_heap);
 368
 369    FREE(screen->tic.entries);
 370
 371    nouveau_object_del(&screen->tesla);
 372    nouveau_object_del(&screen->eng2d);
 373    nouveau_object_del(&screen->m2mf);
 374    nouveau_object_del(&screen->sync);
 375
 376    nouveau_screen_fini(&screen->base);
 377
 378    FREE(screen);
 379 }
 380
 381 static void
 382 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 383 {
 384    struct nv50_screen *screen = nv50_screen(pscreen);
 385    struct nouveau_pushbuf *push = screen->base.pushbuf;
 386
 387    /* we need to do it after possible flush in MARK_RING */
 388    *sequence = ++screen->base.fence.sequence;
 389
 390    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 391    PUSH_DATAh(push, screen->fence.bo->offset);
 392    PUSH_DATA (push, screen->fence.bo->offset);
 393    PUSH_DATA (push, *sequence);
 394    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 395                     NV50_3D_QUERY_GET_UNK4 |
 396                     NV50_3D_QUERY_GET_UNIT_CROP |
 397                     NV50_3D_QUERY_GET_TYPE_QUERY |
 398                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 399                     NV50_3D_QUERY_GET_SHORT);
 400 }
 401
 402 static u32
 403 nv50_screen_fence_update(struct pipe_screen *pscreen)
 404 {
 405    return nv50_screen(pscreen)->fence.map[0];
 406 }
 407
 408 static void
 409 nv50_screen_init_hwctx(struct nv50_screen *screen)
 410 {
 411    struct nouveau_pushbuf *push = screen->base.pushbuf;
 412    struct nv04_fifo *fifo;
 413    unsigned i;
 414
 415    fifo = (struct nv04_fifo *)screen->base.channel->data;
 416
 417    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 418    PUSH_DATA (push, screen->m2mf->handle);
 419    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 420    PUSH_DATA (push, screen->sync->handle);
 421    PUSH_DATA (push, fifo->vram);
 422    PUSH_DATA (push, fifo->vram);
 423
 424    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 425    PUSH_DATA (push, screen->eng2d->handle);
 426    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 427    PUSH_DATA (push, screen->sync->handle);
 428    PUSH_DATA (push, fifo->vram);
 429    PUSH_DATA (push, fifo->vram);
 430    PUSH_DATA (push, fifo->vram);
 431    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 432    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 433    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 434    PUSH_DATA (push, 0);
 435    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 436    PUSH_DATA (push, 0);
 437    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 438    PUSH_DATA (push, 1);
 439    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 440    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 441
 442    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 443    PUSH_DATA (push, screen->tesla->handle);
 444
 445    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 446    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 447
 448    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 449    PUSH_DATA (push, screen->sync->handle);
 450    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 451    for (i = 0; i < 11; ++i)
 452       PUSH_DATA(push, fifo->vram);
 453    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 454    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 455       PUSH_DATA(push, fifo->vram);
 456
 457    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 458    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 459    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 460    PUSH_DATA (push, 0xf);
 461
 462    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 463       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 464       PUSH_DATA (push, 0x18);
 465    }
 466
 467    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 468    PUSH_DATA(push, screen->base.device->drm_version >= 0x01000101);
 469
 470    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 471    for (i = 0; i < 8; ++i)
 472       PUSH_DATA(push, screen->base.device->drm_version >= 0x01000101);
 473
 474    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 475    PUSH_DATA (push, 1);
 476
 477    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 478    PUSH_DATA (push, 0);
 479    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 480    PUSH_DATA (push, 0);
 481    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 482    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 483    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 484    PUSH_DATA (push, 0);
 485    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 486    PUSH_DATA (push, 1);
 487    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 488    PUSH_DATA (push, 1);
 489
 490    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 491       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 492       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 493    }
 494
 495    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 496    PUSH_DATA (push, 0);
 497    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 498    PUSH_DATA (push, 0);
 499    PUSH_DATA (push, 0);
 500    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 501    PUSH_DATA (push, 0x3f);
 502
 503    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 504    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 505    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 506
 507    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 508    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 509    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 510
 511    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 512    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 513    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 514
 515    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 516    PUSH_DATAh(push, screen->tls_bo->offset);
 517    PUSH_DATA (push, screen->tls_bo->offset);
 518    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 519
 520    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 521    PUSH_DATAh(push, screen->stack_bo->offset);
 522    PUSH_DATA (push, screen->stack_bo->offset);
 523    PUSH_DATA (push, 4);
 524
 525    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 526    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 527    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 528    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 529
 530    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 531    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 532    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 533    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 534
 535    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 536    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 537    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 538    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 539
 540    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 541    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 542    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 543    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 544
 545    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 546    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 547    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 548    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 549
 550    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 551    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 552    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 553    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 554    PUSH_DATAf(push, 0.0f);
 555    PUSH_DATAf(push, 0.0f);
 556    PUSH_DATAf(push, 0.0f);
 557    PUSH_DATAf(push, 0.0f);
 558    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 559    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 560    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 561
 562    nv50_upload_ms_info(push);
 563
 564    /* max TIC (bits 4:8) & TSC bindings, per program type */
 565    for (i = 0; i < 3; ++i) {
 566       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 567       PUSH_DATA (push, 0x54);
 568    }
 569
 570    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 571    PUSH_DATAh(push, screen->txc->offset);
 572    PUSH_DATA (push, screen->txc->offset);
 573    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 574
 575    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 576    PUSH_DATAh(push, screen->txc->offset + 65536);
 577    PUSH_DATA (push, screen->txc->offset + 65536);
 578    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 579
 580    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 581    PUSH_DATA (push, 0);
 582
 583    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 584    PUSH_DATA (push, 0);
 585    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 586    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 587    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 588    for (i = 0; i < 8 * 2; ++i)
 589       PUSH_DATA(push, 0);
 590    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 591    PUSH_DATA (push, 0);
 592
 593    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 594    PUSH_DATA (push, 1);
 595    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 596       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 597       PUSH_DATAf(push, 0.0f);
 598       PUSH_DATAf(push, 1.0f);
 599       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 600       PUSH_DATA (push, 8192 << 16);
 601       PUSH_DATA (push, 8192 << 16);
 602    }
 603
 604    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 605 #ifdef NV50_SCISSORS_CLIPPING
 606    PUSH_DATA (push, 0x0000);
 607 #else
 608    PUSH_DATA (push, 0x1080);
 609 #endif
 610
 611    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 612    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 613
 614    /* We use scissors instead of exact view volume clipping,
 615     * so they're always enabled.
 616     */
 617    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 618       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 619       PUSH_DATA (push, 1);
 620       PUSH_DATA (push, 8192 << 16);
 621       PUSH_DATA (push, 8192 << 16);
 622    }
 623
 624    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 625    PUSH_DATA (push, 1);
 626    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 627    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 628    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 629    PUSH_DATA (push, 0x11111111);
 630    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 631    PUSH_DATA (push, 1);
 632
 633    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 634    PUSH_DATA (push, 0);
 635    if (screen->base.class_3d >= NV84_3D_CLASS) {
 636       BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
 637       PUSH_DATA (push, 0);
 638    }
 639
 640    PUSH_KICK (push);
 641 }
 642
 643 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 644       uint64_t *tls_size)
 645 {
 646    struct nouveau_device *dev = screen->base.device;
 647    int ret;
 648
 649    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 650          ONE_TEMP_SIZE;
 651    if (nouveau_mesa_debug)
 652       debug_printf("allocating space for %u temps\n",
 653             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 654    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 655          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 656
 657    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 658                         *tls_size, NULL, &screen->tls_bo);
 659    if (ret) {
 660       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 661       return ret;
 662    }
 663
 664    return 0;
 665 }
 666
 667 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 668 {
 669    struct nouveau_pushbuf *push = screen->base.pushbuf;
 670    int ret;
 671    uint64_t tls_size;
 672
 673    if (tls_space < screen->cur_tls_space)
 674       return 0;
 675    if (tls_space > screen->max_tls_space) {
 676       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 677        * LOCAL_WARPS_NO_CLAMP) */
 678       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 679             (unsigned)(tls_space / ONE_TEMP_SIZE),
 680             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 681       return -ENOMEM;
 682    }
 683
 684    nouveau_bo_ref(NULL, &screen->tls_bo);
 685    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 686    if (ret)
 687       return ret;
 688
 689    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 690    PUSH_DATAh(push, screen->tls_bo->offset);
 691    PUSH_DATA (push, screen->tls_bo->offset);
 692    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 693
 694    return 1;
 695 }
 696
 697 struct pipe_screen *
 698 nv50_screen_create(struct nouveau_device *dev)
 699 {
 700    struct nv50_screen *screen;
 701    struct pipe_screen *pscreen;
 702    struct nouveau_object *chan;
 703    uint64_t value;
 704    uint32_t tesla_class;
 705    unsigned stack_size;
 706    int ret;
 707
 708    screen = CALLOC_STRUCT(nv50_screen);
 709    if (!screen)
 710       return NULL;
 711    pscreen = &screen->base.base;
 712
 713    ret = nouveau_screen_init(&screen->base, dev);
 714    if (ret) {
 715       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 716       goto fail;
 717    }
 718
 719    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 720     *  admit them to VRAM.
 721     */
 722    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 723       PIPE_BIND_VERTEX_BUFFER;
 724    screen->base.sysmem_bindings |=
 725       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 726
 727    screen->base.pushbuf->user_priv = screen;
 728    screen->base.pushbuf->rsvd_kick = 5;
 729
 730    chan = screen->base.channel;
 731
 732    pscreen->destroy = nv50_screen_destroy;
 733    pscreen->context_create = nv50_create;
 734    pscreen->is_format_supported = nv50_screen_is_format_supported;
 735    pscreen->get_param = nv50_screen_get_param;
 736    pscreen->get_shader_param = nv50_screen_get_shader_param;
 737    pscreen->get_paramf = nv50_screen_get_paramf;
 738
 739    nv50_screen_init_resource_functions(pscreen);
 740
 741    if (screen->base.device->chipset < 0x84 ||
 742        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 743       /* PMPEG */
 744       nouveau_screen_init_vdec(&screen->base);
 745    } else if (screen->base.device->chipset < 0x98 ||
 746               screen->base.device->chipset == 0xa0) {
 747       /* VP2 */
 748       screen->base.base.get_video_param = nv84_screen_get_video_param;
 749       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 750    } else {
 751       /* VP3/4 */
 752       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 753       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 754    }
 755
 756    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 757                         NULL, &screen->fence.bo);
 758    if (ret) {
 759       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 760       goto fail;
 761    }
 762
 763    nouveau_bo_map(screen->fence.bo, 0, NULL);
 764    screen->fence.map = screen->fence.bo->map;
 765    screen->base.fence.emit = nv50_screen_fence_emit;
 766    screen->base.fence.update = nv50_screen_fence_update;
 767
 768    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 769                             &(struct nv04_notify){ .length = 32 },
 770                             sizeof(struct nv04_notify), &screen->sync);
 771    if (ret) {
 772       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 773       goto fail;
 774    }
 775
 776    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 777                             NULL, 0, &screen->m2mf);
 778    if (ret) {
 779       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 780       goto fail;
 781    }
 782
 783    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 784                             NULL, 0, &screen->eng2d);
 785    if (ret) {
 786       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 787       goto fail;
 788    }
 789
 790    switch (dev->chipset & 0xf0) {
 791    case 0x50:
 792       tesla_class = NV50_3D_CLASS;
 793       break;
 794    case 0x80:
 795    case 0x90:
 796       tesla_class = NV84_3D_CLASS;
 797       break;
 798    case 0xa0:
 799       switch (dev->chipset) {
 800       case 0xa0:
 801       case 0xaa:
 802       case 0xac:
 803          tesla_class = NVA0_3D_CLASS;
 804          break;
 805       case 0xaf:
 806          tesla_class = NVAF_3D_CLASS;
 807          break;
 808       default:
 809          tesla_class = NVA3_3D_CLASS;
 810          break;
 811       }
 812       break;
 813    default:
 814       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 815       goto fail;
 816    }
 817    screen->base.class_3d = tesla_class;
 818
 819    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 820                             NULL, 0, &screen->tesla);
 821    if (ret) {
 822       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 823       goto fail;
 824    }
 825
 826    /* This over-allocates by a page. The GP, which would execute at the end of
 827     * the last page, would trigger faults. The going theory is that it
 828     * prefetches up to a certain amount.
 829     */
 830    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 831                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 832                         NULL, &screen->code);
 833    if (ret) {
 834       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 835       goto fail;
 836    }
 837
 838    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 839    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 840    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 841
 842    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 843
 844    screen->TPs = util_bitcount(value & 0xffff);
 845    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 846
 847    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 848          STACK_WARPS_ALLOC * 64 * 8;
 849
 850    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 851                         &screen->stack_bo);
 852    if (ret) {
 853       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 854       goto fail;
 855    }
 856
 857    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 858          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 859          ONE_TEMP_SIZE;
 860    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 861    screen->max_tls_space /= 2; /* half of vram */
 862
 863    /* hw can address max 64 KiB */
 864    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 865
 866    uint64_t tls_size;
 867    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 868    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 869    if (ret)
 870       goto fail;
 871
 872    if (nouveau_mesa_debug)
 873       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 874             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 875
 876    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 877                         &screen->uniforms);
 878    if (ret) {
 879       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 880       goto fail;
 881    }
 882
 883    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 884                         &screen->txc);
 885    if (ret) {
 886       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 887       goto fail;
 888    }
 889
 890    screen->tic.entries = CALLOC(4096, sizeof(void *));
 891    screen->tsc.entries = screen->tic.entries + 2048;
 892
 893    if (!nv50_blitter_create(screen))
 894       goto fail;
 895
 896    nv50_screen_init_hwctx(screen);
 897
 898    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
 899
 900    return pscreen;
 901
 902 fail:
 903    nv50_screen_destroy(pscreen);
 904    return NULL;
 905 }
 906
 907 int
 908 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 909 {
 910    int i = screen->tic.next;
 911
 912    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 913       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 914
 915    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 916
 917    if (screen->tic.entries[i])
 918       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 919
 920    screen->tic.entries[i] = entry;
 921    return i;
 922 }
 923
 924 int
 925 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 926 {
 927    int i = screen->tsc.next;
 928
 929    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 930       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 931
 932    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 933
 934    if (screen->tsc.entries[i])
 935       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 936
 937    screen->tsc.entries[i] = entry;
 938    return i;
 939 }