src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    /* transfers & shared are always supported */
  71    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  72                  PIPE_BIND_TRANSFER_WRITE |
  73                  PIPE_BIND_SHARED);
  74
  75    return (nv50_format_table[format].usage & bindings) == bindings;
  76 }
  77
  78 static int
  79 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  80 {
  81    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  82    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  83
  84    switch (param) {
  85    /* non-boolean caps */
  86    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  87       return 14;
  88    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  89       return 12;
  90    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  91       return 14;
  92    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  93       return 512;
  94    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  95    case PIPE_CAP_MIN_TEXEL_OFFSET:
  96       return -8;
  97    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  98    case PIPE_CAP_MAX_TEXEL_OFFSET:
  99       return 7;
 100    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 101       return 128 * 1024 * 1024;
 102    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 103       return 330;
 104    case PIPE_CAP_MAX_RENDER_TARGETS:
 105       return 8;
 106    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 107       return 1;
 108    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 109       return 4;
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 111    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 112       return 64;
 113    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 114    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 115       return 1024;
 116    case PIPE_CAP_MAX_VERTEX_STREAMS:
 117       return 1;
 118    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 119       return 2048;
 120    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 121       return 256;
 122    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 123       return 1; /* 256 for binding as RT, but that's not possible in GL */
 124    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 125       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 126    case PIPE_CAP_MAX_VIEWPORTS:
 127       return NV50_MAX_VIEWPORTS;
 128    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 129       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 130    case PIPE_CAP_ENDIANNESS:
 131       return PIPE_ENDIAN_LITTLE;
 132    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 133       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 134
 135    /* supported caps */
 136    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 137    case PIPE_CAP_TEXTURE_SWIZZLE:
 138    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 139    case PIPE_CAP_NPOT_TEXTURES:
 140    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 141    case PIPE_CAP_ANISOTROPIC_FILTER:
 142    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 143    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 144    case PIPE_CAP_TWO_SIDED_STENCIL:
 145    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 146    case PIPE_CAP_POINT_SPRITE:
 147    case PIPE_CAP_SM3:
 148    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 149    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 150    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 151    case PIPE_CAP_QUERY_TIMESTAMP:
 152    case PIPE_CAP_QUERY_TIME_ELAPSED:
 153    case PIPE_CAP_OCCLUSION_QUERY:
 154    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 155    case PIPE_CAP_INDEP_BLEND_ENABLE:
 156    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 157    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 158    case PIPE_CAP_PRIMITIVE_RESTART:
 159    case PIPE_CAP_TGSI_INSTANCEID:
 160    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 161    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 162    case PIPE_CAP_CONDITIONAL_RENDER:
 163    case PIPE_CAP_TEXTURE_BARRIER:
 164    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 165    case PIPE_CAP_START_INSTANCE:
 166    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 167    case PIPE_CAP_USER_INDEX_BUFFERS:
 168    case PIPE_CAP_USER_VERTEX_BUFFERS:
 169    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 170    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 171    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 172    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 173    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 174    case PIPE_CAP_CLIP_HALFZ:
 175    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 176    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 177    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 178    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 179    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 180    case PIPE_CAP_TGSI_TXQS:
 181    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 182    case PIPE_CAP_SHAREABLE_SHADERS:
 183    case PIPE_CAP_CLEAR_TEXTURE:
 184    case PIPE_CAP_COMPUTE:
 185    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 186       return 1;
 187    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 188       return 1; /* class_3d >= NVA0_3D_CLASS; */
 189    /* supported on nva0+ */
 190    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 191       return class_3d >= NVA0_3D_CLASS;
 192    /* supported on nva3+ */
 193    case PIPE_CAP_CUBE_MAP_ARRAY:
 194    case PIPE_CAP_INDEP_BLEND_FUNC:
 195    case PIPE_CAP_TEXTURE_QUERY_LOD:
 196    case PIPE_CAP_SAMPLE_SHADING:
 197    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 198       return class_3d >= NVA3_3D_CLASS;
 199
 200    /* unsupported caps */
 201    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 202    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 203    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 204    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 205    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 206    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 207    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 208    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 209    case PIPE_CAP_TGSI_TEXCOORD:
 210    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 211    case PIPE_CAP_TEXTURE_GATHER_SM5:
 212    case PIPE_CAP_FAKE_SW_MSAA:
 213    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 214    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 215    case PIPE_CAP_DRAW_INDIRECT:
 216    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 217    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 218    case PIPE_CAP_VERTEXID_NOBASE:
 219    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 220    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 221    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 222    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 223    case PIPE_CAP_DRAW_PARAMETERS:
 224    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 225    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 226    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 227    case PIPE_CAP_INVALIDATE_BUFFER:
 228    case PIPE_CAP_GENERATE_MIPMAP:
 229       return 0;
 230
 231    case PIPE_CAP_VENDOR_ID:
 232       return 0x10de;
 233    case PIPE_CAP_DEVICE_ID: {
 234       uint64_t device_id;
 235       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 236          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 237          return -1;
 238       }
 239       return device_id;
 240    }
 241    case PIPE_CAP_ACCELERATED:
 242       return 1;
 243    case PIPE_CAP_VIDEO_MEMORY:
 244       return dev->vram_size >> 20;
 245    case PIPE_CAP_UMA:
 246       return 0;
 247    }
 248
 249    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 250    return 0;
 251 }
 252
 253 static int
 254 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 255                              enum pipe_shader_cap param)
 256 {
 257    switch (shader) {
 258    case PIPE_SHADER_VERTEX:
 259    case PIPE_SHADER_GEOMETRY:
 260    case PIPE_SHADER_FRAGMENT:
 261    case PIPE_SHADER_COMPUTE:
 262       break;
 263    default:
 264       return 0;
 265    }
 266
 267    switch (param) {
 268    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 269    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 270    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 271    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 272       return 16384;
 273    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 274       return 4;
 275    case PIPE_SHADER_CAP_MAX_INPUTS:
 276       if (shader == PIPE_SHADER_VERTEX)
 277          return 32;
 278       return 15;
 279    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 280       return 16;
 281    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 282       return 65536;
 283    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 284       return NV50_MAX_PIPE_CONSTBUFS;
 285    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 286    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 287       return shader != PIPE_SHADER_FRAGMENT;
 288    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 289    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 290       return 1;
 291    case PIPE_SHADER_CAP_MAX_PREDS:
 292       return 0;
 293    case PIPE_SHADER_CAP_MAX_TEMPS:
 294       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 295    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 296       return 1;
 297    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 298       return 0;
 299    case PIPE_SHADER_CAP_SUBROUTINES:
 300       return 0; /* please inline, or provide function declarations */
 301    case PIPE_SHADER_CAP_INTEGERS:
 302       return 1;
 303    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 304       /* The chip could handle more sampler views than samplers */
 305    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 306       return MIN2(16, PIPE_MAX_SAMPLERS);
 307    case PIPE_SHADER_CAP_DOUBLES:
 308    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 309    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 310    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 311    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 312    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 313       return 0;
 314    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 315       return 32;
 316    default:
 317       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 318       return 0;
 319    }
 320 }
 321
 322 static float
 323 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 324 {
 325    switch (param) {
 326    case PIPE_CAPF_MAX_LINE_WIDTH:
 327    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 328       return 10.0f;
 329    case PIPE_CAPF_MAX_POINT_WIDTH:
 330    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 331       return 64.0f;
 332    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 333       return 16.0f;
 334    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 335       return 4.0f;
 336    case PIPE_CAPF_GUARD_BAND_LEFT:
 337    case PIPE_CAPF_GUARD_BAND_TOP:
 338       return 0.0f;
 339    case PIPE_CAPF_GUARD_BAND_RIGHT:
 340    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 341       return 0.0f; /* that or infinity */
 342    }
 343
 344    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 345    return 0.0f;
 346 }
 347
 348 static int
 349 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 350                               enum pipe_compute_cap param, void *data)
 351 {
 352    struct nv50_screen *screen = nv50_screen(pscreen);
 353
 354 #define RET(x) do {                  \
 355    if (data)                         \
 356       memcpy(data, x, sizeof(x));    \
 357    return sizeof(x);                 \
 358 } while (0)
 359
 360    switch (param) {
 361    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 362       RET((uint64_t []) { 2 });
 363    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 364       RET(((uint64_t []) { 65535, 65535 }));
 365    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 366       RET(((uint64_t []) { 512, 512, 64 }));
 367    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 368       RET((uint64_t []) { 512 });
 369    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 370       RET((uint64_t []) { 1ULL << 32 });
 371    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 372       RET((uint64_t []) { 16 << 10 });
 373    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 374       RET((uint64_t []) { 16 << 10 });
 375    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 376       RET((uint64_t []) { 4096 });
 377    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 378       RET((uint32_t []) { 32 });
 379    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 380       RET((uint64_t []) { 1ULL << 40 });
 381    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 382       RET((uint32_t []) { 0 });
 383    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 384       RET((uint32_t []) { screen->mp_count });
 385    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 386       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 387    default:
 388       return 0;
 389    }
 390
 391 #undef RET
 392 }
 393
 394 static void
 395 nv50_screen_destroy(struct pipe_screen *pscreen)
 396 {
 397    struct nv50_screen *screen = nv50_screen(pscreen);
 398
 399    if (!nouveau_drm_screen_unref(&screen->base))
 400       return;
 401
 402    if (screen->base.fence.current) {
 403       struct nouveau_fence *current = NULL;
 404
 405       /* nouveau_fence_wait will create a new current fence, so wait on the
 406        * _current_ one, and remove both.
 407        */
 408       nouveau_fence_ref(screen->base.fence.current, &current);
 409       nouveau_fence_wait(current, NULL);
 410       nouveau_fence_ref(NULL, &current);
 411       nouveau_fence_ref(NULL, &screen->base.fence.current);
 412    }
 413    if (screen->base.pushbuf)
 414       screen->base.pushbuf->user_priv = NULL;
 415
 416    if (screen->blitter)
 417       nv50_blitter_destroy(screen);
 418    if (screen->pm.prog) {
 419       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 420       nv50_program_destroy(NULL, screen->pm.prog);
 421       FREE(screen->pm.prog);
 422    }
 423
 424    nouveau_bo_ref(NULL, &screen->code);
 425    nouveau_bo_ref(NULL, &screen->tls_bo);
 426    nouveau_bo_ref(NULL, &screen->stack_bo);
 427    nouveau_bo_ref(NULL, &screen->txc);
 428    nouveau_bo_ref(NULL, &screen->uniforms);
 429    nouveau_bo_ref(NULL, &screen->fence.bo);
 430
 431    nouveau_heap_destroy(&screen->vp_code_heap);
 432    nouveau_heap_destroy(&screen->gp_code_heap);
 433    nouveau_heap_destroy(&screen->fp_code_heap);
 434
 435    FREE(screen->tic.entries);
 436
 437    nouveau_object_del(&screen->tesla);
 438    nouveau_object_del(&screen->eng2d);
 439    nouveau_object_del(&screen->m2mf);
 440    nouveau_object_del(&screen->compute);
 441    nouveau_object_del(&screen->sync);
 442
 443    nouveau_screen_fini(&screen->base);
 444
 445    FREE(screen);
 446 }
 447
 448 static void
 449 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 450 {
 451    struct nv50_screen *screen = nv50_screen(pscreen);
 452    struct nouveau_pushbuf *push = screen->base.pushbuf;
 453
 454    /* we need to do it after possible flush in MARK_RING */
 455    *sequence = ++screen->base.fence.sequence;
 456
 457    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 458    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 459    PUSH_DATAh(push, screen->fence.bo->offset);
 460    PUSH_DATA (push, screen->fence.bo->offset);
 461    PUSH_DATA (push, *sequence);
 462    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 463                     NV50_3D_QUERY_GET_UNK4 |
 464                     NV50_3D_QUERY_GET_UNIT_CROP |
 465                     NV50_3D_QUERY_GET_TYPE_QUERY |
 466                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 467                     NV50_3D_QUERY_GET_SHORT);
 468 }
 469
 470 static u32
 471 nv50_screen_fence_update(struct pipe_screen *pscreen)
 472 {
 473    return nv50_screen(pscreen)->fence.map[0];
 474 }
 475
 476 static void
 477 nv50_screen_init_hwctx(struct nv50_screen *screen)
 478 {
 479    struct nouveau_pushbuf *push = screen->base.pushbuf;
 480    struct nv04_fifo *fifo;
 481    unsigned i;
 482
 483    fifo = (struct nv04_fifo *)screen->base.channel->data;
 484
 485    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 486    PUSH_DATA (push, screen->m2mf->handle);
 487    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 488    PUSH_DATA (push, screen->sync->handle);
 489    PUSH_DATA (push, fifo->vram);
 490    PUSH_DATA (push, fifo->vram);
 491
 492    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 493    PUSH_DATA (push, screen->eng2d->handle);
 494    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 495    PUSH_DATA (push, screen->sync->handle);
 496    PUSH_DATA (push, fifo->vram);
 497    PUSH_DATA (push, fifo->vram);
 498    PUSH_DATA (push, fifo->vram);
 499    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 500    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 501    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 502    PUSH_DATA (push, 0);
 503    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 504    PUSH_DATA (push, 0);
 505    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 506    PUSH_DATA (push, 1);
 507    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 508    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 509
 510    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 511    PUSH_DATA (push, screen->tesla->handle);
 512
 513    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 514    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 515
 516    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 517    PUSH_DATA (push, screen->sync->handle);
 518    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 519    for (i = 0; i < 11; ++i)
 520       PUSH_DATA(push, fifo->vram);
 521    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 522    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 523       PUSH_DATA(push, fifo->vram);
 524
 525    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 526    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 527    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 528    PUSH_DATA (push, 0xf);
 529
 530    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 531       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 532       PUSH_DATA (push, 0x18);
 533    }
 534
 535    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 536    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 537
 538    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 539    for (i = 0; i < 8; ++i)
 540       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 541
 542    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 543    PUSH_DATA (push, 1);
 544
 545    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 546    PUSH_DATA (push, 0);
 547    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 548    PUSH_DATA (push, 0);
 549    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 550    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 551    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 552    PUSH_DATA (push, 0);
 553    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 554    PUSH_DATA (push, 1);
 555    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 556    PUSH_DATA (push, 1);
 557
 558    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 559       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 560       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 561    }
 562
 563    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 564    PUSH_DATA (push, 0);
 565    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 566    PUSH_DATA (push, 0);
 567    PUSH_DATA (push, 0);
 568    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 569    PUSH_DATA (push, 0x3f);
 570
 571    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 572    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 573    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 574
 575    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 576    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 577    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 578
 579    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 580    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 581    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 582
 583    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 584    PUSH_DATAh(push, screen->tls_bo->offset);
 585    PUSH_DATA (push, screen->tls_bo->offset);
 586    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 587
 588    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 589    PUSH_DATAh(push, screen->stack_bo->offset);
 590    PUSH_DATA (push, screen->stack_bo->offset);
 591    PUSH_DATA (push, 4);
 592
 593    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 594    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 595    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 596    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 597
 598    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 599    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 600    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 601    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 602
 603    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 604    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 605    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 606    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 607
 608    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 609    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 610    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 611    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 612
 613    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 614    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 615    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 616    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 617
 618    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 619    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 620    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 621    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 622    PUSH_DATAf(push, 0.0f);
 623    PUSH_DATAf(push, 0.0f);
 624    PUSH_DATAf(push, 0.0f);
 625    PUSH_DATAf(push, 0.0f);
 626    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 627    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 628    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 629
 630    nv50_upload_ms_info(push);
 631
 632    /* max TIC (bits 4:8) & TSC bindings, per program type */
 633    for (i = 0; i < 3; ++i) {
 634       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 635       PUSH_DATA (push, 0x54);
 636    }
 637
 638    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 639    PUSH_DATAh(push, screen->txc->offset);
 640    PUSH_DATA (push, screen->txc->offset);
 641    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 642
 643    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 644    PUSH_DATAh(push, screen->txc->offset + 65536);
 645    PUSH_DATA (push, screen->txc->offset + 65536);
 646    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 647
 648    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 649    PUSH_DATA (push, 0);
 650
 651    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 652    PUSH_DATA (push, 0);
 653    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 654    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 655    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 656    for (i = 0; i < 8 * 2; ++i)
 657       PUSH_DATA(push, 0);
 658    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 659    PUSH_DATA (push, 0);
 660
 661    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 662    PUSH_DATA (push, 1);
 663    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 664       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 665       PUSH_DATAf(push, 0.0f);
 666       PUSH_DATAf(push, 1.0f);
 667       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 668       PUSH_DATA (push, 8192 << 16);
 669       PUSH_DATA (push, 8192 << 16);
 670    }
 671
 672    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 673 #ifdef NV50_SCISSORS_CLIPPING
 674    PUSH_DATA (push, 0x0000);
 675 #else
 676    PUSH_DATA (push, 0x1080);
 677 #endif
 678
 679    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 680    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 681
 682    /* We use scissors instead of exact view volume clipping,
 683     * so they're always enabled.
 684     */
 685    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 686       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 687       PUSH_DATA (push, 1);
 688       PUSH_DATA (push, 8192 << 16);
 689       PUSH_DATA (push, 8192 << 16);
 690    }
 691
 692    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 693    PUSH_DATA (push, 1);
 694    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 695    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 696    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 697    PUSH_DATA (push, 0x11111111);
 698    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 699    PUSH_DATA (push, 1);
 700
 701    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 702    PUSH_DATA (push, 0);
 703    if (screen->base.class_3d >= NV84_3D_CLASS) {
 704       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 705       PUSH_DATA (push, 0);
 706    }
 707
 708    PUSH_KICK (push);
 709 }
 710
 711 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 712       uint64_t *tls_size)
 713 {
 714    struct nouveau_device *dev = screen->base.device;
 715    int ret;
 716
 717    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 718          ONE_TEMP_SIZE;
 719    if (nouveau_mesa_debug)
 720       debug_printf("allocating space for %u temps\n",
 721             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 722    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 723          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 724
 725    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 726                         *tls_size, NULL, &screen->tls_bo);
 727    if (ret) {
 728       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 729       return ret;
 730    }
 731
 732    return 0;
 733 }
 734
 735 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 736 {
 737    struct nouveau_pushbuf *push = screen->base.pushbuf;
 738    int ret;
 739    uint64_t tls_size;
 740
 741    if (tls_space < screen->cur_tls_space)
 742       return 0;
 743    if (tls_space > screen->max_tls_space) {
 744       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 745        * LOCAL_WARPS_NO_CLAMP) */
 746       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 747             (unsigned)(tls_space / ONE_TEMP_SIZE),
 748             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 749       return -ENOMEM;
 750    }
 751
 752    nouveau_bo_ref(NULL, &screen->tls_bo);
 753    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 754    if (ret)
 755       return ret;
 756
 757    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 758    PUSH_DATAh(push, screen->tls_bo->offset);
 759    PUSH_DATA (push, screen->tls_bo->offset);
 760    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 761
 762    return 1;
 763 }
 764
 765 struct nouveau_screen *
 766 nv50_screen_create(struct nouveau_device *dev)
 767 {
 768    struct nv50_screen *screen;
 769    struct pipe_screen *pscreen;
 770    struct nouveau_object *chan;
 771    uint64_t value;
 772    uint32_t tesla_class;
 773    unsigned stack_size;
 774    int ret;
 775
 776    screen = CALLOC_STRUCT(nv50_screen);
 777    if (!screen)
 778       return NULL;
 779    pscreen = &screen->base.base;
 780    pscreen->destroy = nv50_screen_destroy;
 781
 782    ret = nouveau_screen_init(&screen->base, dev);
 783    if (ret) {
 784       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 785       goto fail;
 786    }
 787
 788    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 789     *  admit them to VRAM.
 790     */
 791    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 792       PIPE_BIND_VERTEX_BUFFER;
 793    screen->base.sysmem_bindings |=
 794       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 795
 796    screen->base.pushbuf->user_priv = screen;
 797    screen->base.pushbuf->rsvd_kick = 5;
 798
 799    chan = screen->base.channel;
 800
 801    pscreen->context_create = nv50_create;
 802    pscreen->is_format_supported = nv50_screen_is_format_supported;
 803    pscreen->get_param = nv50_screen_get_param;
 804    pscreen->get_shader_param = nv50_screen_get_shader_param;
 805    pscreen->get_paramf = nv50_screen_get_paramf;
 806    pscreen->get_compute_param = nv50_screen_get_compute_param;
 807    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 808    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 809
 810    nv50_screen_init_resource_functions(pscreen);
 811
 812    if (screen->base.device->chipset < 0x84 ||
 813        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 814       /* PMPEG */
 815       nouveau_screen_init_vdec(&screen->base);
 816    } else if (screen->base.device->chipset < 0x98 ||
 817               screen->base.device->chipset == 0xa0) {
 818       /* VP2 */
 819       screen->base.base.get_video_param = nv84_screen_get_video_param;
 820       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 821    } else {
 822       /* VP3/4 */
 823       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 824       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 825    }
 826
 827    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 828                         NULL, &screen->fence.bo);
 829    if (ret) {
 830       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 831       goto fail;
 832    }
 833
 834    nouveau_bo_map(screen->fence.bo, 0, NULL);
 835    screen->fence.map = screen->fence.bo->map;
 836    screen->base.fence.emit = nv50_screen_fence_emit;
 837    screen->base.fence.update = nv50_screen_fence_update;
 838
 839    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 840                             &(struct nv04_notify){ .length = 32 },
 841                             sizeof(struct nv04_notify), &screen->sync);
 842    if (ret) {
 843       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 844       goto fail;
 845    }
 846
 847    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 848                             NULL, 0, &screen->m2mf);
 849    if (ret) {
 850       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 851       goto fail;
 852    }
 853
 854    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 855                             NULL, 0, &screen->eng2d);
 856    if (ret) {
 857       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 858       goto fail;
 859    }
 860
 861    switch (dev->chipset & 0xf0) {
 862    case 0x50:
 863       tesla_class = NV50_3D_CLASS;
 864       break;
 865    case 0x80:
 866    case 0x90:
 867       tesla_class = NV84_3D_CLASS;
 868       break;
 869    case 0xa0:
 870       switch (dev->chipset) {
 871       case 0xa0:
 872       case 0xaa:
 873       case 0xac:
 874          tesla_class = NVA0_3D_CLASS;
 875          break;
 876       case 0xaf:
 877          tesla_class = NVAF_3D_CLASS;
 878          break;
 879       default:
 880          tesla_class = NVA3_3D_CLASS;
 881          break;
 882       }
 883       break;
 884    default:
 885       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 886       goto fail;
 887    }
 888    screen->base.class_3d = tesla_class;
 889
 890    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 891                             NULL, 0, &screen->tesla);
 892    if (ret) {
 893       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 894       goto fail;
 895    }
 896
 897    /* This over-allocates by a page. The GP, which would execute at the end of
 898     * the last page, would trigger faults. The going theory is that it
 899     * prefetches up to a certain amount.
 900     */
 901    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 902                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 903                         NULL, &screen->code);
 904    if (ret) {
 905       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 906       goto fail;
 907    }
 908
 909    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 910    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 911    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 912
 913    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 914
 915    screen->TPs = util_bitcount(value & 0xffff);
 916    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 917
 918    screen->mp_count = screen->TPs * screen->MPsInTP;
 919
 920    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 921          STACK_WARPS_ALLOC * 64 * 8;
 922
 923    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 924                         &screen->stack_bo);
 925    if (ret) {
 926       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 927       goto fail;
 928    }
 929
 930    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 931          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 932          ONE_TEMP_SIZE;
 933    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 934    screen->max_tls_space /= 2; /* half of vram */
 935
 936    /* hw can address max 64 KiB */
 937    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 938
 939    uint64_t tls_size;
 940    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 941    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 942    if (ret)
 943       goto fail;
 944
 945    if (nouveau_mesa_debug)
 946       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 947             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 948
 949    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 950                         &screen->uniforms);
 951    if (ret) {
 952       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 953       goto fail;
 954    }
 955
 956    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 957                         &screen->txc);
 958    if (ret) {
 959       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 960       goto fail;
 961    }
 962
 963    screen->tic.entries = CALLOC(4096, sizeof(void *));
 964    screen->tsc.entries = screen->tic.entries + 2048;
 965
 966    if (!nv50_blitter_create(screen))
 967       goto fail;
 968
 969    nv50_screen_init_hwctx(screen);
 970
 971    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
 972    if (ret) {
 973       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
 974       goto fail;
 975    }
 976
 977    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
 978
 979    return &screen->base;
 980
 981 fail:
 982    screen->base.base.context_create = NULL;
 983    return &screen->base;
 984 }
 985
 986 int
 987 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 988 {
 989    int i = screen->tic.next;
 990
 991    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 992       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 993
 994    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 995
 996    if (screen->tic.entries[i])
 997       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 998
 999    screen->tic.entries[i] = entry;
1000    return i;
1001 }
1002
1003 int
1004 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1005 {
1006    int i = screen->tsc.next;
1007
1008    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1009       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1010
1011    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1012
1013    if (screen->tsc.entries[i])
1014       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1015
1016    screen->tsc.entries[i] = entry;
1017    return i;
1018 }