src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* transfers & shared are always supported */
  79    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  80                  PIPE_BIND_TRANSFER_WRITE |
  81                  PIPE_BIND_LINEAR |
  82                  PIPE_BIND_SHARED);
  83
  84    return (( nv50_format_table[format].usage |
  85             nv50_vertex_format[format].usage) & bindings) == bindings;
  86 }
  87
  88 static int
  89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  90 {
  91    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  92    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  93
  94    switch (param) {
  95    /* non-boolean caps */
  96    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  97       return 14;
  98    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  99       return 12;
 100    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 101       return 14;
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103       return 512;
 104    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 105    case PIPE_CAP_MIN_TEXEL_OFFSET:
 106       return -8;
 107    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109       return 7;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 128 * 1024 * 1024;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 113       return 330;
 114    case PIPE_CAP_MAX_RENDER_TARGETS:
 115       return 8;
 116    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 117       return 1;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 119       return 4;
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122       return 64;
 123    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 124    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 125       return 1024;
 126    case PIPE_CAP_MAX_VERTEX_STREAMS:
 127       return 1;
 128    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 129       return 2048;
 130    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 131       return 256;
 132    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 133       return 16; /* 256 for binding as RT, but that's not possible in GL */
 134    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 135       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 136    case PIPE_CAP_MAX_VIEWPORTS:
 137       return NV50_MAX_VIEWPORTS;
 138    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 139       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 140    case PIPE_CAP_ENDIANNESS:
 141       return PIPE_ENDIAN_LITTLE;
 142    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 143       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 144
 145    /* supported caps */
 146    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 147    case PIPE_CAP_TEXTURE_SWIZZLE:
 148    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 149    case PIPE_CAP_NPOT_TEXTURES:
 150    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151    case PIPE_CAP_ANISOTROPIC_FILTER:
 152    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 153    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 154    case PIPE_CAP_TWO_SIDED_STENCIL:
 155    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 156    case PIPE_CAP_POINT_SPRITE:
 157    case PIPE_CAP_SM3:
 158    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 159    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 160    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 161    case PIPE_CAP_QUERY_TIMESTAMP:
 162    case PIPE_CAP_QUERY_TIME_ELAPSED:
 163    case PIPE_CAP_OCCLUSION_QUERY:
 164    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 165    case PIPE_CAP_INDEP_BLEND_ENABLE:
 166    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 167    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 168    case PIPE_CAP_PRIMITIVE_RESTART:
 169    case PIPE_CAP_TGSI_INSTANCEID:
 170    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 171    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 172    case PIPE_CAP_CONDITIONAL_RENDER:
 173    case PIPE_CAP_TEXTURE_BARRIER:
 174    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 175    case PIPE_CAP_START_INSTANCE:
 176    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 177    case PIPE_CAP_USER_INDEX_BUFFERS:
 178    case PIPE_CAP_USER_VERTEX_BUFFERS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 181    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 182    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 183    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 184    case PIPE_CAP_CLIP_HALFZ:
 185    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 186    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 187    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 188    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 189    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 190    case PIPE_CAP_TGSI_TXQS:
 191    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 192    case PIPE_CAP_SHAREABLE_SHADERS:
 193    case PIPE_CAP_CLEAR_TEXTURE:
 194    case PIPE_CAP_COMPUTE:
 195    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 196    case PIPE_CAP_INVALIDATE_BUFFER:
 197    case PIPE_CAP_STRING_MARKER:
 198    case PIPE_CAP_CULL_DISTANCE:
 199       return 1;
 200    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 201       return 1; /* class_3d >= NVA0_3D_CLASS; */
 202    /* supported on nva0+ */
 203    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 204       return class_3d >= NVA0_3D_CLASS;
 205    /* supported on nva3+ */
 206    case PIPE_CAP_CUBE_MAP_ARRAY:
 207    case PIPE_CAP_INDEP_BLEND_FUNC:
 208    case PIPE_CAP_TEXTURE_QUERY_LOD:
 209    case PIPE_CAP_SAMPLE_SHADING:
 210    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 211       return class_3d >= NVA3_3D_CLASS;
 212
 213    /* unsupported caps */
 214    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 215    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 216    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 217    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 218    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 219    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 220    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 221    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 222    case PIPE_CAP_TGSI_TEXCOORD:
 223    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 224    case PIPE_CAP_TEXTURE_GATHER_SM5:
 225    case PIPE_CAP_FAKE_SW_MSAA:
 226    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 227    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 228    case PIPE_CAP_DRAW_INDIRECT:
 229    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 230    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 231    case PIPE_CAP_VERTEXID_NOBASE:
 232    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 233    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 234    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 235    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 236    case PIPE_CAP_DRAW_PARAMETERS:
 237    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 238    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 239    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 240    case PIPE_CAP_GENERATE_MIPMAP:
 241    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 242    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 243    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 244    case PIPE_CAP_QUERY_MEMORY_INFO:
 245    case PIPE_CAP_PCI_GROUP:
 246    case PIPE_CAP_PCI_BUS:
 247    case PIPE_CAP_PCI_DEVICE:
 248    case PIPE_CAP_PCI_FUNCTION:
 249    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 250    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 251       return 0;
 252
 253    case PIPE_CAP_VENDOR_ID:
 254       return 0x10de;
 255    case PIPE_CAP_DEVICE_ID: {
 256       uint64_t device_id;
 257       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 258          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 259          return -1;
 260       }
 261       return device_id;
 262    }
 263    case PIPE_CAP_ACCELERATED:
 264       return 1;
 265    case PIPE_CAP_VIDEO_MEMORY:
 266       return dev->vram_size >> 20;
 267    case PIPE_CAP_UMA:
 268       return 0;
 269    }
 270
 271    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 272    return 0;
 273 }
 274
 275 static int
 276 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 277                              enum pipe_shader_cap param)
 278 {
 279    switch (shader) {
 280    case PIPE_SHADER_VERTEX:
 281    case PIPE_SHADER_GEOMETRY:
 282    case PIPE_SHADER_FRAGMENT:
 283       break;
 284    case PIPE_SHADER_COMPUTE:
 285    default:
 286       return 0;
 287    }
 288
 289    switch (param) {
 290    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 291    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 292    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 293    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 294       return 16384;
 295    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 296       return 4;
 297    case PIPE_SHADER_CAP_MAX_INPUTS:
 298       if (shader == PIPE_SHADER_VERTEX)
 299          return 32;
 300       return 15;
 301    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 302       return 16;
 303    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 304       return 65536;
 305    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 306       return NV50_MAX_PIPE_CONSTBUFS;
 307    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 308    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 309       return shader != PIPE_SHADER_FRAGMENT;
 310    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 311    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 312       return 1;
 313    case PIPE_SHADER_CAP_MAX_PREDS:
 314       return 0;
 315    case PIPE_SHADER_CAP_MAX_TEMPS:
 316       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 317    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 318       return 1;
 319    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 320       return 1;
 321    case PIPE_SHADER_CAP_SUBROUTINES:
 322       return 0; /* please inline, or provide function declarations */
 323    case PIPE_SHADER_CAP_INTEGERS:
 324       return 1;
 325    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 326       /* The chip could handle more sampler views than samplers */
 327    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 328       return MIN2(16, PIPE_MAX_SAMPLERS);
 329    case PIPE_SHADER_CAP_DOUBLES:
 330    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 331    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 332    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 333    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 334    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 335    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 336    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 337       return 0;
 338    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 339       return 32;
 340    default:
 341       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 342       return 0;
 343    }
 344 }
 345
 346 static float
 347 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 348 {
 349    switch (param) {
 350    case PIPE_CAPF_MAX_LINE_WIDTH:
 351    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 352       return 10.0f;
 353    case PIPE_CAPF_MAX_POINT_WIDTH:
 354    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 355       return 64.0f;
 356    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 357       return 16.0f;
 358    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 359       return 4.0f;
 360    case PIPE_CAPF_GUARD_BAND_LEFT:
 361    case PIPE_CAPF_GUARD_BAND_TOP:
 362       return 0.0f;
 363    case PIPE_CAPF_GUARD_BAND_RIGHT:
 364    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 365       return 0.0f; /* that or infinity */
 366    }
 367
 368    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 369    return 0.0f;
 370 }
 371
 372 static int
 373 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 374                               enum pipe_shader_ir ir_type,
 375                               enum pipe_compute_cap param, void *data)
 376 {
 377    struct nv50_screen *screen = nv50_screen(pscreen);
 378
 379 #define RET(x) do {                  \
 380    if (data)                         \
 381       memcpy(data, x, sizeof(x));    \
 382    return sizeof(x);                 \
 383 } while (0)
 384
 385    switch (param) {
 386    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 387       RET((uint64_t []) { 2 });
 388    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 389       RET(((uint64_t []) { 65535, 65535 }));
 390    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 391       RET(((uint64_t []) { 512, 512, 64 }));
 392    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 393       RET((uint64_t []) { 512 });
 394    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 395       RET((uint64_t []) { 1ULL << 32 });
 396    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 397       RET((uint64_t []) { 16 << 10 });
 398    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 399       RET((uint64_t []) { 16 << 10 });
 400    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 401       RET((uint64_t []) { 4096 });
 402    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 403       RET((uint32_t []) { 32 });
 404    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 405       RET((uint64_t []) { 1ULL << 40 });
 406    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 407       RET((uint32_t []) { 0 });
 408    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 409       RET((uint32_t []) { screen->mp_count });
 410    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 411       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 412    default:
 413       return 0;
 414    }
 415
 416 #undef RET
 417 }
 418
 419 static void
 420 nv50_screen_destroy(struct pipe_screen *pscreen)
 421 {
 422    struct nv50_screen *screen = nv50_screen(pscreen);
 423
 424    if (!nouveau_drm_screen_unref(&screen->base))
 425       return;
 426
 427    if (screen->base.fence.current) {
 428       struct nouveau_fence *current = NULL;
 429
 430       /* nouveau_fence_wait will create a new current fence, so wait on the
 431        * _current_ one, and remove both.
 432        */
 433       nouveau_fence_ref(screen->base.fence.current, &current);
 434       nouveau_fence_wait(current, NULL);
 435       nouveau_fence_ref(NULL, &current);
 436       nouveau_fence_ref(NULL, &screen->base.fence.current);
 437    }
 438    if (screen->base.pushbuf)
 439       screen->base.pushbuf->user_priv = NULL;
 440
 441    if (screen->blitter)
 442       nv50_blitter_destroy(screen);
 443    if (screen->pm.prog) {
 444       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 445       nv50_program_destroy(NULL, screen->pm.prog);
 446       FREE(screen->pm.prog);
 447    }
 448
 449    nouveau_bo_ref(NULL, &screen->code);
 450    nouveau_bo_ref(NULL, &screen->tls_bo);
 451    nouveau_bo_ref(NULL, &screen->stack_bo);
 452    nouveau_bo_ref(NULL, &screen->txc);
 453    nouveau_bo_ref(NULL, &screen->uniforms);
 454    nouveau_bo_ref(NULL, &screen->fence.bo);
 455
 456    nouveau_heap_destroy(&screen->vp_code_heap);
 457    nouveau_heap_destroy(&screen->gp_code_heap);
 458    nouveau_heap_destroy(&screen->fp_code_heap);
 459
 460    FREE(screen->tic.entries);
 461
 462    nouveau_object_del(&screen->tesla);
 463    nouveau_object_del(&screen->eng2d);
 464    nouveau_object_del(&screen->m2mf);
 465    nouveau_object_del(&screen->compute);
 466    nouveau_object_del(&screen->sync);
 467
 468    nouveau_screen_fini(&screen->base);
 469
 470    FREE(screen);
 471 }
 472
 473 static void
 474 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 475 {
 476    struct nv50_screen *screen = nv50_screen(pscreen);
 477    struct nouveau_pushbuf *push = screen->base.pushbuf;
 478
 479    /* we need to do it after possible flush in MARK_RING */
 480    *sequence = ++screen->base.fence.sequence;
 481
 482    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 483    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 484    PUSH_DATAh(push, screen->fence.bo->offset);
 485    PUSH_DATA (push, screen->fence.bo->offset);
 486    PUSH_DATA (push, *sequence);
 487    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 488                     NV50_3D_QUERY_GET_UNK4 |
 489                     NV50_3D_QUERY_GET_UNIT_CROP |
 490                     NV50_3D_QUERY_GET_TYPE_QUERY |
 491                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 492                     NV50_3D_QUERY_GET_SHORT);
 493 }
 494
 495 static u32
 496 nv50_screen_fence_update(struct pipe_screen *pscreen)
 497 {
 498    return nv50_screen(pscreen)->fence.map[0];
 499 }
 500
 501 static void
 502 nv50_screen_init_hwctx(struct nv50_screen *screen)
 503 {
 504    struct nouveau_pushbuf *push = screen->base.pushbuf;
 505    struct nv04_fifo *fifo;
 506    unsigned i;
 507
 508    fifo = (struct nv04_fifo *)screen->base.channel->data;
 509
 510    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 511    PUSH_DATA (push, screen->m2mf->handle);
 512    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 513    PUSH_DATA (push, screen->sync->handle);
 514    PUSH_DATA (push, fifo->vram);
 515    PUSH_DATA (push, fifo->vram);
 516
 517    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 518    PUSH_DATA (push, screen->eng2d->handle);
 519    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 520    PUSH_DATA (push, screen->sync->handle);
 521    PUSH_DATA (push, fifo->vram);
 522    PUSH_DATA (push, fifo->vram);
 523    PUSH_DATA (push, fifo->vram);
 524    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 525    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 526    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 527    PUSH_DATA (push, 0);
 528    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 529    PUSH_DATA (push, 0);
 530    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 531    PUSH_DATA (push, 1);
 532    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 533    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 534
 535    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 536    PUSH_DATA (push, screen->tesla->handle);
 537
 538    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 539    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 540
 541    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 542    PUSH_DATA (push, screen->sync->handle);
 543    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 544    for (i = 0; i < 11; ++i)
 545       PUSH_DATA(push, fifo->vram);
 546    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 547    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 548       PUSH_DATA(push, fifo->vram);
 549
 550    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 551    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 552    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 553    PUSH_DATA (push, 0xf);
 554
 555    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 556       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 557       PUSH_DATA (push, 0x18);
 558    }
 559
 560    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 561    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 562
 563    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 564    for (i = 0; i < 8; ++i)
 565       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 566
 567    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 568    PUSH_DATA (push, 1);
 569
 570    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 571    PUSH_DATA (push, 0);
 572    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 573    PUSH_DATA (push, 0);
 574    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 575    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 576    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 577    PUSH_DATA (push, 0);
 578    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 579    PUSH_DATA (push, 1);
 580    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 581    PUSH_DATA (push, 1);
 582
 583    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 584       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 585       PUSH_DATA (push, 0);
 586    }
 587
 588    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 589    PUSH_DATA (push, 0);
 590    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 591    PUSH_DATA (push, 0);
 592    PUSH_DATA (push, 0);
 593    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 594    PUSH_DATA (push, 0x3f);
 595
 596    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 597    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 598    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 599
 600    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 601    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 602    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 603
 604    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 605    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 606    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 607
 608    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 609    PUSH_DATAh(push, screen->tls_bo->offset);
 610    PUSH_DATA (push, screen->tls_bo->offset);
 611    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 612
 613    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 614    PUSH_DATAh(push, screen->stack_bo->offset);
 615    PUSH_DATA (push, screen->stack_bo->offset);
 616    PUSH_DATA (push, 4);
 617
 618    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 619    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 620    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 621    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 622
 623    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 624    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 625    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 626    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 627
 628    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 629    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 630    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 631    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 632
 633    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 634    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 635    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 636    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 637
 638    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 639    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 640    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 641    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 642
 643    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 644    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 645    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 646    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 647    PUSH_DATAf(push, 0.0f);
 648    PUSH_DATAf(push, 0.0f);
 649    PUSH_DATAf(push, 0.0f);
 650    PUSH_DATAf(push, 0.0f);
 651    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 652    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 653    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 654
 655    nv50_upload_ms_info(push);
 656
 657    /* max TIC (bits 4:8) & TSC bindings, per program type */
 658    for (i = 0; i < 3; ++i) {
 659       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 660       PUSH_DATA (push, 0x54);
 661    }
 662
 663    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 664    PUSH_DATAh(push, screen->txc->offset);
 665    PUSH_DATA (push, screen->txc->offset);
 666    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 667
 668    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 669    PUSH_DATAh(push, screen->txc->offset + 65536);
 670    PUSH_DATA (push, screen->txc->offset + 65536);
 671    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 672
 673    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 674    PUSH_DATA (push, 0);
 675
 676    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 677    PUSH_DATA (push, 0);
 678    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 679    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 680    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 681    for (i = 0; i < 8 * 2; ++i)
 682       PUSH_DATA(push, 0);
 683    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 684    PUSH_DATA (push, 0);
 685
 686    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 687    PUSH_DATA (push, 1);
 688    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 689       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 690       PUSH_DATAf(push, 0.0f);
 691       PUSH_DATAf(push, 1.0f);
 692       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 693       PUSH_DATA (push, 8192 << 16);
 694       PUSH_DATA (push, 8192 << 16);
 695    }
 696
 697    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 698 #ifdef NV50_SCISSORS_CLIPPING
 699    PUSH_DATA (push, 0x0000);
 700 #else
 701    PUSH_DATA (push, 0x1080);
 702 #endif
 703
 704    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 705    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 706
 707    /* We use scissors instead of exact view volume clipping,
 708     * so they're always enabled.
 709     */
 710    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 711       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 712       PUSH_DATA (push, 1);
 713       PUSH_DATA (push, 8192 << 16);
 714       PUSH_DATA (push, 8192 << 16);
 715    }
 716
 717    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 718    PUSH_DATA (push, 1);
 719    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 720    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 721    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 722    PUSH_DATA (push, 0x11111111);
 723    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 724    PUSH_DATA (push, 1);
 725
 726    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 727    PUSH_DATA (push, 0);
 728    if (screen->base.class_3d >= NV84_3D_CLASS) {
 729       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 730       PUSH_DATA (push, 0);
 731    }
 732
 733    PUSH_KICK (push);
 734 }
 735
 736 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 737       uint64_t *tls_size)
 738 {
 739    struct nouveau_device *dev = screen->base.device;
 740    int ret;
 741
 742    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 743          ONE_TEMP_SIZE;
 744    if (nouveau_mesa_debug)
 745       debug_printf("allocating space for %u temps\n",
 746             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 747    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 748          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 749
 750    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 751                         *tls_size, NULL, &screen->tls_bo);
 752    if (ret) {
 753       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 754       return ret;
 755    }
 756
 757    return 0;
 758 }
 759
 760 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 761 {
 762    struct nouveau_pushbuf *push = screen->base.pushbuf;
 763    int ret;
 764    uint64_t tls_size;
 765
 766    if (tls_space < screen->cur_tls_space)
 767       return 0;
 768    if (tls_space > screen->max_tls_space) {
 769       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 770        * LOCAL_WARPS_NO_CLAMP) */
 771       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 772             (unsigned)(tls_space / ONE_TEMP_SIZE),
 773             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 774       return -ENOMEM;
 775    }
 776
 777    nouveau_bo_ref(NULL, &screen->tls_bo);
 778    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 779    if (ret)
 780       return ret;
 781
 782    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 783    PUSH_DATAh(push, screen->tls_bo->offset);
 784    PUSH_DATA (push, screen->tls_bo->offset);
 785    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 786
 787    return 1;
 788 }
 789
 790 struct nouveau_screen *
 791 nv50_screen_create(struct nouveau_device *dev)
 792 {
 793    struct nv50_screen *screen;
 794    struct pipe_screen *pscreen;
 795    struct nouveau_object *chan;
 796    uint64_t value;
 797    uint32_t tesla_class;
 798    unsigned stack_size;
 799    int ret;
 800
 801    screen = CALLOC_STRUCT(nv50_screen);
 802    if (!screen)
 803       return NULL;
 804    pscreen = &screen->base.base;
 805    pscreen->destroy = nv50_screen_destroy;
 806
 807    ret = nouveau_screen_init(&screen->base, dev);
 808    if (ret) {
 809       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 810       goto fail;
 811    }
 812
 813    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 814     *  admit them to VRAM.
 815     */
 816    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 817       PIPE_BIND_VERTEX_BUFFER;
 818    screen->base.sysmem_bindings |=
 819       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 820
 821    screen->base.pushbuf->user_priv = screen;
 822    screen->base.pushbuf->rsvd_kick = 5;
 823
 824    chan = screen->base.channel;
 825
 826    pscreen->context_create = nv50_create;
 827    pscreen->is_format_supported = nv50_screen_is_format_supported;
 828    pscreen->get_param = nv50_screen_get_param;
 829    pscreen->get_shader_param = nv50_screen_get_shader_param;
 830    pscreen->get_paramf = nv50_screen_get_paramf;
 831    pscreen->get_compute_param = nv50_screen_get_compute_param;
 832    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 833    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 834
 835    nv50_screen_init_resource_functions(pscreen);
 836
 837    if (screen->base.device->chipset < 0x84 ||
 838        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 839       /* PMPEG */
 840       nouveau_screen_init_vdec(&screen->base);
 841    } else if (screen->base.device->chipset < 0x98 ||
 842               screen->base.device->chipset == 0xa0) {
 843       /* VP2 */
 844       screen->base.base.get_video_param = nv84_screen_get_video_param;
 845       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 846    } else {
 847       /* VP3/4 */
 848       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 849       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 850    }
 851
 852    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 853                         NULL, &screen->fence.bo);
 854    if (ret) {
 855       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 856       goto fail;
 857    }
 858
 859    nouveau_bo_map(screen->fence.bo, 0, NULL);
 860    screen->fence.map = screen->fence.bo->map;
 861    screen->base.fence.emit = nv50_screen_fence_emit;
 862    screen->base.fence.update = nv50_screen_fence_update;
 863
 864    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 865                             &(struct nv04_notify){ .length = 32 },
 866                             sizeof(struct nv04_notify), &screen->sync);
 867    if (ret) {
 868       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 869       goto fail;
 870    }
 871
 872    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 873                             NULL, 0, &screen->m2mf);
 874    if (ret) {
 875       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 876       goto fail;
 877    }
 878
 879    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 880                             NULL, 0, &screen->eng2d);
 881    if (ret) {
 882       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 883       goto fail;
 884    }
 885
 886    switch (dev->chipset & 0xf0) {
 887    case 0x50:
 888       tesla_class = NV50_3D_CLASS;
 889       break;
 890    case 0x80:
 891    case 0x90:
 892       tesla_class = NV84_3D_CLASS;
 893       break;
 894    case 0xa0:
 895       switch (dev->chipset) {
 896       case 0xa0:
 897       case 0xaa:
 898       case 0xac:
 899          tesla_class = NVA0_3D_CLASS;
 900          break;
 901       case 0xaf:
 902          tesla_class = NVAF_3D_CLASS;
 903          break;
 904       default:
 905          tesla_class = NVA3_3D_CLASS;
 906          break;
 907       }
 908       break;
 909    default:
 910       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 911       goto fail;
 912    }
 913    screen->base.class_3d = tesla_class;
 914
 915    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 916                             NULL, 0, &screen->tesla);
 917    if (ret) {
 918       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 919       goto fail;
 920    }
 921
 922    /* This over-allocates by a page. The GP, which would execute at the end of
 923     * the last page, would trigger faults. The going theory is that it
 924     * prefetches up to a certain amount.
 925     */
 926    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 927                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 928                         NULL, &screen->code);
 929    if (ret) {
 930       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 931       goto fail;
 932    }
 933
 934    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 935    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 936    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 937
 938    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 939
 940    screen->TPs = util_bitcount(value & 0xffff);
 941    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 942
 943    screen->mp_count = screen->TPs * screen->MPsInTP;
 944
 945    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 946          STACK_WARPS_ALLOC * 64 * 8;
 947
 948    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 949                         &screen->stack_bo);
 950    if (ret) {
 951       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 952       goto fail;
 953    }
 954
 955    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 956          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 957          ONE_TEMP_SIZE;
 958    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 959    screen->max_tls_space /= 2; /* half of vram */
 960
 961    /* hw can address max 64 KiB */
 962    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 963
 964    uint64_t tls_size;
 965    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 966    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 967    if (ret)
 968       goto fail;
 969
 970    if (nouveau_mesa_debug)
 971       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 972             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 973
 974    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 975                         &screen->uniforms);
 976    if (ret) {
 977       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 978       goto fail;
 979    }
 980
 981    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 982                         &screen->txc);
 983    if (ret) {
 984       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 985       goto fail;
 986    }
 987
 988    screen->tic.entries = CALLOC(4096, sizeof(void *));
 989    screen->tsc.entries = screen->tic.entries + 2048;
 990
 991    if (!nv50_blitter_create(screen))
 992       goto fail;
 993
 994    nv50_screen_init_hwctx(screen);
 995
 996    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
 997    if (ret) {
 998       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
 999       goto fail;
1000    }
1001
1002    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1003
1004    return &screen->base;
1005
1006 fail:
1007    screen->base.base.context_create = NULL;
1008    return &screen->base;
1009 }
1010
1011 int
1012 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1013 {
1014    int i = screen->tic.next;
1015
1016    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1017       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1018
1019    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1020
1021    if (screen->tic.entries[i])
1022       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1023
1024    screen->tic.entries[i] = entry;
1025    return i;
1026 }
1027
1028 int
1029 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1030 {
1031    int i = screen->tsc.next;
1032
1033    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1034       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1035
1036    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1037
1038    if (screen->tsc.entries[i])
1039       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1040
1041    screen->tsc.entries[i] = entry;
1042    return i;
1043 }