src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50/nv50_context.h"
  28 #include "nv50/nv50_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nv_object.xml.h"
  33 #include <errno.h>
  34
  35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  37 #endif
  38
  39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  40 #define LOCAL_WARPS_ALLOC 32
  41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  42 #define STACK_WARPS_ALLOC 32
  43
  44 #define THREADS_IN_WARP 32
  45
  46 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  47
  48 static boolean
  49 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  50                                 enum pipe_format format,
  51                                 enum pipe_texture_target target,
  52                                 unsigned sample_count,
  53                                 unsigned bindings)
  54 {
  55    if (sample_count > 8)
  56       return FALSE;
  57    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  58       return FALSE;
  59    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  60       return FALSE;
  61
  62    if (!util_format_is_supported(format, bindings))
  63       return FALSE;
  64
  65    switch (format) {
  66    case PIPE_FORMAT_Z16_UNORM:
  67       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  68          return FALSE;
  69       break;
  70    default:
  71       break;
  72    }
  73
  74    /* transfers & shared are always supported */
  75    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  76                  PIPE_BIND_TRANSFER_WRITE |
  77                  PIPE_BIND_SHARED);
  78
  79    return (nv50_format_table[format].usage & bindings) == bindings;
  80 }
  81
  82 static int
  83 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  84 {
  85    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  86
  87    switch (param) {
  88    /* non-boolean caps */
  89    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  90       return 14;
  91    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  92       return 12;
  93    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  94       return 14;
  95    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  96       return 512;
  97    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  98    case PIPE_CAP_MIN_TEXEL_OFFSET:
  99       return -8;
 100    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 101    case PIPE_CAP_MAX_TEXEL_OFFSET:
 102       return 7;
 103    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 104       return 65536;
 105    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 106       return 330;
 107    case PIPE_CAP_MAX_RENDER_TARGETS:
 108       return 8;
 109    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 110       return 1;
 111    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 112       return 4;
 113    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 114    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 115       return 64;
 116    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 117    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 118       return 1024;
 119    case PIPE_CAP_MAX_VERTEX_STREAMS:
 120       return 1;
 121    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 122       return 256;
 123    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 124       return 1; /* 256 for binding as RT, but that's not possible in GL */
 125    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 126       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 127    case PIPE_CAP_MAX_VIEWPORTS:
 128       return NV50_MAX_VIEWPORTS;
 129    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 130       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 131    case PIPE_CAP_ENDIANNESS:
 132       return PIPE_ENDIAN_LITTLE;
 133    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 134       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 135
 136    /* supported caps */
 137    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 138    case PIPE_CAP_TEXTURE_SWIZZLE:
 139    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 140    case PIPE_CAP_NPOT_TEXTURES:
 141    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 142    case PIPE_CAP_ANISOTROPIC_FILTER:
 143    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 144    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 145    case PIPE_CAP_TWO_SIDED_STENCIL:
 146    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 147    case PIPE_CAP_POINT_SPRITE:
 148    case PIPE_CAP_SM3:
 149    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 150    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 151    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 152    case PIPE_CAP_QUERY_TIMESTAMP:
 153    case PIPE_CAP_QUERY_TIME_ELAPSED:
 154    case PIPE_CAP_OCCLUSION_QUERY:
 155    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 156    case PIPE_CAP_INDEP_BLEND_ENABLE:
 157    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 158    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 159    case PIPE_CAP_PRIMITIVE_RESTART:
 160    case PIPE_CAP_TGSI_INSTANCEID:
 161    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 162    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 163    case PIPE_CAP_CONDITIONAL_RENDER:
 164    case PIPE_CAP_TEXTURE_BARRIER:
 165    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 166    case PIPE_CAP_START_INSTANCE:
 167    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 168    case PIPE_CAP_USER_INDEX_BUFFERS:
 169    case PIPE_CAP_USER_VERTEX_BUFFERS:
 170    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 171    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 172       return 1;
 173    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 174       return 1; /* class_3d >= NVA0_3D_CLASS; */
 175    /* supported on nva0+ */
 176    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 177       return class_3d >= NVA0_3D_CLASS;
 178    /* supported on nva3+ */
 179    case PIPE_CAP_CUBE_MAP_ARRAY:
 180    case PIPE_CAP_INDEP_BLEND_FUNC:
 181    case PIPE_CAP_TEXTURE_QUERY_LOD:
 182    case PIPE_CAP_SAMPLE_SHADING:
 183       return class_3d >= NVA3_3D_CLASS;
 184
 185    /* unsupported caps */
 186    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 187    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 188    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 189    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 190    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 191    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 192    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 193    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 194    case PIPE_CAP_TGSI_TEXCOORD:
 195    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 196    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 197    case PIPE_CAP_TEXTURE_GATHER_SM5:
 198    case PIPE_CAP_FAKE_SW_MSAA:
 199    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 200    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 201    case PIPE_CAP_COMPUTE:
 202    case PIPE_CAP_DRAW_INDIRECT:
 203    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 204       return 0;
 205    }
 206
 207    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 208    return 0;
 209 }
 210
 211 static int
 212 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 213                              enum pipe_shader_cap param)
 214 {
 215    switch (shader) {
 216    case PIPE_SHADER_VERTEX:
 217    case PIPE_SHADER_GEOMETRY:
 218    case PIPE_SHADER_FRAGMENT:
 219       break;
 220    default:
 221       return 0;
 222    }
 223
 224    switch (param) {
 225    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 226    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 227    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 228    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 229       return 16384;
 230    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 231       return 4;
 232    case PIPE_SHADER_CAP_MAX_INPUTS:
 233       if (shader == PIPE_SHADER_VERTEX)
 234          return 32;
 235       return 15;
 236    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 237       return 65536;
 238    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 239       return NV50_MAX_PIPE_CONSTBUFS;
 240    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 241    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 242       return shader != PIPE_SHADER_FRAGMENT;
 243    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 244    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 245       return 1;
 246    case PIPE_SHADER_CAP_MAX_PREDS:
 247       return 0;
 248    case PIPE_SHADER_CAP_MAX_TEMPS:
 249       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 250    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 251       return 1;
 252    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 253       return 0;
 254    case PIPE_SHADER_CAP_SUBROUTINES:
 255       return 0; /* please inline, or provide function declarations */
 256    case PIPE_SHADER_CAP_INTEGERS:
 257       return 1;
 258    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 259       /* The chip could handle more sampler views than samplers */
 260    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 261       return MIN2(32, PIPE_MAX_SAMPLERS);
 262    default:
 263       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 264       return 0;
 265    }
 266 }
 267
 268 static float
 269 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 270 {
 271    switch (param) {
 272    case PIPE_CAPF_MAX_LINE_WIDTH:
 273    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 274       return 10.0f;
 275    case PIPE_CAPF_MAX_POINT_WIDTH:
 276    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 277       return 64.0f;
 278    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 279       return 16.0f;
 280    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 281       return 4.0f;
 282    case PIPE_CAPF_GUARD_BAND_LEFT:
 283    case PIPE_CAPF_GUARD_BAND_TOP:
 284       return 0.0f;
 285    case PIPE_CAPF_GUARD_BAND_RIGHT:
 286    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 287       return 0.0f; /* that or infinity */
 288    }
 289
 290    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 291    return 0.0f;
 292 }
 293
 294 static void
 295 nv50_screen_destroy(struct pipe_screen *pscreen)
 296 {
 297    struct nv50_screen *screen = nv50_screen(pscreen);
 298
 299    if (!nouveau_drm_screen_unref(&screen->base))
 300       return;
 301
 302    if (screen->base.fence.current) {
 303       struct nouveau_fence *current = NULL;
 304
 305       /* nouveau_fence_wait will create a new current fence, so wait on the
 306        * _current_ one, and remove both.
 307        */
 308       nouveau_fence_ref(screen->base.fence.current, &current);
 309       nouveau_fence_wait(current);
 310       nouveau_fence_ref(NULL, &current);
 311       nouveau_fence_ref(NULL, &screen->base.fence.current);
 312    }
 313    if (screen->base.pushbuf)
 314       screen->base.pushbuf->user_priv = NULL;
 315
 316    if (screen->blitter)
 317       nv50_blitter_destroy(screen);
 318
 319    nouveau_bo_ref(NULL, &screen->code);
 320    nouveau_bo_ref(NULL, &screen->tls_bo);
 321    nouveau_bo_ref(NULL, &screen->stack_bo);
 322    nouveau_bo_ref(NULL, &screen->txc);
 323    nouveau_bo_ref(NULL, &screen->uniforms);
 324    nouveau_bo_ref(NULL, &screen->fence.bo);
 325
 326    nouveau_heap_destroy(&screen->vp_code_heap);
 327    nouveau_heap_destroy(&screen->gp_code_heap);
 328    nouveau_heap_destroy(&screen->fp_code_heap);
 329
 330    FREE(screen->tic.entries);
 331
 332    nouveau_object_del(&screen->tesla);
 333    nouveau_object_del(&screen->eng2d);
 334    nouveau_object_del(&screen->m2mf);
 335    nouveau_object_del(&screen->sync);
 336
 337    nouveau_screen_fini(&screen->base);
 338
 339    FREE(screen);
 340 }
 341
 342 static void
 343 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 344 {
 345    struct nv50_screen *screen = nv50_screen(pscreen);
 346    struct nouveau_pushbuf *push = screen->base.pushbuf;
 347
 348    /* we need to do it after possible flush in MARK_RING */
 349    *sequence = ++screen->base.fence.sequence;
 350
 351    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 352    PUSH_DATAh(push, screen->fence.bo->offset);
 353    PUSH_DATA (push, screen->fence.bo->offset);
 354    PUSH_DATA (push, *sequence);
 355    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 356                     NV50_3D_QUERY_GET_UNK4 |
 357                     NV50_3D_QUERY_GET_UNIT_CROP |
 358                     NV50_3D_QUERY_GET_TYPE_QUERY |
 359                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 360                     NV50_3D_QUERY_GET_SHORT);
 361 }
 362
 363 static u32
 364 nv50_screen_fence_update(struct pipe_screen *pscreen)
 365 {
 366    return nv50_screen(pscreen)->fence.map[0];
 367 }
 368
 369 static void
 370 nv50_screen_init_hwctx(struct nv50_screen *screen)
 371 {
 372    struct nouveau_pushbuf *push = screen->base.pushbuf;
 373    struct nv04_fifo *fifo;
 374    unsigned i;
 375
 376    fifo = (struct nv04_fifo *)screen->base.channel->data;
 377
 378    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 379    PUSH_DATA (push, screen->m2mf->handle);
 380    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 381    PUSH_DATA (push, screen->sync->handle);
 382    PUSH_DATA (push, fifo->vram);
 383    PUSH_DATA (push, fifo->vram);
 384
 385    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 386    PUSH_DATA (push, screen->eng2d->handle);
 387    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 388    PUSH_DATA (push, screen->sync->handle);
 389    PUSH_DATA (push, fifo->vram);
 390    PUSH_DATA (push, fifo->vram);
 391    PUSH_DATA (push, fifo->vram);
 392    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 393    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 394    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 395    PUSH_DATA (push, 0);
 396    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 397    PUSH_DATA (push, 0);
 398    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 399    PUSH_DATA (push, 1);
 400    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 401    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 402
 403    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 404    PUSH_DATA (push, screen->tesla->handle);
 405
 406    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 407    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 408
 409    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 410    PUSH_DATA (push, screen->sync->handle);
 411    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 412    for (i = 0; i < 11; ++i)
 413       PUSH_DATA(push, fifo->vram);
 414    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 415    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 416       PUSH_DATA(push, fifo->vram);
 417
 418    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 419    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 420    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 421    PUSH_DATA (push, 0xf);
 422
 423    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 424       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 425       PUSH_DATA (push, 0x18);
 426    }
 427
 428    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 429    PUSH_DATA (push, 1);
 430
 431    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 432    PUSH_DATA (push, 0);
 433    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 434    PUSH_DATA (push, 0);
 435    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 436    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 437    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 438    PUSH_DATA (push, 0);
 439    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 440    PUSH_DATA (push, 1);
 441    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 442    PUSH_DATA (push, 0);
 443    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 444    PUSH_DATA (push, 1);
 445
 446    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 447       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 448       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 449    }
 450
 451    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 452    PUSH_DATA (push, 0);
 453    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 454    PUSH_DATA (push, 0);
 455    PUSH_DATA (push, 0);
 456    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 457    PUSH_DATA (push, 0x3f);
 458
 459    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 460    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 461    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 462
 463    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 464    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 465    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 466
 467    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 468    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 469    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 470
 471    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 472    PUSH_DATAh(push, screen->tls_bo->offset);
 473    PUSH_DATA (push, screen->tls_bo->offset);
 474    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 475
 476    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 477    PUSH_DATAh(push, screen->stack_bo->offset);
 478    PUSH_DATA (push, screen->stack_bo->offset);
 479    PUSH_DATA (push, 4);
 480
 481    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 482    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 483    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 484    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 485
 486    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 487    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 488    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 489    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 490
 491    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 492    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 493    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 494    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 495
 496    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 497    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 498    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 499    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 500
 501    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 502    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 503    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 504    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 505
 506    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 507    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 508    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 509    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 510    PUSH_DATAf(push, 0.0f);
 511    PUSH_DATAf(push, 0.0f);
 512    PUSH_DATAf(push, 0.0f);
 513    PUSH_DATAf(push, 0.0f);
 514    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 515    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 516    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 517
 518    nv50_upload_ms_info(push);
 519
 520    /* max TIC (bits 4:8) & TSC bindings, per program type */
 521    for (i = 0; i < 3; ++i) {
 522       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 523       PUSH_DATA (push, 0x54);
 524    }
 525
 526    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 527    PUSH_DATAh(push, screen->txc->offset);
 528    PUSH_DATA (push, screen->txc->offset);
 529    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 530
 531    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 532    PUSH_DATAh(push, screen->txc->offset + 65536);
 533    PUSH_DATA (push, screen->txc->offset + 65536);
 534    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 535
 536    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 537    PUSH_DATA (push, 0);
 538
 539    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 540    PUSH_DATA (push, 0);
 541    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 542    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 543    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 544    for (i = 0; i < 8 * 2; ++i)
 545       PUSH_DATA(push, 0);
 546    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 547    PUSH_DATA (push, 0);
 548
 549    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 550    PUSH_DATA (push, 1);
 551    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 552       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 553       PUSH_DATAf(push, 0.0f);
 554       PUSH_DATAf(push, 1.0f);
 555       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 556       PUSH_DATA (push, 8192 << 16);
 557       PUSH_DATA (push, 8192 << 16);
 558    }
 559
 560    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 561 #ifdef NV50_SCISSORS_CLIPPING
 562    PUSH_DATA (push, 0x0000);
 563 #else
 564    PUSH_DATA (push, 0x1080);
 565 #endif
 566
 567    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 568    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 569
 570    /* We use scissors instead of exact view volume clipping,
 571     * so they're always enabled.
 572     */
 573    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 574       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 575       PUSH_DATA (push, 1);
 576       PUSH_DATA (push, 8192 << 16);
 577       PUSH_DATA (push, 8192 << 16);
 578    }
 579
 580    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 581    PUSH_DATA (push, 1);
 582    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 583    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 584    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 585    PUSH_DATA (push, 0x11111111);
 586    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 587    PUSH_DATA (push, 1);
 588
 589    PUSH_KICK (push);
 590 }
 591
 592 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 593       uint64_t *tls_size)
 594 {
 595    struct nouveau_device *dev = screen->base.device;
 596    int ret;
 597
 598    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 599          ONE_TEMP_SIZE;
 600    if (nouveau_mesa_debug)
 601       debug_printf("allocating space for %u temps\n",
 602             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 603    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 604          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 605
 606    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 607                         *tls_size, NULL, &screen->tls_bo);
 608    if (ret) {
 609       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 610       return ret;
 611    }
 612
 613    return 0;
 614 }
 615
 616 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 617 {
 618    struct nouveau_pushbuf *push = screen->base.pushbuf;
 619    int ret;
 620    uint64_t tls_size;
 621
 622    if (tls_space < screen->cur_tls_space)
 623       return 0;
 624    if (tls_space > screen->max_tls_space) {
 625       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 626        * LOCAL_WARPS_NO_CLAMP) */
 627       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 628             (unsigned)(tls_space / ONE_TEMP_SIZE),
 629             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 630       return -ENOMEM;
 631    }
 632
 633    nouveau_bo_ref(NULL, &screen->tls_bo);
 634    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 635    if (ret)
 636       return ret;
 637
 638    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 639    PUSH_DATAh(push, screen->tls_bo->offset);
 640    PUSH_DATA (push, screen->tls_bo->offset);
 641    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 642
 643    return 1;
 644 }
 645
 646 struct pipe_screen *
 647 nv50_screen_create(struct nouveau_device *dev)
 648 {
 649    struct nv50_screen *screen;
 650    struct pipe_screen *pscreen;
 651    struct nouveau_object *chan;
 652    uint64_t value;
 653    uint32_t tesla_class;
 654    unsigned stack_size;
 655    int ret;
 656
 657    screen = CALLOC_STRUCT(nv50_screen);
 658    if (!screen)
 659       return NULL;
 660    pscreen = &screen->base.base;
 661
 662    ret = nouveau_screen_init(&screen->base, dev);
 663    if (ret) {
 664       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 665       goto fail;
 666    }
 667
 668    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 669     *  admit them to VRAM.
 670     */
 671    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 672       PIPE_BIND_VERTEX_BUFFER;
 673    screen->base.sysmem_bindings |=
 674       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 675
 676    screen->base.pushbuf->user_priv = screen;
 677    screen->base.pushbuf->rsvd_kick = 5;
 678
 679    chan = screen->base.channel;
 680
 681    pscreen->destroy = nv50_screen_destroy;
 682    pscreen->context_create = nv50_create;
 683    pscreen->is_format_supported = nv50_screen_is_format_supported;
 684    pscreen->get_param = nv50_screen_get_param;
 685    pscreen->get_shader_param = nv50_screen_get_shader_param;
 686    pscreen->get_paramf = nv50_screen_get_paramf;
 687
 688    nv50_screen_init_resource_functions(pscreen);
 689
 690    if (screen->base.device->chipset < 0x84 ||
 691        debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
 692       /* PMPEG */
 693       nouveau_screen_init_vdec(&screen->base);
 694    } else if (screen->base.device->chipset < 0x98 ||
 695               screen->base.device->chipset == 0xa0) {
 696       /* VP2 */
 697       screen->base.base.get_video_param = nv84_screen_get_video_param;
 698       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 699    } else {
 700       /* VP3/4 */
 701       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 702       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 703    }
 704
 705    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 706                         NULL, &screen->fence.bo);
 707    if (ret) {
 708       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 709       goto fail;
 710    }
 711
 712    nouveau_bo_map(screen->fence.bo, 0, NULL);
 713    screen->fence.map = screen->fence.bo->map;
 714    screen->base.fence.emit = nv50_screen_fence_emit;
 715    screen->base.fence.update = nv50_screen_fence_update;
 716
 717    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 718                             &(struct nv04_notify){ .length = 32 },
 719                             sizeof(struct nv04_notify), &screen->sync);
 720    if (ret) {
 721       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 722       goto fail;
 723    }
 724
 725    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 726                             NULL, 0, &screen->m2mf);
 727    if (ret) {
 728       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 729       goto fail;
 730    }
 731
 732    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 733                             NULL, 0, &screen->eng2d);
 734    if (ret) {
 735       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 736       goto fail;
 737    }
 738
 739    switch (dev->chipset & 0xf0) {
 740    case 0x50:
 741       tesla_class = NV50_3D_CLASS;
 742       break;
 743    case 0x80:
 744    case 0x90:
 745       tesla_class = NV84_3D_CLASS;
 746       break;
 747    case 0xa0:
 748       switch (dev->chipset) {
 749       case 0xa0:
 750       case 0xaa:
 751       case 0xac:
 752          tesla_class = NVA0_3D_CLASS;
 753          break;
 754       case 0xaf:
 755          tesla_class = NVAF_3D_CLASS;
 756          break;
 757       default:
 758          tesla_class = NVA3_3D_CLASS;
 759          break;
 760       }
 761       break;
 762    default:
 763       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 764       goto fail;
 765    }
 766    screen->base.class_3d = tesla_class;
 767
 768    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 769                             NULL, 0, &screen->tesla);
 770    if (ret) {
 771       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 772       goto fail;
 773    }
 774
 775    /* This over-allocates by a page. The GP, which would execute at the end of
 776     * the last page, would trigger faults. The going theory is that it
 777     * prefetches up to a certain amount.
 778     */
 779    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 780                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 781                         NULL, &screen->code);
 782    if (ret) {
 783       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 784       goto fail;
 785    }
 786
 787    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 788    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 789    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 790
 791    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 792
 793    screen->TPs = util_bitcount(value & 0xffff);
 794    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 795
 796    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 797          STACK_WARPS_ALLOC * 64 * 8;
 798
 799    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 800                         &screen->stack_bo);
 801    if (ret) {
 802       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 803       goto fail;
 804    }
 805
 806    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 807          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 808          ONE_TEMP_SIZE;
 809    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 810    screen->max_tls_space /= 2; /* half of vram */
 811
 812    /* hw can address max 64 KiB */
 813    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 814
 815    uint64_t tls_size;
 816    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 817    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 818    if (ret)
 819       goto fail;
 820
 821    if (nouveau_mesa_debug)
 822       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 823             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 824
 825    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 826                         &screen->uniforms);
 827    if (ret) {
 828       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 829       goto fail;
 830    }
 831
 832    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 833                         &screen->txc);
 834    if (ret) {
 835       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 836       goto fail;
 837    }
 838
 839    screen->tic.entries = CALLOC(4096, sizeof(void *));
 840    screen->tsc.entries = screen->tic.entries + 2048;
 841
 842    if (!nv50_blitter_create(screen))
 843       goto fail;
 844
 845    nv50_screen_init_hwctx(screen);
 846
 847    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 848
 849    return pscreen;
 850
 851 fail:
 852    nv50_screen_destroy(pscreen);
 853    return NULL;
 854 }
 855
 856 int
 857 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 858 {
 859    int i = screen->tic.next;
 860
 861    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 862       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 863
 864    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 865
 866    if (screen->tic.entries[i])
 867       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 868
 869    screen->tic.entries[i] = entry;
 870    return i;
 871 }
 872
 873 int
 874 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 875 {
 876    int i = screen->tsc.next;
 877
 878    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 879       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 880
 881    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 882
 883    if (screen->tsc.entries[i])
 884       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 885
 886    screen->tsc.entries[i] = entry;
 887    return i;
 888 }