src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned storage_sample_count,
  50                                 unsigned bindings)
  51 {
  52    if (sample_count > 8)
  53       return false;
  54    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  55       return false;
  56    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  57       return false;
  58
  59    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  60       return false;
  61
  62    switch (format) {
  63    case PIPE_FORMAT_Z16_UNORM:
  64       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  65          return false;
  66       break;
  67    default:
  68       break;
  69    }
  70
  71    if (bindings & PIPE_BIND_LINEAR)
  72       if (util_format_is_depth_or_stencil(format) ||
  73           (target != PIPE_TEXTURE_1D &&
  74            target != PIPE_TEXTURE_2D &&
  75            target != PIPE_TEXTURE_RECT) ||
  76           sample_count > 1)
  77          return false;
  78
  79    /* shared is always supported */
  80    bindings &= ~(PIPE_BIND_LINEAR |
  81                  PIPE_BIND_SHARED);
  82
  83    return (( nv50_format_table[format].usage |
  84             nv50_vertex_format[format].usage) & bindings) == bindings;
  85 }
  86
  87 static int
  88 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  89 {
  90    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  91    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  92
  93    switch (param) {
  94    /* non-boolean caps */
  95    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  96       return 14;
  97    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  98       return 12;
  99    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 100       return 14;
 101    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 102       return 512;
 103    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 104    case PIPE_CAP_MIN_TEXEL_OFFSET:
 105       return -8;
 106    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 107    case PIPE_CAP_MAX_TEXEL_OFFSET:
 108       return 7;
 109    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 110       return 128 * 1024 * 1024;
 111    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 112       return 330;
 113    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 114       return 140;
 115    case PIPE_CAP_MAX_RENDER_TARGETS:
 116       return 8;
 117    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 118       return 1;
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 120       return 4;
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 122    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 123       return 64;
 124    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 125    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 126       return 1024;
 127    case PIPE_CAP_MAX_VERTEX_STREAMS:
 128       return 1;
 129    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 130       return 2048;
 131    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 132       return 256;
 133    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 134       return 16; /* 256 for binding as RT, but that's not possible in GL */
 135    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 136       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 137    case PIPE_CAP_MAX_VIEWPORTS:
 138       return NV50_MAX_VIEWPORTS;
 139    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 140       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 141    case PIPE_CAP_ENDIANNESS:
 142       return PIPE_ENDIAN_LITTLE;
 143    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 144       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 145    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 146       return NV50_MAX_WINDOW_RECTANGLES;
 147
 148    /* supported caps */
 149    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 150    case PIPE_CAP_TEXTURE_SWIZZLE:
 151    case PIPE_CAP_NPOT_TEXTURES:
 152    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 153    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 154    case PIPE_CAP_ANISOTROPIC_FILTER:
 155    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 156    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 157    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 158    case PIPE_CAP_POINT_SPRITE:
 159    case PIPE_CAP_SM3:
 160    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 161    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 162    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 163    case PIPE_CAP_QUERY_TIMESTAMP:
 164    case PIPE_CAP_QUERY_TIME_ELAPSED:
 165    case PIPE_CAP_OCCLUSION_QUERY:
 166    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 167    case PIPE_CAP_INDEP_BLEND_ENABLE:
 168    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 169    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 170    case PIPE_CAP_PRIMITIVE_RESTART:
 171    case PIPE_CAP_TGSI_INSTANCEID:
 172    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 173    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 174    case PIPE_CAP_CONDITIONAL_RENDER:
 175    case PIPE_CAP_TEXTURE_BARRIER:
 176    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 177    case PIPE_CAP_START_INSTANCE:
 178    case PIPE_CAP_USER_VERTEX_BUFFERS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 181    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 182    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 183    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 184    case PIPE_CAP_CLIP_HALFZ:
 185    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 186    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 187    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 188    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 189    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 190    case PIPE_CAP_TGSI_TXQS:
 191    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 192    case PIPE_CAP_SHAREABLE_SHADERS:
 193    case PIPE_CAP_CLEAR_TEXTURE:
 194    case PIPE_CAP_COMPUTE:
 195    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 196    case PIPE_CAP_INVALIDATE_BUFFER:
 197    case PIPE_CAP_STRING_MARKER:
 198    case PIPE_CAP_CULL_DISTANCE:
 199    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 200    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 201    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 202    case PIPE_CAP_TGSI_CLOCK:
 203    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 204    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 205       return 1;
 206    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 207       return 1; /* class_3d >= NVA0_3D_CLASS; */
 208    /* supported on nva0+ */
 209    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 210       return class_3d >= NVA0_3D_CLASS;
 211    /* supported on nva3+ */
 212    case PIPE_CAP_CUBE_MAP_ARRAY:
 213    case PIPE_CAP_INDEP_BLEND_FUNC:
 214    case PIPE_CAP_TEXTURE_QUERY_LOD:
 215    case PIPE_CAP_SAMPLE_SHADING:
 216    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 217       return class_3d >= NVA3_3D_CLASS;
 218
 219    /* unsupported caps */
 220    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 221    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 222    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 223    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 224    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 225    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 226    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 227    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 228    case PIPE_CAP_TGSI_TEXCOORD:
 229    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 230    case PIPE_CAP_TEXTURE_GATHER_SM5:
 231    case PIPE_CAP_FAKE_SW_MSAA:
 232    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 233    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 234    case PIPE_CAP_DRAW_INDIRECT:
 235    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 236    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 237    case PIPE_CAP_VERTEXID_NOBASE:
 238    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 239    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 240    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 241    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 242    case PIPE_CAP_DRAW_PARAMETERS:
 243    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 244    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 245    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 246    case PIPE_CAP_GENERATE_MIPMAP:
 247    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 248    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 249    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 250    case PIPE_CAP_QUERY_MEMORY_INFO:
 251    case PIPE_CAP_PCI_GROUP:
 252    case PIPE_CAP_PCI_BUS:
 253    case PIPE_CAP_PCI_DEVICE:
 254    case PIPE_CAP_PCI_FUNCTION:
 255    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 256    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 257    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 258    case PIPE_CAP_TGSI_VOTE:
 259    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 260    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 261    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 262    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 263    case PIPE_CAP_NATIVE_FENCE_FD:
 264    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 265    case PIPE_CAP_TGSI_FS_FBFETCH:
 266    case PIPE_CAP_DOUBLES:
 267    case PIPE_CAP_INT64:
 268    case PIPE_CAP_INT64_DIVMOD:
 269    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 270    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 271    case PIPE_CAP_TGSI_BALLOT:
 272    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 273    case PIPE_CAP_POST_DEPTH_COVERAGE:
 274    case PIPE_CAP_BINDLESS_TEXTURE:
 275    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 276    case PIPE_CAP_QUERY_SO_OVERFLOW:
 277    case PIPE_CAP_MEMOBJ:
 278    case PIPE_CAP_LOAD_CONSTBUF:
 279    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 280    case PIPE_CAP_TILE_RASTER_ORDER:
 281    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 282    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 283    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 284    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 285    case PIPE_CAP_FENCE_SIGNAL:
 286    case PIPE_CAP_CONSTBUF0_FLAGS:
 287    case PIPE_CAP_PACKED_UNIFORMS:
 288    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 289    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 290    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 291    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 292    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 293    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 294    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 295       return 0;
 296
 297    case PIPE_CAP_VENDOR_ID:
 298       return 0x10de;
 299    case PIPE_CAP_DEVICE_ID: {
 300       uint64_t device_id;
 301       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 302          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 303          return -1;
 304       }
 305       return device_id;
 306    }
 307    case PIPE_CAP_ACCELERATED:
 308       return 1;
 309    case PIPE_CAP_VIDEO_MEMORY:
 310       return dev->vram_size >> 20;
 311    case PIPE_CAP_UMA:
 312       return 0;
 313    }
 314
 315    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 316    return 0;
 317 }
 318
 319 static int
 320 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 321                              enum pipe_shader_type shader,
 322                              enum pipe_shader_cap param)
 323 {
 324    switch (shader) {
 325    case PIPE_SHADER_VERTEX:
 326    case PIPE_SHADER_GEOMETRY:
 327    case PIPE_SHADER_FRAGMENT:
 328       break;
 329    case PIPE_SHADER_COMPUTE:
 330    default:
 331       return 0;
 332    }
 333
 334    switch (param) {
 335    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 336    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 337    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 338    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 339       return 16384;
 340    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 341       return 4;
 342    case PIPE_SHADER_CAP_MAX_INPUTS:
 343       if (shader == PIPE_SHADER_VERTEX)
 344          return 32;
 345       return 15;
 346    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 347       return 16;
 348    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 349       return 65536;
 350    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 351       return NV50_MAX_PIPE_CONSTBUFS;
 352    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 353       return shader != PIPE_SHADER_FRAGMENT;
 354    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 355    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 356    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 357       return 1;
 358    case PIPE_SHADER_CAP_MAX_TEMPS:
 359       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 360    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 361       return 1;
 362    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 363       return 1;
 364    case PIPE_SHADER_CAP_INT64_ATOMICS:
 365    case PIPE_SHADER_CAP_FP16:
 366    case PIPE_SHADER_CAP_SUBROUTINES:
 367       return 0; /* please inline, or provide function declarations */
 368    case PIPE_SHADER_CAP_INTEGERS:
 369       return 1;
 370    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 371       return 1;
 372    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 373       /* The chip could handle more sampler views than samplers */
 374    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 375       return MIN2(16, PIPE_MAX_SAMPLERS);
 376    case PIPE_SHADER_CAP_PREFERRED_IR:
 377       return PIPE_SHADER_IR_TGSI;
 378    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 379       return 32;
 380    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 381    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 382    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 383    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 384    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 385    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 386    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 387    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 388    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 389    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 390    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 391       return 0;
 392    case PIPE_SHADER_CAP_SCALAR_ISA:
 393       return 1;
 394    default:
 395       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 396       return 0;
 397    }
 398 }
 399
 400 static float
 401 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 402 {
 403    switch (param) {
 404    case PIPE_CAPF_MAX_LINE_WIDTH:
 405    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 406       return 10.0f;
 407    case PIPE_CAPF_MAX_POINT_WIDTH:
 408    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 409       return 64.0f;
 410    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 411       return 16.0f;
 412    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 413       return 4.0f;
 414    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 415    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 416    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 417       return 0.0f;
 418    }
 419
 420    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 421    return 0.0f;
 422 }
 423
 424 static int
 425 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 426                               enum pipe_shader_ir ir_type,
 427                               enum pipe_compute_cap param, void *data)
 428 {
 429    struct nv50_screen *screen = nv50_screen(pscreen);
 430
 431 #define RET(x) do {                  \
 432    if (data)                         \
 433       memcpy(data, x, sizeof(x));    \
 434    return sizeof(x);                 \
 435 } while (0)
 436
 437    switch (param) {
 438    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 439       RET((uint64_t []) { 2 });
 440    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 441       RET(((uint64_t []) { 65535, 65535 }));
 442    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 443       RET(((uint64_t []) { 512, 512, 64 }));
 444    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 445       RET((uint64_t []) { 512 });
 446    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 447       RET((uint64_t []) { 1ULL << 32 });
 448    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 449       RET((uint64_t []) { 16 << 10 });
 450    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 451       RET((uint64_t []) { 16 << 10 });
 452    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 453       RET((uint64_t []) { 4096 });
 454    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 455       RET((uint32_t []) { 32 });
 456    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 457       RET((uint64_t []) { 1ULL << 40 });
 458    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 459       RET((uint32_t []) { 0 });
 460    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 461       RET((uint32_t []) { screen->mp_count });
 462    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 463       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 464    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 465       RET((uint32_t []) { 32 });
 466    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 467       RET((uint64_t []) { 0 });
 468    default:
 469       return 0;
 470    }
 471
 472 #undef RET
 473 }
 474
 475 static void
 476 nv50_screen_destroy(struct pipe_screen *pscreen)
 477 {
 478    struct nv50_screen *screen = nv50_screen(pscreen);
 479
 480    if (!nouveau_drm_screen_unref(&screen->base))
 481       return;
 482
 483    if (screen->base.fence.current) {
 484       struct nouveau_fence *current = NULL;
 485
 486       /* nouveau_fence_wait will create a new current fence, so wait on the
 487        * _current_ one, and remove both.
 488        */
 489       nouveau_fence_ref(screen->base.fence.current, &current);
 490       nouveau_fence_wait(current, NULL);
 491       nouveau_fence_ref(NULL, &current);
 492       nouveau_fence_ref(NULL, &screen->base.fence.current);
 493    }
 494    if (screen->base.pushbuf)
 495       screen->base.pushbuf->user_priv = NULL;
 496
 497    if (screen->blitter)
 498       nv50_blitter_destroy(screen);
 499    if (screen->pm.prog) {
 500       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 501       nv50_program_destroy(NULL, screen->pm.prog);
 502       FREE(screen->pm.prog);
 503    }
 504
 505    nouveau_bo_ref(NULL, &screen->code);
 506    nouveau_bo_ref(NULL, &screen->tls_bo);
 507    nouveau_bo_ref(NULL, &screen->stack_bo);
 508    nouveau_bo_ref(NULL, &screen->txc);
 509    nouveau_bo_ref(NULL, &screen->uniforms);
 510    nouveau_bo_ref(NULL, &screen->fence.bo);
 511
 512    nouveau_heap_destroy(&screen->vp_code_heap);
 513    nouveau_heap_destroy(&screen->gp_code_heap);
 514    nouveau_heap_destroy(&screen->fp_code_heap);
 515
 516    FREE(screen->tic.entries);
 517
 518    nouveau_object_del(&screen->tesla);
 519    nouveau_object_del(&screen->eng2d);
 520    nouveau_object_del(&screen->m2mf);
 521    nouveau_object_del(&screen->compute);
 522    nouveau_object_del(&screen->sync);
 523
 524    nouveau_screen_fini(&screen->base);
 525
 526    FREE(screen);
 527 }
 528
 529 static void
 530 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 531 {
 532    struct nv50_screen *screen = nv50_screen(pscreen);
 533    struct nouveau_pushbuf *push = screen->base.pushbuf;
 534
 535    /* we need to do it after possible flush in MARK_RING */
 536    *sequence = ++screen->base.fence.sequence;
 537
 538    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 539    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 540    PUSH_DATAh(push, screen->fence.bo->offset);
 541    PUSH_DATA (push, screen->fence.bo->offset);
 542    PUSH_DATA (push, *sequence);
 543    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 544                     NV50_3D_QUERY_GET_UNK4 |
 545                     NV50_3D_QUERY_GET_UNIT_CROP |
 546                     NV50_3D_QUERY_GET_TYPE_QUERY |
 547                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 548                     NV50_3D_QUERY_GET_SHORT);
 549 }
 550
 551 static u32
 552 nv50_screen_fence_update(struct pipe_screen *pscreen)
 553 {
 554    return nv50_screen(pscreen)->fence.map[0];
 555 }
 556
 557 static void
 558 nv50_screen_init_hwctx(struct nv50_screen *screen)
 559 {
 560    struct nouveau_pushbuf *push = screen->base.pushbuf;
 561    struct nv04_fifo *fifo;
 562    unsigned i;
 563
 564    fifo = (struct nv04_fifo *)screen->base.channel->data;
 565
 566    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 567    PUSH_DATA (push, screen->m2mf->handle);
 568    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 569    PUSH_DATA (push, screen->sync->handle);
 570    PUSH_DATA (push, fifo->vram);
 571    PUSH_DATA (push, fifo->vram);
 572
 573    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 574    PUSH_DATA (push, screen->eng2d->handle);
 575    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 576    PUSH_DATA (push, screen->sync->handle);
 577    PUSH_DATA (push, fifo->vram);
 578    PUSH_DATA (push, fifo->vram);
 579    PUSH_DATA (push, fifo->vram);
 580    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 581    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 582    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 583    PUSH_DATA (push, 0);
 584    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 585    PUSH_DATA (push, 0);
 586    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 587    PUSH_DATA (push, 1);
 588    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 589    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 590
 591    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 592    PUSH_DATA (push, screen->tesla->handle);
 593
 594    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 595    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 596
 597    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 598    PUSH_DATA (push, screen->sync->handle);
 599    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 600    for (i = 0; i < 11; ++i)
 601       PUSH_DATA(push, fifo->vram);
 602    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 603    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 604       PUSH_DATA(push, fifo->vram);
 605
 606    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 607    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 608    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 609    PUSH_DATA (push, 0xf);
 610
 611    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 612       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 613       PUSH_DATA (push, 0x18);
 614    }
 615
 616    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 617    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 618
 619    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 620    for (i = 0; i < 8; ++i)
 621       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 622
 623    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 624    PUSH_DATA (push, 1);
 625
 626    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 627    PUSH_DATA (push, 0);
 628    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 629    PUSH_DATA (push, 0);
 630    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 631    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 632    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 633    PUSH_DATA (push, 0);
 634    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 635    PUSH_DATA (push, 1);
 636    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 637    PUSH_DATA (push, 1);
 638
 639    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 640       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 641       PUSH_DATA (push, 0);
 642    }
 643
 644    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 645    PUSH_DATA (push, 0);
 646    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 647    PUSH_DATA (push, 0);
 648    PUSH_DATA (push, 0);
 649    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 650    PUSH_DATA (push, 0x3f);
 651
 652    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 653    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 654    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 655
 656    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 657    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 658    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 659
 660    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 661    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 662    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 663
 664    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 665    PUSH_DATAh(push, screen->tls_bo->offset);
 666    PUSH_DATA (push, screen->tls_bo->offset);
 667    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 668
 669    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 670    PUSH_DATAh(push, screen->stack_bo->offset);
 671    PUSH_DATA (push, screen->stack_bo->offset);
 672    PUSH_DATA (push, 4);
 673
 674    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 675    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 676    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 677    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 678
 679    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 680    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 681    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 682    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 683
 684    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 685    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 686    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 687    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 688
 689    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 690    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 691    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 692    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 693
 694    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 695    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 696    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 697    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 698
 699    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 700    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 701    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 702    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 703    PUSH_DATAf(push, 0.0f);
 704    PUSH_DATAf(push, 0.0f);
 705    PUSH_DATAf(push, 0.0f);
 706    PUSH_DATAf(push, 0.0f);
 707    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 708    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 709    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 710
 711    nv50_upload_ms_info(push);
 712
 713    /* max TIC (bits 4:8) & TSC bindings, per program type */
 714    for (i = 0; i < 3; ++i) {
 715       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 716       PUSH_DATA (push, 0x54);
 717    }
 718
 719    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 720    PUSH_DATAh(push, screen->txc->offset);
 721    PUSH_DATA (push, screen->txc->offset);
 722    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 723
 724    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 725    PUSH_DATAh(push, screen->txc->offset + 65536);
 726    PUSH_DATA (push, screen->txc->offset + 65536);
 727    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 728
 729    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 730    PUSH_DATA (push, 0);
 731
 732    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 733    PUSH_DATA (push, 0);
 734    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 735    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 736    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 737    for (i = 0; i < 8 * 2; ++i)
 738       PUSH_DATA(push, 0);
 739    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 740    PUSH_DATA (push, 0);
 741
 742    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 743    PUSH_DATA (push, 1);
 744    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 745       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 746       PUSH_DATAf(push, 0.0f);
 747       PUSH_DATAf(push, 1.0f);
 748       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 749       PUSH_DATA (push, 8192 << 16);
 750       PUSH_DATA (push, 8192 << 16);
 751    }
 752
 753    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 754 #ifdef NV50_SCISSORS_CLIPPING
 755    PUSH_DATA (push, 0x0000);
 756 #else
 757    PUSH_DATA (push, 0x1080);
 758 #endif
 759
 760    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 761    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 762
 763    /* We use scissors instead of exact view volume clipping,
 764     * so they're always enabled.
 765     */
 766    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 767       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 768       PUSH_DATA (push, 1);
 769       PUSH_DATA (push, 8192 << 16);
 770       PUSH_DATA (push, 8192 << 16);
 771    }
 772
 773    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 774    PUSH_DATA (push, 1);
 775    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 776    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 777    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 778    PUSH_DATA (push, 0x11111111);
 779    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 780    PUSH_DATA (push, 1);
 781
 782    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 783    PUSH_DATA (push, 0);
 784    if (screen->base.class_3d >= NV84_3D_CLASS) {
 785       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 786       PUSH_DATA (push, 0);
 787    }
 788
 789    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 790    PUSH_DATA (push, 1);
 791    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 792    PUSH_DATA (push, 1);
 793
 794    PUSH_KICK (push);
 795 }
 796
 797 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 798       uint64_t *tls_size)
 799 {
 800    struct nouveau_device *dev = screen->base.device;
 801    int ret;
 802
 803    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 804          ONE_TEMP_SIZE;
 805    if (nouveau_mesa_debug)
 806       debug_printf("allocating space for %u temps\n",
 807             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 808    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 809          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 810
 811    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 812                         *tls_size, NULL, &screen->tls_bo);
 813    if (ret) {
 814       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 815       return ret;
 816    }
 817
 818    return 0;
 819 }
 820
 821 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 822 {
 823    struct nouveau_pushbuf *push = screen->base.pushbuf;
 824    int ret;
 825    uint64_t tls_size;
 826
 827    if (tls_space < screen->cur_tls_space)
 828       return 0;
 829    if (tls_space > screen->max_tls_space) {
 830       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 831        * LOCAL_WARPS_NO_CLAMP) */
 832       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 833             (unsigned)(tls_space / ONE_TEMP_SIZE),
 834             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 835       return -ENOMEM;
 836    }
 837
 838    nouveau_bo_ref(NULL, &screen->tls_bo);
 839    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 840    if (ret)
 841       return ret;
 842
 843    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 844    PUSH_DATAh(push, screen->tls_bo->offset);
 845    PUSH_DATA (push, screen->tls_bo->offset);
 846    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 847
 848    return 1;
 849 }
 850
 851 struct nouveau_screen *
 852 nv50_screen_create(struct nouveau_device *dev)
 853 {
 854    struct nv50_screen *screen;
 855    struct pipe_screen *pscreen;
 856    struct nouveau_object *chan;
 857    uint64_t value;
 858    uint32_t tesla_class;
 859    unsigned stack_size;
 860    int ret;
 861
 862    screen = CALLOC_STRUCT(nv50_screen);
 863    if (!screen)
 864       return NULL;
 865    pscreen = &screen->base.base;
 866    pscreen->destroy = nv50_screen_destroy;
 867
 868    ret = nouveau_screen_init(&screen->base, dev);
 869    if (ret) {
 870       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 871       goto fail;
 872    }
 873
 874    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 875     *  admit them to VRAM.
 876     */
 877    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 878       PIPE_BIND_VERTEX_BUFFER;
 879    screen->base.sysmem_bindings |=
 880       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 881
 882    screen->base.pushbuf->user_priv = screen;
 883    screen->base.pushbuf->rsvd_kick = 5;
 884
 885    chan = screen->base.channel;
 886
 887    pscreen->context_create = nv50_create;
 888    pscreen->is_format_supported = nv50_screen_is_format_supported;
 889    pscreen->get_param = nv50_screen_get_param;
 890    pscreen->get_shader_param = nv50_screen_get_shader_param;
 891    pscreen->get_paramf = nv50_screen_get_paramf;
 892    pscreen->get_compute_param = nv50_screen_get_compute_param;
 893    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 894    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 895
 896    nv50_screen_init_resource_functions(pscreen);
 897
 898    if (screen->base.device->chipset < 0x84 ||
 899        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 900       /* PMPEG */
 901       nouveau_screen_init_vdec(&screen->base);
 902    } else if (screen->base.device->chipset < 0x98 ||
 903               screen->base.device->chipset == 0xa0) {
 904       /* VP2 */
 905       screen->base.base.get_video_param = nv84_screen_get_video_param;
 906       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 907    } else {
 908       /* VP3/4 */
 909       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 910       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 911    }
 912
 913    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 914                         NULL, &screen->fence.bo);
 915    if (ret) {
 916       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 917       goto fail;
 918    }
 919
 920    nouveau_bo_map(screen->fence.bo, 0, NULL);
 921    screen->fence.map = screen->fence.bo->map;
 922    screen->base.fence.emit = nv50_screen_fence_emit;
 923    screen->base.fence.update = nv50_screen_fence_update;
 924
 925    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 926                             &(struct nv04_notify){ .length = 32 },
 927                             sizeof(struct nv04_notify), &screen->sync);
 928    if (ret) {
 929       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 930       goto fail;
 931    }
 932
 933    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 934                             NULL, 0, &screen->m2mf);
 935    if (ret) {
 936       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 937       goto fail;
 938    }
 939
 940    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 941                             NULL, 0, &screen->eng2d);
 942    if (ret) {
 943       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 944       goto fail;
 945    }
 946
 947    switch (dev->chipset & 0xf0) {
 948    case 0x50:
 949       tesla_class = NV50_3D_CLASS;
 950       break;
 951    case 0x80:
 952    case 0x90:
 953       tesla_class = NV84_3D_CLASS;
 954       break;
 955    case 0xa0:
 956       switch (dev->chipset) {
 957       case 0xa0:
 958       case 0xaa:
 959       case 0xac:
 960          tesla_class = NVA0_3D_CLASS;
 961          break;
 962       case 0xaf:
 963          tesla_class = NVAF_3D_CLASS;
 964          break;
 965       default:
 966          tesla_class = NVA3_3D_CLASS;
 967          break;
 968       }
 969       break;
 970    default:
 971       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 972       goto fail;
 973    }
 974    screen->base.class_3d = tesla_class;
 975
 976    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 977                             NULL, 0, &screen->tesla);
 978    if (ret) {
 979       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 980       goto fail;
 981    }
 982
 983    /* This over-allocates by a page. The GP, which would execute at the end of
 984     * the last page, would trigger faults. The going theory is that it
 985     * prefetches up to a certain amount.
 986     */
 987    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 988                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 989                         NULL, &screen->code);
 990    if (ret) {
 991       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 992       goto fail;
 993    }
 994
 995    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 996    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 997    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 998
 999    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1000
1001    screen->TPs = util_bitcount(value & 0xffff);
1002    screen->MPsInTP = util_bitcount(value & 0x0f000000);
1003
1004    screen->mp_count = screen->TPs * screen->MPsInTP;
1005
1006    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1007          STACK_WARPS_ALLOC * 64 * 8;
1008
1009    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1010                         &screen->stack_bo);
1011    if (ret) {
1012       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1013       goto fail;
1014    }
1015
1016    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1017          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1018          ONE_TEMP_SIZE;
1019    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1020    screen->max_tls_space /= 2; /* half of vram */
1021
1022    /* hw can address max 64 KiB */
1023    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1024
1025    uint64_t tls_size;
1026    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1027    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1028    if (ret)
1029       goto fail;
1030
1031    if (nouveau_mesa_debug)
1032       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1033             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1034
1035    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1036                         &screen->uniforms);
1037    if (ret) {
1038       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1039       goto fail;
1040    }
1041
1042    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1043                         &screen->txc);
1044    if (ret) {
1045       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1046       goto fail;
1047    }
1048
1049    screen->tic.entries = CALLOC(4096, sizeof(void *));
1050    screen->tsc.entries = screen->tic.entries + 2048;
1051
1052    if (!nv50_blitter_create(screen))
1053       goto fail;
1054
1055    nv50_screen_init_hwctx(screen);
1056
1057    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1058    if (ret) {
1059       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1060       goto fail;
1061    }
1062
1063    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1064
1065    return &screen->base;
1066
1067 fail:
1068    screen->base.base.context_create = NULL;
1069    return &screen->base;
1070 }
1071
1072 int
1073 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1074 {
1075    int i = screen->tic.next;
1076
1077    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1078       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1079
1080    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1081
1082    if (screen->tic.entries[i])
1083       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1084
1085    screen->tic.entries[i] = entry;
1086    return i;
1087 }
1088
1089 int
1090 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1091 {
1092    int i = screen->tsc.next;
1093
1094    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1095       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1096
1097    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1098
1099    if (screen->tsc.entries[i])
1100       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1101
1102    screen->tsc.entries[i] = entry;
1103    return i;
1104 }