src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* shared is always supported */
  79    bindings &= ~(PIPE_BIND_LINEAR |
  80                  PIPE_BIND_SHARED);
  81
  82    return (( nv50_format_table[format].usage |
  83             nv50_vertex_format[format].usage) & bindings) == bindings;
  84 }
  85
  86 static int
  87 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  88 {
  89    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  90    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  91
  92    switch (param) {
  93    /* non-boolean caps */
  94    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  97       return 12;
  98    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  99       return 14;
 100    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 101       return 512;
 102    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 103    case PIPE_CAP_MIN_TEXEL_OFFSET:
 104       return -8;
 105    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MAX_TEXEL_OFFSET:
 107       return 7;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 128 * 1024 * 1024;
 110    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 111       return 330;
 112    case PIPE_CAP_MAX_RENDER_TARGETS:
 113       return 8;
 114    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 115       return 1;
 116    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 117       return 4;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 120       return 64;
 121    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 122    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 123       return 1024;
 124    case PIPE_CAP_MAX_VERTEX_STREAMS:
 125       return 1;
 126    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 127       return 2048;
 128    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 129       return 256;
 130    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 131       return 16; /* 256 for binding as RT, but that's not possible in GL */
 132    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 133       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 134    case PIPE_CAP_MAX_VIEWPORTS:
 135       return NV50_MAX_VIEWPORTS;
 136    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 137       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 138    case PIPE_CAP_ENDIANNESS:
 139       return PIPE_ENDIAN_LITTLE;
 140    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 141       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 142    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 143       return NV50_MAX_WINDOW_RECTANGLES;
 144
 145    /* supported caps */
 146    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 147    case PIPE_CAP_TEXTURE_SWIZZLE:
 148    case PIPE_CAP_NPOT_TEXTURES:
 149    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 150    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 151    case PIPE_CAP_ANISOTROPIC_FILTER:
 152    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 153    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 154    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 155    case PIPE_CAP_POINT_SPRITE:
 156    case PIPE_CAP_SM3:
 157    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 158    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 159    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 160    case PIPE_CAP_QUERY_TIMESTAMP:
 161    case PIPE_CAP_QUERY_TIME_ELAPSED:
 162    case PIPE_CAP_OCCLUSION_QUERY:
 163    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 164    case PIPE_CAP_INDEP_BLEND_ENABLE:
 165    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 166    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 167    case PIPE_CAP_PRIMITIVE_RESTART:
 168    case PIPE_CAP_TGSI_INSTANCEID:
 169    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 170    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 171    case PIPE_CAP_CONDITIONAL_RENDER:
 172    case PIPE_CAP_TEXTURE_BARRIER:
 173    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 174    case PIPE_CAP_START_INSTANCE:
 175    case PIPE_CAP_USER_VERTEX_BUFFERS:
 176    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 177    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 178    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 179    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 180    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 181    case PIPE_CAP_CLIP_HALFZ:
 182    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 183    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 184    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 185    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 186    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 187    case PIPE_CAP_TGSI_TXQS:
 188    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 189    case PIPE_CAP_SHAREABLE_SHADERS:
 190    case PIPE_CAP_CLEAR_TEXTURE:
 191    case PIPE_CAP_COMPUTE:
 192    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 193    case PIPE_CAP_INVALIDATE_BUFFER:
 194    case PIPE_CAP_STRING_MARKER:
 195    case PIPE_CAP_CULL_DISTANCE:
 196    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 197    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 198    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 199    case PIPE_CAP_TGSI_CLOCK:
 200    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 201    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 202       return 1;
 203    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 204       return 1; /* class_3d >= NVA0_3D_CLASS; */
 205    /* supported on nva0+ */
 206    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 207       return class_3d >= NVA0_3D_CLASS;
 208    /* supported on nva3+ */
 209    case PIPE_CAP_CUBE_MAP_ARRAY:
 210    case PIPE_CAP_INDEP_BLEND_FUNC:
 211    case PIPE_CAP_TEXTURE_QUERY_LOD:
 212    case PIPE_CAP_SAMPLE_SHADING:
 213    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 214       return class_3d >= NVA3_3D_CLASS;
 215
 216    /* unsupported caps */
 217    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 218    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 219    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 220    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 221    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 222    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 223    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 224    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 225    case PIPE_CAP_TGSI_TEXCOORD:
 226    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 227    case PIPE_CAP_TEXTURE_GATHER_SM5:
 228    case PIPE_CAP_FAKE_SW_MSAA:
 229    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 230    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 231    case PIPE_CAP_DRAW_INDIRECT:
 232    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 233    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 234    case PIPE_CAP_VERTEXID_NOBASE:
 235    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 236    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 237    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 238    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 239    case PIPE_CAP_DRAW_PARAMETERS:
 240    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 241    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 242    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 243    case PIPE_CAP_GENERATE_MIPMAP:
 244    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 245    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 246    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 247    case PIPE_CAP_QUERY_MEMORY_INFO:
 248    case PIPE_CAP_PCI_GROUP:
 249    case PIPE_CAP_PCI_BUS:
 250    case PIPE_CAP_PCI_DEVICE:
 251    case PIPE_CAP_PCI_FUNCTION:
 252    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 253    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 254    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 255    case PIPE_CAP_TGSI_VOTE:
 256    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 257    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 258    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 259    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 260    case PIPE_CAP_NATIVE_FENCE_FD:
 261    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 262    case PIPE_CAP_TGSI_FS_FBFETCH:
 263    case PIPE_CAP_DOUBLES:
 264    case PIPE_CAP_INT64:
 265    case PIPE_CAP_INT64_DIVMOD:
 266    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 267    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 268    case PIPE_CAP_TGSI_BALLOT:
 269    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 270    case PIPE_CAP_POST_DEPTH_COVERAGE:
 271    case PIPE_CAP_BINDLESS_TEXTURE:
 272    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 273    case PIPE_CAP_QUERY_SO_OVERFLOW:
 274    case PIPE_CAP_MEMOBJ:
 275    case PIPE_CAP_LOAD_CONSTBUF:
 276    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 277    case PIPE_CAP_TILE_RASTER_ORDER:
 278    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 279    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 280    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 281    case PIPE_CAP_FENCE_SIGNAL:
 282    case PIPE_CAP_CONSTBUF0_FLAGS:
 283    case PIPE_CAP_PACKED_UNIFORMS:
 284    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 285    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 286    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 287    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 288    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 289    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 290       return 0;
 291
 292    case PIPE_CAP_VENDOR_ID:
 293       return 0x10de;
 294    case PIPE_CAP_DEVICE_ID: {
 295       uint64_t device_id;
 296       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 297          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 298          return -1;
 299       }
 300       return device_id;
 301    }
 302    case PIPE_CAP_ACCELERATED:
 303       return 1;
 304    case PIPE_CAP_VIDEO_MEMORY:
 305       return dev->vram_size >> 20;
 306    case PIPE_CAP_UMA:
 307       return 0;
 308    }
 309
 310    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 311    return 0;
 312 }
 313
 314 static int
 315 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 316                              enum pipe_shader_type shader,
 317                              enum pipe_shader_cap param)
 318 {
 319    switch (shader) {
 320    case PIPE_SHADER_VERTEX:
 321    case PIPE_SHADER_GEOMETRY:
 322    case PIPE_SHADER_FRAGMENT:
 323       break;
 324    case PIPE_SHADER_COMPUTE:
 325    default:
 326       return 0;
 327    }
 328
 329    switch (param) {
 330    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 331    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 332    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 333    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 334       return 16384;
 335    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 336       return 4;
 337    case PIPE_SHADER_CAP_MAX_INPUTS:
 338       if (shader == PIPE_SHADER_VERTEX)
 339          return 32;
 340       return 15;
 341    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 342       return 16;
 343    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 344       return 65536;
 345    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 346       return NV50_MAX_PIPE_CONSTBUFS;
 347    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 348       return shader != PIPE_SHADER_FRAGMENT;
 349    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 350    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 351    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 352       return 1;
 353    case PIPE_SHADER_CAP_MAX_TEMPS:
 354       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 355    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 356       return 1;
 357    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 358       return 1;
 359    case PIPE_SHADER_CAP_INT64_ATOMICS:
 360    case PIPE_SHADER_CAP_FP16:
 361    case PIPE_SHADER_CAP_SUBROUTINES:
 362       return 0; /* please inline, or provide function declarations */
 363    case PIPE_SHADER_CAP_INTEGERS:
 364       return 1;
 365    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 366       return 1;
 367    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 368       /* The chip could handle more sampler views than samplers */
 369    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 370       return MIN2(16, PIPE_MAX_SAMPLERS);
 371    case PIPE_SHADER_CAP_PREFERRED_IR:
 372       return PIPE_SHADER_IR_TGSI;
 373    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 374       return 32;
 375    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 376    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 377    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 378    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 379    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 380    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 381    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 382    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 383    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 384    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 385    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 386       return 0;
 387    default:
 388       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 389       return 0;
 390    }
 391 }
 392
 393 static float
 394 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 395 {
 396    switch (param) {
 397    case PIPE_CAPF_MAX_LINE_WIDTH:
 398    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 399       return 10.0f;
 400    case PIPE_CAPF_MAX_POINT_WIDTH:
 401    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 402       return 64.0f;
 403    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 404       return 16.0f;
 405    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 406       return 4.0f;
 407    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 408    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 409    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 410       return 0.0f;
 411    }
 412
 413    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 414    return 0.0f;
 415 }
 416
 417 static int
 418 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 419                               enum pipe_shader_ir ir_type,
 420                               enum pipe_compute_cap param, void *data)
 421 {
 422    struct nv50_screen *screen = nv50_screen(pscreen);
 423
 424 #define RET(x) do {                  \
 425    if (data)                         \
 426       memcpy(data, x, sizeof(x));    \
 427    return sizeof(x);                 \
 428 } while (0)
 429
 430    switch (param) {
 431    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 432       RET((uint64_t []) { 2 });
 433    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 434       RET(((uint64_t []) { 65535, 65535 }));
 435    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 436       RET(((uint64_t []) { 512, 512, 64 }));
 437    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 438       RET((uint64_t []) { 512 });
 439    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 440       RET((uint64_t []) { 1ULL << 32 });
 441    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 442       RET((uint64_t []) { 16 << 10 });
 443    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 444       RET((uint64_t []) { 16 << 10 });
 445    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 446       RET((uint64_t []) { 4096 });
 447    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 448       RET((uint32_t []) { 32 });
 449    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 450       RET((uint64_t []) { 1ULL << 40 });
 451    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 452       RET((uint32_t []) { 0 });
 453    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 454       RET((uint32_t []) { screen->mp_count });
 455    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 456       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 457    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 458       RET((uint32_t []) { 32 });
 459    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 460       RET((uint64_t []) { 0 });
 461    default:
 462       return 0;
 463    }
 464
 465 #undef RET
 466 }
 467
 468 static void
 469 nv50_screen_destroy(struct pipe_screen *pscreen)
 470 {
 471    struct nv50_screen *screen = nv50_screen(pscreen);
 472
 473    if (!nouveau_drm_screen_unref(&screen->base))
 474       return;
 475
 476    if (screen->base.fence.current) {
 477       struct nouveau_fence *current = NULL;
 478
 479       /* nouveau_fence_wait will create a new current fence, so wait on the
 480        * _current_ one, and remove both.
 481        */
 482       nouveau_fence_ref(screen->base.fence.current, &current);
 483       nouveau_fence_wait(current, NULL);
 484       nouveau_fence_ref(NULL, &current);
 485       nouveau_fence_ref(NULL, &screen->base.fence.current);
 486    }
 487    if (screen->base.pushbuf)
 488       screen->base.pushbuf->user_priv = NULL;
 489
 490    if (screen->blitter)
 491       nv50_blitter_destroy(screen);
 492    if (screen->pm.prog) {
 493       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 494       nv50_program_destroy(NULL, screen->pm.prog);
 495       FREE(screen->pm.prog);
 496    }
 497
 498    nouveau_bo_ref(NULL, &screen->code);
 499    nouveau_bo_ref(NULL, &screen->tls_bo);
 500    nouveau_bo_ref(NULL, &screen->stack_bo);
 501    nouveau_bo_ref(NULL, &screen->txc);
 502    nouveau_bo_ref(NULL, &screen->uniforms);
 503    nouveau_bo_ref(NULL, &screen->fence.bo);
 504
 505    nouveau_heap_destroy(&screen->vp_code_heap);
 506    nouveau_heap_destroy(&screen->gp_code_heap);
 507    nouveau_heap_destroy(&screen->fp_code_heap);
 508
 509    FREE(screen->tic.entries);
 510
 511    nouveau_object_del(&screen->tesla);
 512    nouveau_object_del(&screen->eng2d);
 513    nouveau_object_del(&screen->m2mf);
 514    nouveau_object_del(&screen->compute);
 515    nouveau_object_del(&screen->sync);
 516
 517    nouveau_screen_fini(&screen->base);
 518
 519    FREE(screen);
 520 }
 521
 522 static void
 523 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 524 {
 525    struct nv50_screen *screen = nv50_screen(pscreen);
 526    struct nouveau_pushbuf *push = screen->base.pushbuf;
 527
 528    /* we need to do it after possible flush in MARK_RING */
 529    *sequence = ++screen->base.fence.sequence;
 530
 531    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 532    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 533    PUSH_DATAh(push, screen->fence.bo->offset);
 534    PUSH_DATA (push, screen->fence.bo->offset);
 535    PUSH_DATA (push, *sequence);
 536    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 537                     NV50_3D_QUERY_GET_UNK4 |
 538                     NV50_3D_QUERY_GET_UNIT_CROP |
 539                     NV50_3D_QUERY_GET_TYPE_QUERY |
 540                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 541                     NV50_3D_QUERY_GET_SHORT);
 542 }
 543
 544 static u32
 545 nv50_screen_fence_update(struct pipe_screen *pscreen)
 546 {
 547    return nv50_screen(pscreen)->fence.map[0];
 548 }
 549
 550 static void
 551 nv50_screen_init_hwctx(struct nv50_screen *screen)
 552 {
 553    struct nouveau_pushbuf *push = screen->base.pushbuf;
 554    struct nv04_fifo *fifo;
 555    unsigned i;
 556
 557    fifo = (struct nv04_fifo *)screen->base.channel->data;
 558
 559    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 560    PUSH_DATA (push, screen->m2mf->handle);
 561    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 562    PUSH_DATA (push, screen->sync->handle);
 563    PUSH_DATA (push, fifo->vram);
 564    PUSH_DATA (push, fifo->vram);
 565
 566    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 567    PUSH_DATA (push, screen->eng2d->handle);
 568    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 569    PUSH_DATA (push, screen->sync->handle);
 570    PUSH_DATA (push, fifo->vram);
 571    PUSH_DATA (push, fifo->vram);
 572    PUSH_DATA (push, fifo->vram);
 573    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 574    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 575    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 576    PUSH_DATA (push, 0);
 577    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 578    PUSH_DATA (push, 0);
 579    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 580    PUSH_DATA (push, 1);
 581    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 582    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 583
 584    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 585    PUSH_DATA (push, screen->tesla->handle);
 586
 587    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 588    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 589
 590    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 591    PUSH_DATA (push, screen->sync->handle);
 592    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 593    for (i = 0; i < 11; ++i)
 594       PUSH_DATA(push, fifo->vram);
 595    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 596    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 597       PUSH_DATA(push, fifo->vram);
 598
 599    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 600    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 601    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 602    PUSH_DATA (push, 0xf);
 603
 604    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 605       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 606       PUSH_DATA (push, 0x18);
 607    }
 608
 609    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 610    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 611
 612    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 613    for (i = 0; i < 8; ++i)
 614       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 615
 616    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 617    PUSH_DATA (push, 1);
 618
 619    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 620    PUSH_DATA (push, 0);
 621    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 622    PUSH_DATA (push, 0);
 623    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 624    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 625    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 626    PUSH_DATA (push, 0);
 627    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 628    PUSH_DATA (push, 1);
 629    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 630    PUSH_DATA (push, 1);
 631
 632    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 633       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 634       PUSH_DATA (push, 0);
 635    }
 636
 637    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 638    PUSH_DATA (push, 0);
 639    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 640    PUSH_DATA (push, 0);
 641    PUSH_DATA (push, 0);
 642    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 643    PUSH_DATA (push, 0x3f);
 644
 645    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 646    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 647    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 648
 649    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 650    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 651    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 652
 653    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 654    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 655    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 656
 657    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 658    PUSH_DATAh(push, screen->tls_bo->offset);
 659    PUSH_DATA (push, screen->tls_bo->offset);
 660    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 661
 662    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 663    PUSH_DATAh(push, screen->stack_bo->offset);
 664    PUSH_DATA (push, screen->stack_bo->offset);
 665    PUSH_DATA (push, 4);
 666
 667    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 668    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 669    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 670    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 671
 672    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 673    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 674    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 675    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 676
 677    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 678    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 679    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 680    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 681
 682    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 683    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 684    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 685    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 686
 687    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 688    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 689    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 690    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 691
 692    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 693    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 694    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 695    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 696    PUSH_DATAf(push, 0.0f);
 697    PUSH_DATAf(push, 0.0f);
 698    PUSH_DATAf(push, 0.0f);
 699    PUSH_DATAf(push, 0.0f);
 700    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 701    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 702    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 703
 704    nv50_upload_ms_info(push);
 705
 706    /* max TIC (bits 4:8) & TSC bindings, per program type */
 707    for (i = 0; i < 3; ++i) {
 708       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 709       PUSH_DATA (push, 0x54);
 710    }
 711
 712    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 713    PUSH_DATAh(push, screen->txc->offset);
 714    PUSH_DATA (push, screen->txc->offset);
 715    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 716
 717    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 718    PUSH_DATAh(push, screen->txc->offset + 65536);
 719    PUSH_DATA (push, screen->txc->offset + 65536);
 720    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 721
 722    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 723    PUSH_DATA (push, 0);
 724
 725    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 726    PUSH_DATA (push, 0);
 727    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 728    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 729    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 730    for (i = 0; i < 8 * 2; ++i)
 731       PUSH_DATA(push, 0);
 732    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 733    PUSH_DATA (push, 0);
 734
 735    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 736    PUSH_DATA (push, 1);
 737    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 738       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 739       PUSH_DATAf(push, 0.0f);
 740       PUSH_DATAf(push, 1.0f);
 741       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 742       PUSH_DATA (push, 8192 << 16);
 743       PUSH_DATA (push, 8192 << 16);
 744    }
 745
 746    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 747 #ifdef NV50_SCISSORS_CLIPPING
 748    PUSH_DATA (push, 0x0000);
 749 #else
 750    PUSH_DATA (push, 0x1080);
 751 #endif
 752
 753    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 754    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 755
 756    /* We use scissors instead of exact view volume clipping,
 757     * so they're always enabled.
 758     */
 759    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 760       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 761       PUSH_DATA (push, 1);
 762       PUSH_DATA (push, 8192 << 16);
 763       PUSH_DATA (push, 8192 << 16);
 764    }
 765
 766    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 767    PUSH_DATA (push, 1);
 768    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 769    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 770    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 771    PUSH_DATA (push, 0x11111111);
 772    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 773    PUSH_DATA (push, 1);
 774
 775    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 776    PUSH_DATA (push, 0);
 777    if (screen->base.class_3d >= NV84_3D_CLASS) {
 778       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 779       PUSH_DATA (push, 0);
 780    }
 781
 782    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 783    PUSH_DATA (push, 1);
 784    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 785    PUSH_DATA (push, 1);
 786
 787    PUSH_KICK (push);
 788 }
 789
 790 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 791       uint64_t *tls_size)
 792 {
 793    struct nouveau_device *dev = screen->base.device;
 794    int ret;
 795
 796    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 797          ONE_TEMP_SIZE;
 798    if (nouveau_mesa_debug)
 799       debug_printf("allocating space for %u temps\n",
 800             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 801    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 802          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 803
 804    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 805                         *tls_size, NULL, &screen->tls_bo);
 806    if (ret) {
 807       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 808       return ret;
 809    }
 810
 811    return 0;
 812 }
 813
 814 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 815 {
 816    struct nouveau_pushbuf *push = screen->base.pushbuf;
 817    int ret;
 818    uint64_t tls_size;
 819
 820    if (tls_space < screen->cur_tls_space)
 821       return 0;
 822    if (tls_space > screen->max_tls_space) {
 823       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 824        * LOCAL_WARPS_NO_CLAMP) */
 825       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 826             (unsigned)(tls_space / ONE_TEMP_SIZE),
 827             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 828       return -ENOMEM;
 829    }
 830
 831    nouveau_bo_ref(NULL, &screen->tls_bo);
 832    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 833    if (ret)
 834       return ret;
 835
 836    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 837    PUSH_DATAh(push, screen->tls_bo->offset);
 838    PUSH_DATA (push, screen->tls_bo->offset);
 839    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 840
 841    return 1;
 842 }
 843
 844 struct nouveau_screen *
 845 nv50_screen_create(struct nouveau_device *dev)
 846 {
 847    struct nv50_screen *screen;
 848    struct pipe_screen *pscreen;
 849    struct nouveau_object *chan;
 850    uint64_t value;
 851    uint32_t tesla_class;
 852    unsigned stack_size;
 853    int ret;
 854
 855    screen = CALLOC_STRUCT(nv50_screen);
 856    if (!screen)
 857       return NULL;
 858    pscreen = &screen->base.base;
 859    pscreen->destroy = nv50_screen_destroy;
 860
 861    ret = nouveau_screen_init(&screen->base, dev);
 862    if (ret) {
 863       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 864       goto fail;
 865    }
 866
 867    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 868     *  admit them to VRAM.
 869     */
 870    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 871       PIPE_BIND_VERTEX_BUFFER;
 872    screen->base.sysmem_bindings |=
 873       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 874
 875    screen->base.pushbuf->user_priv = screen;
 876    screen->base.pushbuf->rsvd_kick = 5;
 877
 878    chan = screen->base.channel;
 879
 880    pscreen->context_create = nv50_create;
 881    pscreen->is_format_supported = nv50_screen_is_format_supported;
 882    pscreen->get_param = nv50_screen_get_param;
 883    pscreen->get_shader_param = nv50_screen_get_shader_param;
 884    pscreen->get_paramf = nv50_screen_get_paramf;
 885    pscreen->get_compute_param = nv50_screen_get_compute_param;
 886    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 887    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 888
 889    nv50_screen_init_resource_functions(pscreen);
 890
 891    if (screen->base.device->chipset < 0x84 ||
 892        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 893       /* PMPEG */
 894       nouveau_screen_init_vdec(&screen->base);
 895    } else if (screen->base.device->chipset < 0x98 ||
 896               screen->base.device->chipset == 0xa0) {
 897       /* VP2 */
 898       screen->base.base.get_video_param = nv84_screen_get_video_param;
 899       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 900    } else {
 901       /* VP3/4 */
 902       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 903       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 904    }
 905
 906    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 907                         NULL, &screen->fence.bo);
 908    if (ret) {
 909       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 910       goto fail;
 911    }
 912
 913    nouveau_bo_map(screen->fence.bo, 0, NULL);
 914    screen->fence.map = screen->fence.bo->map;
 915    screen->base.fence.emit = nv50_screen_fence_emit;
 916    screen->base.fence.update = nv50_screen_fence_update;
 917
 918    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 919                             &(struct nv04_notify){ .length = 32 },
 920                             sizeof(struct nv04_notify), &screen->sync);
 921    if (ret) {
 922       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 923       goto fail;
 924    }
 925
 926    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 927                             NULL, 0, &screen->m2mf);
 928    if (ret) {
 929       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 930       goto fail;
 931    }
 932
 933    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 934                             NULL, 0, &screen->eng2d);
 935    if (ret) {
 936       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 937       goto fail;
 938    }
 939
 940    switch (dev->chipset & 0xf0) {
 941    case 0x50:
 942       tesla_class = NV50_3D_CLASS;
 943       break;
 944    case 0x80:
 945    case 0x90:
 946       tesla_class = NV84_3D_CLASS;
 947       break;
 948    case 0xa0:
 949       switch (dev->chipset) {
 950       case 0xa0:
 951       case 0xaa:
 952       case 0xac:
 953          tesla_class = NVA0_3D_CLASS;
 954          break;
 955       case 0xaf:
 956          tesla_class = NVAF_3D_CLASS;
 957          break;
 958       default:
 959          tesla_class = NVA3_3D_CLASS;
 960          break;
 961       }
 962       break;
 963    default:
 964       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 965       goto fail;
 966    }
 967    screen->base.class_3d = tesla_class;
 968
 969    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 970                             NULL, 0, &screen->tesla);
 971    if (ret) {
 972       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 973       goto fail;
 974    }
 975
 976    /* This over-allocates by a page. The GP, which would execute at the end of
 977     * the last page, would trigger faults. The going theory is that it
 978     * prefetches up to a certain amount.
 979     */
 980    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 981                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 982                         NULL, &screen->code);
 983    if (ret) {
 984       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 985       goto fail;
 986    }
 987
 988    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 989    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 990    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 991
 992    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 993
 994    screen->TPs = util_bitcount(value & 0xffff);
 995    screen->MPsInTP = util_bitcount(value & 0x0f000000);
 996
 997    screen->mp_count = screen->TPs * screen->MPsInTP;
 998
 999    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1000          STACK_WARPS_ALLOC * 64 * 8;
1001
1002    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1003                         &screen->stack_bo);
1004    if (ret) {
1005       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1006       goto fail;
1007    }
1008
1009    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1010          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1011          ONE_TEMP_SIZE;
1012    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1013    screen->max_tls_space /= 2; /* half of vram */
1014
1015    /* hw can address max 64 KiB */
1016    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1017
1018    uint64_t tls_size;
1019    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1020    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1021    if (ret)
1022       goto fail;
1023
1024    if (nouveau_mesa_debug)
1025       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1026             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1027
1028    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1029                         &screen->uniforms);
1030    if (ret) {
1031       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1032       goto fail;
1033    }
1034
1035    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1036                         &screen->txc);
1037    if (ret) {
1038       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1039       goto fail;
1040    }
1041
1042    screen->tic.entries = CALLOC(4096, sizeof(void *));
1043    screen->tsc.entries = screen->tic.entries + 2048;
1044
1045    if (!nv50_blitter_create(screen))
1046       goto fail;
1047
1048    nv50_screen_init_hwctx(screen);
1049
1050    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1051    if (ret) {
1052       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1053       goto fail;
1054    }
1055
1056    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1057
1058    return &screen->base;
1059
1060 fail:
1061    screen->base.base.context_create = NULL;
1062    return &screen->base;
1063 }
1064
1065 int
1066 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1067 {
1068    int i = screen->tic.next;
1069
1070    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1071       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1072
1073    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1074
1075    if (screen->tic.entries[i])
1076       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1077
1078    screen->tic.entries[i] = entry;
1079    return i;
1080 }
1081
1082 int
1083 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1084 {
1085    int i = screen->tsc.next;
1086
1087    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1088       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1089
1090    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1091
1092    if (screen->tsc.entries[i])
1093       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1094
1095    screen->tsc.entries[i] = entry;
1096    return i;
1097 }