src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30
  31 #include "nv50/nv50_context.h"
  32 #include "nv50/nv50_screen.h"
  33
  34 #include "nouveau_vp3_video.h"
  35
  36 #include "nv_object.xml.h"
  37
  38 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  39 #define LOCAL_WARPS_ALLOC 32
  40 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  41 #define STACK_WARPS_ALLOC 32
  42
  43 #define THREADS_IN_WARP 32
  44
  45 static boolean
  46 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  47                                 enum pipe_format format,
  48                                 enum pipe_texture_target target,
  49                                 unsigned sample_count,
  50                                 unsigned storage_sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (sample_count > 8)
  54       return false;
  55    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  56       return false;
  57    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  58       return false;
  59
  60    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  61       return false;
  62
  63    switch (format) {
  64    case PIPE_FORMAT_Z16_UNORM:
  65       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  66          return false;
  67       break;
  68    default:
  69       break;
  70    }
  71
  72    if (bindings & PIPE_BIND_LINEAR)
  73       if (util_format_is_depth_or_stencil(format) ||
  74           (target != PIPE_TEXTURE_1D &&
  75            target != PIPE_TEXTURE_2D &&
  76            target != PIPE_TEXTURE_RECT) ||
  77           sample_count > 1)
  78          return false;
  79
  80    /* shared is always supported */
  81    bindings &= ~(PIPE_BIND_LINEAR |
  82                  PIPE_BIND_SHARED);
  83
  84    return (( nv50_format_table[format].usage |
  85             nv50_vertex_format[format].usage) & bindings) == bindings;
  86 }
  87
  88 static int
  89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  90 {
  91    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  92    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  93
  94    switch (param) {
  95    /* non-boolean caps */
  96    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  97       return 14;
  98    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  99       return 12;
 100    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 101       return 14;
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103       return 512;
 104    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 105    case PIPE_CAP_MIN_TEXEL_OFFSET:
 106       return -8;
 107    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109       return 7;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 128 * 1024 * 1024;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 113       return 330;
 114    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 115       return 330;
 116    case PIPE_CAP_MAX_RENDER_TARGETS:
 117       return 8;
 118    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 119       return 1;
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 121       return 4;
 122    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 124       return 64;
 125    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 126    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 127       return 1024;
 128    case PIPE_CAP_MAX_VERTEX_STREAMS:
 129       return 1;
 130    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 131       return 2048;
 132    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 133       return 256;
 134    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 135       return 16; /* 256 for binding as RT, but that's not possible in GL */
 136    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 137       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 138    case PIPE_CAP_MAX_VIEWPORTS:
 139       return NV50_MAX_VIEWPORTS;
 140    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 141       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 142    case PIPE_CAP_ENDIANNESS:
 143       return PIPE_ENDIAN_LITTLE;
 144    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 145       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 146    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 147       return NV50_MAX_WINDOW_RECTANGLES;
 148
 149    /* supported caps */
 150    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 151    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 152    case PIPE_CAP_TEXTURE_SWIZZLE:
 153    case PIPE_CAP_NPOT_TEXTURES:
 154    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 155    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 156    case PIPE_CAP_ANISOTROPIC_FILTER:
 157    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 158    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 159    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 160    case PIPE_CAP_POINT_SPRITE:
 161    case PIPE_CAP_SM3:
 162    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 163    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 164    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 165    case PIPE_CAP_QUERY_TIMESTAMP:
 166    case PIPE_CAP_QUERY_TIME_ELAPSED:
 167    case PIPE_CAP_OCCLUSION_QUERY:
 168    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 169    case PIPE_CAP_INDEP_BLEND_ENABLE:
 170    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 171    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 172    case PIPE_CAP_PRIMITIVE_RESTART:
 173    case PIPE_CAP_TGSI_INSTANCEID:
 174    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 175    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 176    case PIPE_CAP_CONDITIONAL_RENDER:
 177    case PIPE_CAP_TEXTURE_BARRIER:
 178    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 179    case PIPE_CAP_START_INSTANCE:
 180    case PIPE_CAP_USER_VERTEX_BUFFERS:
 181    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 182    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 183    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 184    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 185    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 186    case PIPE_CAP_CLIP_HALFZ:
 187    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 188    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 189    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 190    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 191    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 192    case PIPE_CAP_TGSI_TXQS:
 193    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 194    case PIPE_CAP_SHAREABLE_SHADERS:
 195    case PIPE_CAP_CLEAR_TEXTURE:
 196    case PIPE_CAP_COMPUTE:
 197    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 198    case PIPE_CAP_INVALIDATE_BUFFER:
 199    case PIPE_CAP_STRING_MARKER:
 200    case PIPE_CAP_CULL_DISTANCE:
 201    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 202    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 203    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 204    case PIPE_CAP_TGSI_CLOCK:
 205    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 206    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 207       return 1;
 208    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 209       return 1; /* class_3d >= NVA0_3D_CLASS; */
 210    /* supported on nva0+ */
 211    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 212       return class_3d >= NVA0_3D_CLASS;
 213    /* supported on nva3+ */
 214    case PIPE_CAP_CUBE_MAP_ARRAY:
 215    case PIPE_CAP_INDEP_BLEND_FUNC:
 216    case PIPE_CAP_TEXTURE_QUERY_LOD:
 217    case PIPE_CAP_SAMPLE_SHADING:
 218    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 219       return class_3d >= NVA3_3D_CLASS;
 220
 221    /* unsupported caps */
 222    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 223    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 224    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 225    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 226    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 227    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 228    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 229    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 230    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 231    case PIPE_CAP_TGSI_TEXCOORD:
 232    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 233    case PIPE_CAP_TEXTURE_GATHER_SM5:
 234    case PIPE_CAP_FAKE_SW_MSAA:
 235    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 236    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 237    case PIPE_CAP_DRAW_INDIRECT:
 238    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 239    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 240    case PIPE_CAP_VERTEXID_NOBASE:
 241    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 242    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 243    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 244    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 245    case PIPE_CAP_DRAW_PARAMETERS:
 246    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 247    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 248    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 249    case PIPE_CAP_GENERATE_MIPMAP:
 250    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 251    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 252    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 253    case PIPE_CAP_QUERY_MEMORY_INFO:
 254    case PIPE_CAP_PCI_GROUP:
 255    case PIPE_CAP_PCI_BUS:
 256    case PIPE_CAP_PCI_DEVICE:
 257    case PIPE_CAP_PCI_FUNCTION:
 258    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 259    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 260    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 261    case PIPE_CAP_TGSI_VOTE:
 262    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 263    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 264    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 265    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 266    case PIPE_CAP_NATIVE_FENCE_FD:
 267    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 268    case PIPE_CAP_TGSI_FS_FBFETCH:
 269    case PIPE_CAP_DOUBLES:
 270    case PIPE_CAP_INT64:
 271    case PIPE_CAP_INT64_DIVMOD:
 272    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 273    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 274    case PIPE_CAP_TGSI_BALLOT:
 275    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 276    case PIPE_CAP_POST_DEPTH_COVERAGE:
 277    case PIPE_CAP_BINDLESS_TEXTURE:
 278    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 279    case PIPE_CAP_QUERY_SO_OVERFLOW:
 280    case PIPE_CAP_MEMOBJ:
 281    case PIPE_CAP_LOAD_CONSTBUF:
 282    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 283    case PIPE_CAP_TILE_RASTER_ORDER:
 284    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 285    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 286    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 287    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 288    case PIPE_CAP_FENCE_SIGNAL:
 289    case PIPE_CAP_CONSTBUF0_FLAGS:
 290    case PIPE_CAP_PACKED_UNIFORMS:
 291    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 292    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 293    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 294    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 295    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 296    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 297    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 298    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 299       return 0;
 300
 301    case PIPE_CAP_MAX_GS_INVOCATIONS:
 302       return 32;
 303    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 304       return 1 << 27;
 305    case PIPE_CAP_VENDOR_ID:
 306       return 0x10de;
 307    case PIPE_CAP_DEVICE_ID: {
 308       uint64_t device_id;
 309       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 310          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 311          return -1;
 312       }
 313       return device_id;
 314    }
 315    case PIPE_CAP_ACCELERATED:
 316       return 1;
 317    case PIPE_CAP_VIDEO_MEMORY:
 318       return dev->vram_size >> 20;
 319    case PIPE_CAP_UMA:
 320       return 0;
 321    default:
 322       return u_pipe_screen_get_param_defaults(pscreen, param);
 323    }
 324 }
 325
 326 static int
 327 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 328                              enum pipe_shader_type shader,
 329                              enum pipe_shader_cap param)
 330 {
 331    switch (shader) {
 332    case PIPE_SHADER_VERTEX:
 333    case PIPE_SHADER_GEOMETRY:
 334    case PIPE_SHADER_FRAGMENT:
 335       break;
 336    case PIPE_SHADER_COMPUTE:
 337    default:
 338       return 0;
 339    }
 340
 341    switch (param) {
 342    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 343    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 344    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 345    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 346       return 16384;
 347    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 348       return 4;
 349    case PIPE_SHADER_CAP_MAX_INPUTS:
 350       if (shader == PIPE_SHADER_VERTEX)
 351          return 32;
 352       return 15;
 353    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 354       return 16;
 355    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 356       return 65536;
 357    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 358       return NV50_MAX_PIPE_CONSTBUFS;
 359    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 360       return shader != PIPE_SHADER_FRAGMENT;
 361    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 362    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 363    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 364       return 1;
 365    case PIPE_SHADER_CAP_MAX_TEMPS:
 366       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 367    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 368       return 1;
 369    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 370       return 1;
 371    case PIPE_SHADER_CAP_INT64_ATOMICS:
 372    case PIPE_SHADER_CAP_FP16:
 373    case PIPE_SHADER_CAP_SUBROUTINES:
 374       return 0; /* please inline, or provide function declarations */
 375    case PIPE_SHADER_CAP_INTEGERS:
 376       return 1;
 377    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 378       return 1;
 379    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 380       /* The chip could handle more sampler views than samplers */
 381    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 382       return MIN2(16, PIPE_MAX_SAMPLERS);
 383    case PIPE_SHADER_CAP_PREFERRED_IR:
 384       return PIPE_SHADER_IR_TGSI;
 385    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 386       return 32;
 387    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 388    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 389    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 390    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 391    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 392    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 393    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 394    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 395    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 396    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 397    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 398       return 0;
 399    case PIPE_SHADER_CAP_SCALAR_ISA:
 400       return 1;
 401    default:
 402       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 403       return 0;
 404    }
 405 }
 406
 407 static float
 408 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 409 {
 410    switch (param) {
 411    case PIPE_CAPF_MAX_LINE_WIDTH:
 412    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 413       return 10.0f;
 414    case PIPE_CAPF_MAX_POINT_WIDTH:
 415    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 416       return 64.0f;
 417    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 418       return 16.0f;
 419    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 420       return 4.0f;
 421    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 422    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 423    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 424       return 0.0f;
 425    }
 426
 427    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 428    return 0.0f;
 429 }
 430
 431 static int
 432 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 433                               enum pipe_shader_ir ir_type,
 434                               enum pipe_compute_cap param, void *data)
 435 {
 436    struct nv50_screen *screen = nv50_screen(pscreen);
 437
 438 #define RET(x) do {                  \
 439    if (data)                         \
 440       memcpy(data, x, sizeof(x));    \
 441    return sizeof(x);                 \
 442 } while (0)
 443
 444    switch (param) {
 445    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 446       RET((uint64_t []) { 2 });
 447    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 448       RET(((uint64_t []) { 65535, 65535 }));
 449    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 450       RET(((uint64_t []) { 512, 512, 64 }));
 451    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 452       RET((uint64_t []) { 512 });
 453    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 454       RET((uint64_t []) { 1ULL << 32 });
 455    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 456       RET((uint64_t []) { 16 << 10 });
 457    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 458       RET((uint64_t []) { 16 << 10 });
 459    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 460       RET((uint64_t []) { 4096 });
 461    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 462       RET((uint32_t []) { 32 });
 463    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 464       RET((uint64_t []) { 1ULL << 40 });
 465    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 466       RET((uint32_t []) { 0 });
 467    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 468       RET((uint32_t []) { screen->mp_count });
 469    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 470       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 471    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 472       RET((uint32_t []) { 32 });
 473    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 474       RET((uint64_t []) { 0 });
 475    default:
 476       return 0;
 477    }
 478
 479 #undef RET
 480 }
 481
 482 static void
 483 nv50_screen_destroy(struct pipe_screen *pscreen)
 484 {
 485    struct nv50_screen *screen = nv50_screen(pscreen);
 486
 487    if (!nouveau_drm_screen_unref(&screen->base))
 488       return;
 489
 490    if (screen->base.fence.current) {
 491       struct nouveau_fence *current = NULL;
 492
 493       /* nouveau_fence_wait will create a new current fence, so wait on the
 494        * _current_ one, and remove both.
 495        */
 496       nouveau_fence_ref(screen->base.fence.current, &current);
 497       nouveau_fence_wait(current, NULL);
 498       nouveau_fence_ref(NULL, &current);
 499       nouveau_fence_ref(NULL, &screen->base.fence.current);
 500    }
 501    if (screen->base.pushbuf)
 502       screen->base.pushbuf->user_priv = NULL;
 503
 504    if (screen->blitter)
 505       nv50_blitter_destroy(screen);
 506    if (screen->pm.prog) {
 507       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 508       nv50_program_destroy(NULL, screen->pm.prog);
 509       FREE(screen->pm.prog);
 510    }
 511
 512    nouveau_bo_ref(NULL, &screen->code);
 513    nouveau_bo_ref(NULL, &screen->tls_bo);
 514    nouveau_bo_ref(NULL, &screen->stack_bo);
 515    nouveau_bo_ref(NULL, &screen->txc);
 516    nouveau_bo_ref(NULL, &screen->uniforms);
 517    nouveau_bo_ref(NULL, &screen->fence.bo);
 518
 519    nouveau_heap_destroy(&screen->vp_code_heap);
 520    nouveau_heap_destroy(&screen->gp_code_heap);
 521    nouveau_heap_destroy(&screen->fp_code_heap);
 522
 523    FREE(screen->tic.entries);
 524
 525    nouveau_object_del(&screen->tesla);
 526    nouveau_object_del(&screen->eng2d);
 527    nouveau_object_del(&screen->m2mf);
 528    nouveau_object_del(&screen->compute);
 529    nouveau_object_del(&screen->sync);
 530
 531    nouveau_screen_fini(&screen->base);
 532
 533    FREE(screen);
 534 }
 535
 536 static void
 537 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 538 {
 539    struct nv50_screen *screen = nv50_screen(pscreen);
 540    struct nouveau_pushbuf *push = screen->base.pushbuf;
 541
 542    /* we need to do it after possible flush in MARK_RING */
 543    *sequence = ++screen->base.fence.sequence;
 544
 545    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 546    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 547    PUSH_DATAh(push, screen->fence.bo->offset);
 548    PUSH_DATA (push, screen->fence.bo->offset);
 549    PUSH_DATA (push, *sequence);
 550    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 551                     NV50_3D_QUERY_GET_UNK4 |
 552                     NV50_3D_QUERY_GET_UNIT_CROP |
 553                     NV50_3D_QUERY_GET_TYPE_QUERY |
 554                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 555                     NV50_3D_QUERY_GET_SHORT);
 556 }
 557
 558 static u32
 559 nv50_screen_fence_update(struct pipe_screen *pscreen)
 560 {
 561    return nv50_screen(pscreen)->fence.map[0];
 562 }
 563
 564 static void
 565 nv50_screen_init_hwctx(struct nv50_screen *screen)
 566 {
 567    struct nouveau_pushbuf *push = screen->base.pushbuf;
 568    struct nv04_fifo *fifo;
 569    unsigned i;
 570
 571    fifo = (struct nv04_fifo *)screen->base.channel->data;
 572
 573    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 574    PUSH_DATA (push, screen->m2mf->handle);
 575    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 576    PUSH_DATA (push, screen->sync->handle);
 577    PUSH_DATA (push, fifo->vram);
 578    PUSH_DATA (push, fifo->vram);
 579
 580    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 581    PUSH_DATA (push, screen->eng2d->handle);
 582    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 583    PUSH_DATA (push, screen->sync->handle);
 584    PUSH_DATA (push, fifo->vram);
 585    PUSH_DATA (push, fifo->vram);
 586    PUSH_DATA (push, fifo->vram);
 587    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 588    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 589    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 590    PUSH_DATA (push, 0);
 591    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 592    PUSH_DATA (push, 0);
 593    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 594    PUSH_DATA (push, 1);
 595    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 596    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 597
 598    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 599    PUSH_DATA (push, screen->tesla->handle);
 600
 601    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 602    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 603
 604    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 605    PUSH_DATA (push, screen->sync->handle);
 606    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 607    for (i = 0; i < 11; ++i)
 608       PUSH_DATA(push, fifo->vram);
 609    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 610    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 611       PUSH_DATA(push, fifo->vram);
 612
 613    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 614    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 615    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 616    PUSH_DATA (push, 0xf);
 617
 618    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 619       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 620       PUSH_DATA (push, 0x18);
 621    }
 622
 623    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 624    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 625
 626    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 627    for (i = 0; i < 8; ++i)
 628       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 629
 630    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 631    PUSH_DATA (push, 1);
 632
 633    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 634    PUSH_DATA (push, 0);
 635    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 636    PUSH_DATA (push, 0);
 637    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 638    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 639    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 640    PUSH_DATA (push, 0);
 641    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 642    PUSH_DATA (push, 1);
 643    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 644    PUSH_DATA (push, 1);
 645
 646    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 647       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 648       PUSH_DATA (push, 0);
 649    }
 650
 651    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 652    PUSH_DATA (push, 0);
 653    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 654    PUSH_DATA (push, 0);
 655    PUSH_DATA (push, 0);
 656    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 657    PUSH_DATA (push, 0x3f);
 658
 659    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 660    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 661    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 662
 663    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 664    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 665    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 666
 667    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 668    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 669    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 670
 671    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 672    PUSH_DATAh(push, screen->tls_bo->offset);
 673    PUSH_DATA (push, screen->tls_bo->offset);
 674    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 675
 676    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 677    PUSH_DATAh(push, screen->stack_bo->offset);
 678    PUSH_DATA (push, screen->stack_bo->offset);
 679    PUSH_DATA (push, 4);
 680
 681    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 682    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 683    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 684    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 685
 686    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 687    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 688    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 689    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 690
 691    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 692    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 693    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 694    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 695
 696    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 697    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 698    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 699    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 700
 701    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 702    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 703    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 704    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 705
 706    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 707    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 708    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 709    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 710    PUSH_DATAf(push, 0.0f);
 711    PUSH_DATAf(push, 0.0f);
 712    PUSH_DATAf(push, 0.0f);
 713    PUSH_DATAf(push, 0.0f);
 714    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 715    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 716    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 717
 718    nv50_upload_ms_info(push);
 719
 720    /* max TIC (bits 4:8) & TSC bindings, per program type */
 721    for (i = 0; i < 3; ++i) {
 722       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 723       PUSH_DATA (push, 0x54);
 724    }
 725
 726    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 727    PUSH_DATAh(push, screen->txc->offset);
 728    PUSH_DATA (push, screen->txc->offset);
 729    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 730
 731    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 732    PUSH_DATAh(push, screen->txc->offset + 65536);
 733    PUSH_DATA (push, screen->txc->offset + 65536);
 734    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 735
 736    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 737    PUSH_DATA (push, 0);
 738
 739    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 740    PUSH_DATA (push, 0);
 741    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 742    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 743    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 744    for (i = 0; i < 8 * 2; ++i)
 745       PUSH_DATA(push, 0);
 746    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 747    PUSH_DATA (push, 0);
 748
 749    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 750    PUSH_DATA (push, 1);
 751    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 752       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 753       PUSH_DATAf(push, 0.0f);
 754       PUSH_DATAf(push, 1.0f);
 755       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 756       PUSH_DATA (push, 8192 << 16);
 757       PUSH_DATA (push, 8192 << 16);
 758    }
 759
 760    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 761 #ifdef NV50_SCISSORS_CLIPPING
 762    PUSH_DATA (push, 0x0000);
 763 #else
 764    PUSH_DATA (push, 0x1080);
 765 #endif
 766
 767    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 768    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 769
 770    /* We use scissors instead of exact view volume clipping,
 771     * so they're always enabled.
 772     */
 773    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 774       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 775       PUSH_DATA (push, 1);
 776       PUSH_DATA (push, 8192 << 16);
 777       PUSH_DATA (push, 8192 << 16);
 778    }
 779
 780    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 781    PUSH_DATA (push, 1);
 782    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 783    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 784    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 785    PUSH_DATA (push, 0x11111111);
 786    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 787    PUSH_DATA (push, 1);
 788
 789    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 790    PUSH_DATA (push, 0);
 791    if (screen->base.class_3d >= NV84_3D_CLASS) {
 792       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 793       PUSH_DATA (push, 0);
 794    }
 795
 796    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 797    PUSH_DATA (push, 1);
 798    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 799    PUSH_DATA (push, 1);
 800
 801    PUSH_KICK (push);
 802 }
 803
 804 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 805       uint64_t *tls_size)
 806 {
 807    struct nouveau_device *dev = screen->base.device;
 808    int ret;
 809
 810    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 811          ONE_TEMP_SIZE;
 812    if (nouveau_mesa_debug)
 813       debug_printf("allocating space for %u temps\n",
 814             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 815    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 816          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 817
 818    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 819                         *tls_size, NULL, &screen->tls_bo);
 820    if (ret) {
 821       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 822       return ret;
 823    }
 824
 825    return 0;
 826 }
 827
 828 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 829 {
 830    struct nouveau_pushbuf *push = screen->base.pushbuf;
 831    int ret;
 832    uint64_t tls_size;
 833
 834    if (tls_space < screen->cur_tls_space)
 835       return 0;
 836    if (tls_space > screen->max_tls_space) {
 837       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 838        * LOCAL_WARPS_NO_CLAMP) */
 839       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 840             (unsigned)(tls_space / ONE_TEMP_SIZE),
 841             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 842       return -ENOMEM;
 843    }
 844
 845    nouveau_bo_ref(NULL, &screen->tls_bo);
 846    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 847    if (ret)
 848       return ret;
 849
 850    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 851    PUSH_DATAh(push, screen->tls_bo->offset);
 852    PUSH_DATA (push, screen->tls_bo->offset);
 853    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 854
 855    return 1;
 856 }
 857
 858 struct nouveau_screen *
 859 nv50_screen_create(struct nouveau_device *dev)
 860 {
 861    struct nv50_screen *screen;
 862    struct pipe_screen *pscreen;
 863    struct nouveau_object *chan;
 864    uint64_t value;
 865    uint32_t tesla_class;
 866    unsigned stack_size;
 867    int ret;
 868
 869    screen = CALLOC_STRUCT(nv50_screen);
 870    if (!screen)
 871       return NULL;
 872    pscreen = &screen->base.base;
 873    pscreen->destroy = nv50_screen_destroy;
 874
 875    ret = nouveau_screen_init(&screen->base, dev);
 876    if (ret) {
 877       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 878       goto fail;
 879    }
 880
 881    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 882     *  admit them to VRAM.
 883     */
 884    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 885       PIPE_BIND_VERTEX_BUFFER;
 886    screen->base.sysmem_bindings |=
 887       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 888
 889    screen->base.pushbuf->user_priv = screen;
 890    screen->base.pushbuf->rsvd_kick = 5;
 891
 892    chan = screen->base.channel;
 893
 894    pscreen->context_create = nv50_create;
 895    pscreen->is_format_supported = nv50_screen_is_format_supported;
 896    pscreen->get_param = nv50_screen_get_param;
 897    pscreen->get_shader_param = nv50_screen_get_shader_param;
 898    pscreen->get_paramf = nv50_screen_get_paramf;
 899    pscreen->get_compute_param = nv50_screen_get_compute_param;
 900    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 901    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 902
 903    nv50_screen_init_resource_functions(pscreen);
 904
 905    if (screen->base.device->chipset < 0x84 ||
 906        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 907       /* PMPEG */
 908       nouveau_screen_init_vdec(&screen->base);
 909    } else if (screen->base.device->chipset < 0x98 ||
 910               screen->base.device->chipset == 0xa0) {
 911       /* VP2 */
 912       screen->base.base.get_video_param = nv84_screen_get_video_param;
 913       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 914    } else {
 915       /* VP3/4 */
 916       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 917       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 918    }
 919
 920    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 921                         NULL, &screen->fence.bo);
 922    if (ret) {
 923       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 924       goto fail;
 925    }
 926
 927    nouveau_bo_map(screen->fence.bo, 0, NULL);
 928    screen->fence.map = screen->fence.bo->map;
 929    screen->base.fence.emit = nv50_screen_fence_emit;
 930    screen->base.fence.update = nv50_screen_fence_update;
 931
 932    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 933                             &(struct nv04_notify){ .length = 32 },
 934                             sizeof(struct nv04_notify), &screen->sync);
 935    if (ret) {
 936       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 937       goto fail;
 938    }
 939
 940    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 941                             NULL, 0, &screen->m2mf);
 942    if (ret) {
 943       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 944       goto fail;
 945    }
 946
 947    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 948                             NULL, 0, &screen->eng2d);
 949    if (ret) {
 950       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 951       goto fail;
 952    }
 953
 954    switch (dev->chipset & 0xf0) {
 955    case 0x50:
 956       tesla_class = NV50_3D_CLASS;
 957       break;
 958    case 0x80:
 959    case 0x90:
 960       tesla_class = NV84_3D_CLASS;
 961       break;
 962    case 0xa0:
 963       switch (dev->chipset) {
 964       case 0xa0:
 965       case 0xaa:
 966       case 0xac:
 967          tesla_class = NVA0_3D_CLASS;
 968          break;
 969       case 0xaf:
 970          tesla_class = NVAF_3D_CLASS;
 971          break;
 972       default:
 973          tesla_class = NVA3_3D_CLASS;
 974          break;
 975       }
 976       break;
 977    default:
 978       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 979       goto fail;
 980    }
 981    screen->base.class_3d = tesla_class;
 982
 983    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 984                             NULL, 0, &screen->tesla);
 985    if (ret) {
 986       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 987       goto fail;
 988    }
 989
 990    /* This over-allocates by a page. The GP, which would execute at the end of
 991     * the last page, would trigger faults. The going theory is that it
 992     * prefetches up to a certain amount.
 993     */
 994    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 995                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 996                         NULL, &screen->code);
 997    if (ret) {
 998       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 999       goto fail;
1000    }
1001
1002    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1003    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1004    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1005
1006    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1007
1008    screen->TPs = util_bitcount(value & 0xffff);
1009    screen->MPsInTP = util_bitcount(value & 0x0f000000);
1010
1011    screen->mp_count = screen->TPs * screen->MPsInTP;
1012
1013    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1014          STACK_WARPS_ALLOC * 64 * 8;
1015
1016    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1017                         &screen->stack_bo);
1018    if (ret) {
1019       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1020       goto fail;
1021    }
1022
1023    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1024          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1025          ONE_TEMP_SIZE;
1026    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1027    screen->max_tls_space /= 2; /* half of vram */
1028
1029    /* hw can address max 64 KiB */
1030    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1031
1032    uint64_t tls_size;
1033    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1034    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1035    if (ret)
1036       goto fail;
1037
1038    if (nouveau_mesa_debug)
1039       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1040             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1041
1042    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1043                         &screen->uniforms);
1044    if (ret) {
1045       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1046       goto fail;
1047    }
1048
1049    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1050                         &screen->txc);
1051    if (ret) {
1052       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1053       goto fail;
1054    }
1055
1056    screen->tic.entries = CALLOC(4096, sizeof(void *));
1057    screen->tsc.entries = screen->tic.entries + 2048;
1058
1059    if (!nv50_blitter_create(screen))
1060       goto fail;
1061
1062    nv50_screen_init_hwctx(screen);
1063
1064    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1065    if (ret) {
1066       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1067       goto fail;
1068    }
1069
1070    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1071
1072    return &screen->base;
1073
1074 fail:
1075    screen->base.base.context_create = NULL;
1076    return &screen->base;
1077 }
1078
1079 int
1080 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1081 {
1082    int i = screen->tic.next;
1083
1084    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1085       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1086
1087    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1088
1089    if (screen->tic.entries[i])
1090       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1091
1092    screen->tic.entries[i] = entry;
1093    return i;
1094 }
1095
1096 int
1097 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1098 {
1099    int i = screen->tsc.next;
1100
1101    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1102       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1103
1104    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1105
1106    if (screen->tsc.entries[i])
1107       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1108
1109    screen->tsc.entries[i] = entry;
1110    return i;
1111 }