src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50/nv50_context.h"
  28 #include "nv50/nv50_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nv_object.xml.h"
  33 #include <errno.h>
  34
  35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  37 #endif
  38
  39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  40 #define LOCAL_WARPS_ALLOC 32
  41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  42 #define STACK_WARPS_ALLOC 32
  43
  44 #define THREADS_IN_WARP 32
  45
  46 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  47
  48 static boolean
  49 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  50                                 enum pipe_format format,
  51                                 enum pipe_texture_target target,
  52                                 unsigned sample_count,
  53                                 unsigned bindings)
  54 {
  55    if (sample_count > 8)
  56       return FALSE;
  57    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  58       return FALSE;
  59    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  60       return FALSE;
  61
  62    if (!util_format_is_supported(format, bindings))
  63       return FALSE;
  64
  65    switch (format) {
  66    case PIPE_FORMAT_Z16_UNORM:
  67       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  68          return FALSE;
  69       break;
  70    default:
  71       break;
  72    }
  73
  74    /* transfers & shared are always supported */
  75    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  76                  PIPE_BIND_TRANSFER_WRITE |
  77                  PIPE_BIND_SHARED);
  78
  79    return (nv50_format_table[format].usage & bindings) == bindings;
  80 }
  81
  82 static int
  83 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  84 {
  85    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  86
  87    switch (param) {
  88    /* non-boolean caps */
  89    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  90       return 14;
  91    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  92       return 12;
  93    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  94       return 14;
  95    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  96       return 512;
  97    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  98    case PIPE_CAP_MIN_TEXEL_OFFSET:
  99       return -8;
 100    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 101    case PIPE_CAP_MAX_TEXEL_OFFSET:
 102       return 7;
 103    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 104       return 65536;
 105    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 106       return 330;
 107    case PIPE_CAP_MAX_RENDER_TARGETS:
 108       return 8;
 109    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 110       return 1;
 111    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 112       return 4;
 113    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 114    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 115       return 64;
 116    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 117    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 118       return 1024;
 119    case PIPE_CAP_MAX_VERTEX_STREAMS:
 120       return 1;
 121    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 122       return 256;
 123    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 124       return 1; /* 256 for binding as RT, but that's not possible in GL */
 125    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 126       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 127    case PIPE_CAP_MAX_VIEWPORTS:
 128       return NV50_MAX_VIEWPORTS;
 129    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 130       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 131    case PIPE_CAP_ENDIANNESS:
 132       return PIPE_ENDIAN_LITTLE;
 133    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 134       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 135
 136    /* supported caps */
 137    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 138    case PIPE_CAP_TEXTURE_SWIZZLE:
 139    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 140    case PIPE_CAP_NPOT_TEXTURES:
 141    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 142    case PIPE_CAP_ANISOTROPIC_FILTER:
 143    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 144    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 145    case PIPE_CAP_TWO_SIDED_STENCIL:
 146    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 147    case PIPE_CAP_POINT_SPRITE:
 148    case PIPE_CAP_SM3:
 149    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 150    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 151    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 152    case PIPE_CAP_QUERY_TIMESTAMP:
 153    case PIPE_CAP_QUERY_TIME_ELAPSED:
 154    case PIPE_CAP_OCCLUSION_QUERY:
 155    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 156    case PIPE_CAP_INDEP_BLEND_ENABLE:
 157    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 158    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 159    case PIPE_CAP_PRIMITIVE_RESTART:
 160    case PIPE_CAP_TGSI_INSTANCEID:
 161    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 162    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 163    case PIPE_CAP_CONDITIONAL_RENDER:
 164    case PIPE_CAP_TEXTURE_BARRIER:
 165    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 166    case PIPE_CAP_START_INSTANCE:
 167    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 168    case PIPE_CAP_USER_INDEX_BUFFERS:
 169    case PIPE_CAP_USER_VERTEX_BUFFERS:
 170    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 171    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 172       return 1;
 173    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 174       return 1; /* class_3d >= NVA0_3D_CLASS; */
 175    /* supported on nva0+ */
 176    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 177       return class_3d >= NVA0_3D_CLASS;
 178    /* supported on nva3+ */
 179    case PIPE_CAP_CUBE_MAP_ARRAY:
 180    case PIPE_CAP_INDEP_BLEND_FUNC:
 181    case PIPE_CAP_TEXTURE_QUERY_LOD:
 182    case PIPE_CAP_SAMPLE_SHADING:
 183       return class_3d >= NVA3_3D_CLASS;
 184
 185    /* unsupported caps */
 186    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 187    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 188    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 189    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 190    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 191    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 192    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 193    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 194    case PIPE_CAP_TGSI_TEXCOORD:
 195    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 196    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 197    case PIPE_CAP_TEXTURE_GATHER_SM5:
 198    case PIPE_CAP_FAKE_SW_MSAA:
 199    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 200    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 201    case PIPE_CAP_COMPUTE:
 202    case PIPE_CAP_DRAW_INDIRECT:
 203       return 0;
 204    }
 205
 206    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 207    return 0;
 208 }
 209
 210 static int
 211 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 212                              enum pipe_shader_cap param)
 213 {
 214    switch (shader) {
 215    case PIPE_SHADER_VERTEX:
 216    case PIPE_SHADER_GEOMETRY:
 217    case PIPE_SHADER_FRAGMENT:
 218       break;
 219    default:
 220       return 0;
 221    }
 222
 223    switch (param) {
 224    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 225    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 226    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 227    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 228       return 16384;
 229    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 230       return 4;
 231    case PIPE_SHADER_CAP_MAX_INPUTS:
 232       if (shader == PIPE_SHADER_VERTEX)
 233          return 32;
 234       return 15;
 235    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 236       return 65536;
 237    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 238       return NV50_MAX_PIPE_CONSTBUFS;
 239    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 240    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 241       return shader != PIPE_SHADER_FRAGMENT;
 242    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 243    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 244       return 1;
 245    case PIPE_SHADER_CAP_MAX_PREDS:
 246       return 0;
 247    case PIPE_SHADER_CAP_MAX_TEMPS:
 248       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 249    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 250       return 1;
 251    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 252       return 0;
 253    case PIPE_SHADER_CAP_SUBROUTINES:
 254       return 0; /* please inline, or provide function declarations */
 255    case PIPE_SHADER_CAP_INTEGERS:
 256       return 1;
 257    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 258       /* The chip could handle more sampler views than samplers */
 259    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 260       return MIN2(32, PIPE_MAX_SAMPLERS);
 261    default:
 262       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 263       return 0;
 264    }
 265 }
 266
 267 static float
 268 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 269 {
 270    switch (param) {
 271    case PIPE_CAPF_MAX_LINE_WIDTH:
 272    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 273       return 10.0f;
 274    case PIPE_CAPF_MAX_POINT_WIDTH:
 275    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 276       return 64.0f;
 277    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 278       return 16.0f;
 279    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 280       return 4.0f;
 281    case PIPE_CAPF_GUARD_BAND_LEFT:
 282    case PIPE_CAPF_GUARD_BAND_TOP:
 283       return 0.0f;
 284    case PIPE_CAPF_GUARD_BAND_RIGHT:
 285    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 286       return 0.0f; /* that or infinity */
 287    }
 288
 289    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 290    return 0.0f;
 291 }
 292
 293 static void
 294 nv50_screen_destroy(struct pipe_screen *pscreen)
 295 {
 296    struct nv50_screen *screen = nv50_screen(pscreen);
 297
 298    if (!nouveau_drm_screen_unref(&screen->base))
 299       return;
 300
 301    if (screen->base.fence.current) {
 302       struct nouveau_fence *current = NULL;
 303
 304       /* nouveau_fence_wait will create a new current fence, so wait on the
 305        * _current_ one, and remove both.
 306        */
 307       nouveau_fence_ref(screen->base.fence.current, &current);
 308       nouveau_fence_wait(current);
 309       nouveau_fence_ref(NULL, &current);
 310       nouveau_fence_ref(NULL, &screen->base.fence.current);
 311    }
 312    if (screen->base.pushbuf)
 313       screen->base.pushbuf->user_priv = NULL;
 314
 315    if (screen->blitter)
 316       nv50_blitter_destroy(screen);
 317
 318    nouveau_bo_ref(NULL, &screen->code);
 319    nouveau_bo_ref(NULL, &screen->tls_bo);
 320    nouveau_bo_ref(NULL, &screen->stack_bo);
 321    nouveau_bo_ref(NULL, &screen->txc);
 322    nouveau_bo_ref(NULL, &screen->uniforms);
 323    nouveau_bo_ref(NULL, &screen->fence.bo);
 324
 325    nouveau_heap_destroy(&screen->vp_code_heap);
 326    nouveau_heap_destroy(&screen->gp_code_heap);
 327    nouveau_heap_destroy(&screen->fp_code_heap);
 328
 329    FREE(screen->tic.entries);
 330
 331    nouveau_object_del(&screen->tesla);
 332    nouveau_object_del(&screen->eng2d);
 333    nouveau_object_del(&screen->m2mf);
 334    nouveau_object_del(&screen->sync);
 335
 336    nouveau_screen_fini(&screen->base);
 337
 338    FREE(screen);
 339 }
 340
 341 static void
 342 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 343 {
 344    struct nv50_screen *screen = nv50_screen(pscreen);
 345    struct nouveau_pushbuf *push = screen->base.pushbuf;
 346
 347    /* we need to do it after possible flush in MARK_RING */
 348    *sequence = ++screen->base.fence.sequence;
 349
 350    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 351    PUSH_DATAh(push, screen->fence.bo->offset);
 352    PUSH_DATA (push, screen->fence.bo->offset);
 353    PUSH_DATA (push, *sequence);
 354    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 355                     NV50_3D_QUERY_GET_UNK4 |
 356                     NV50_3D_QUERY_GET_UNIT_CROP |
 357                     NV50_3D_QUERY_GET_TYPE_QUERY |
 358                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 359                     NV50_3D_QUERY_GET_SHORT);
 360 }
 361
 362 static u32
 363 nv50_screen_fence_update(struct pipe_screen *pscreen)
 364 {
 365    return nv50_screen(pscreen)->fence.map[0];
 366 }
 367
 368 static void
 369 nv50_screen_init_hwctx(struct nv50_screen *screen)
 370 {
 371    struct nouveau_pushbuf *push = screen->base.pushbuf;
 372    struct nv04_fifo *fifo;
 373    unsigned i;
 374
 375    fifo = (struct nv04_fifo *)screen->base.channel->data;
 376
 377    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 378    PUSH_DATA (push, screen->m2mf->handle);
 379    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 380    PUSH_DATA (push, screen->sync->handle);
 381    PUSH_DATA (push, fifo->vram);
 382    PUSH_DATA (push, fifo->vram);
 383
 384    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 385    PUSH_DATA (push, screen->eng2d->handle);
 386    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 387    PUSH_DATA (push, screen->sync->handle);
 388    PUSH_DATA (push, fifo->vram);
 389    PUSH_DATA (push, fifo->vram);
 390    PUSH_DATA (push, fifo->vram);
 391    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 392    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 393    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 394    PUSH_DATA (push, 0);
 395    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 396    PUSH_DATA (push, 0);
 397    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 398    PUSH_DATA (push, 1);
 399    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 400    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 401
 402    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 403    PUSH_DATA (push, screen->tesla->handle);
 404
 405    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 406    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 407
 408    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 409    PUSH_DATA (push, screen->sync->handle);
 410    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 411    for (i = 0; i < 11; ++i)
 412       PUSH_DATA(push, fifo->vram);
 413    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 414    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 415       PUSH_DATA(push, fifo->vram);
 416
 417    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 418    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 419    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 420    PUSH_DATA (push, 0xf);
 421
 422    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 423       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 424       PUSH_DATA (push, 0x18);
 425    }
 426
 427    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 428    PUSH_DATA (push, 1);
 429
 430    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 431    PUSH_DATA (push, 0);
 432    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 433    PUSH_DATA (push, 0);
 434    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 435    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 436    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 437    PUSH_DATA (push, 0);
 438    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 439    PUSH_DATA (push, 1);
 440    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 441    PUSH_DATA (push, 0);
 442    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 443    PUSH_DATA (push, 1);
 444
 445    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 446       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 447       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 448    }
 449
 450    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 451    PUSH_DATA (push, 0);
 452    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 453    PUSH_DATA (push, 0);
 454    PUSH_DATA (push, 0);
 455    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 456    PUSH_DATA (push, 0x3f);
 457
 458    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 459    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 460    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 461
 462    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 463    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 464    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 465
 466    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 467    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 468    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 469
 470    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 471    PUSH_DATAh(push, screen->tls_bo->offset);
 472    PUSH_DATA (push, screen->tls_bo->offset);
 473    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 474
 475    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 476    PUSH_DATAh(push, screen->stack_bo->offset);
 477    PUSH_DATA (push, screen->stack_bo->offset);
 478    PUSH_DATA (push, 4);
 479
 480    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 481    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 482    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 483    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 484
 485    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 486    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 487    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 488    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 489
 490    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 491    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 492    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 493    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 494
 495    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 496    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 497    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 498    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 499
 500    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 501    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 502    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 503    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 504
 505    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 506    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 507    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 508    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 509    PUSH_DATAf(push, 0.0f);
 510    PUSH_DATAf(push, 0.0f);
 511    PUSH_DATAf(push, 0.0f);
 512    PUSH_DATAf(push, 0.0f);
 513    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 514    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 515    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 516
 517    nv50_upload_ms_info(push);
 518
 519    /* max TIC (bits 4:8) & TSC bindings, per program type */
 520    for (i = 0; i < 3; ++i) {
 521       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 522       PUSH_DATA (push, 0x54);
 523    }
 524
 525    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 526    PUSH_DATAh(push, screen->txc->offset);
 527    PUSH_DATA (push, screen->txc->offset);
 528    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 529
 530    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 531    PUSH_DATAh(push, screen->txc->offset + 65536);
 532    PUSH_DATA (push, screen->txc->offset + 65536);
 533    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 534
 535    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 536    PUSH_DATA (push, 0);
 537
 538    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 539    PUSH_DATA (push, 0);
 540    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 541    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 542    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 543    for (i = 0; i < 8 * 2; ++i)
 544       PUSH_DATA(push, 0);
 545    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 546    PUSH_DATA (push, 0);
 547
 548    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 549    PUSH_DATA (push, 1);
 550    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 551       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 552       PUSH_DATAf(push, 0.0f);
 553       PUSH_DATAf(push, 1.0f);
 554       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 555       PUSH_DATA (push, 8192 << 16);
 556       PUSH_DATA (push, 8192 << 16);
 557    }
 558
 559    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 560 #ifdef NV50_SCISSORS_CLIPPING
 561    PUSH_DATA (push, 0x0000);
 562 #else
 563    PUSH_DATA (push, 0x1080);
 564 #endif
 565
 566    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 567    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 568
 569    /* We use scissors instead of exact view volume clipping,
 570     * so they're always enabled.
 571     */
 572    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 573       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 574       PUSH_DATA (push, 1);
 575       PUSH_DATA (push, 8192 << 16);
 576       PUSH_DATA (push, 8192 << 16);
 577    }
 578
 579    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 580    PUSH_DATA (push, 1);
 581    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 582    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 583    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 584    PUSH_DATA (push, 0x11111111);
 585    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 586    PUSH_DATA (push, 1);
 587
 588    PUSH_KICK (push);
 589 }
 590
 591 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 592       uint64_t *tls_size)
 593 {
 594    struct nouveau_device *dev = screen->base.device;
 595    int ret;
 596
 597    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 598          ONE_TEMP_SIZE;
 599    if (nouveau_mesa_debug)
 600       debug_printf("allocating space for %u temps\n",
 601             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 602    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 603          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 604
 605    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 606                         *tls_size, NULL, &screen->tls_bo);
 607    if (ret) {
 608       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 609       return ret;
 610    }
 611
 612    return 0;
 613 }
 614
 615 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 616 {
 617    struct nouveau_pushbuf *push = screen->base.pushbuf;
 618    int ret;
 619    uint64_t tls_size;
 620
 621    if (tls_space < screen->cur_tls_space)
 622       return 0;
 623    if (tls_space > screen->max_tls_space) {
 624       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 625        * LOCAL_WARPS_NO_CLAMP) */
 626       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 627             (unsigned)(tls_space / ONE_TEMP_SIZE),
 628             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 629       return -ENOMEM;
 630    }
 631
 632    nouveau_bo_ref(NULL, &screen->tls_bo);
 633    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 634    if (ret)
 635       return ret;
 636
 637    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 638    PUSH_DATAh(push, screen->tls_bo->offset);
 639    PUSH_DATA (push, screen->tls_bo->offset);
 640    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 641
 642    return 1;
 643 }
 644
 645 struct pipe_screen *
 646 nv50_screen_create(struct nouveau_device *dev)
 647 {
 648    struct nv50_screen *screen;
 649    struct pipe_screen *pscreen;
 650    struct nouveau_object *chan;
 651    uint64_t value;
 652    uint32_t tesla_class;
 653    unsigned stack_size;
 654    int ret;
 655
 656    screen = CALLOC_STRUCT(nv50_screen);
 657    if (!screen)
 658       return NULL;
 659    pscreen = &screen->base.base;
 660
 661    ret = nouveau_screen_init(&screen->base, dev);
 662    if (ret) {
 663       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 664       goto fail;
 665    }
 666
 667    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 668     *  admit them to VRAM.
 669     */
 670    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 671       PIPE_BIND_VERTEX_BUFFER;
 672    screen->base.sysmem_bindings |=
 673       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 674
 675    screen->base.pushbuf->user_priv = screen;
 676    screen->base.pushbuf->rsvd_kick = 5;
 677
 678    chan = screen->base.channel;
 679
 680    pscreen->destroy = nv50_screen_destroy;
 681    pscreen->context_create = nv50_create;
 682    pscreen->is_format_supported = nv50_screen_is_format_supported;
 683    pscreen->get_param = nv50_screen_get_param;
 684    pscreen->get_shader_param = nv50_screen_get_shader_param;
 685    pscreen->get_paramf = nv50_screen_get_paramf;
 686
 687    nv50_screen_init_resource_functions(pscreen);
 688
 689    if (screen->base.device->chipset < 0x84 ||
 690        debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
 691       /* PMPEG */
 692       nouveau_screen_init_vdec(&screen->base);
 693    } else if (screen->base.device->chipset < 0x98 ||
 694               screen->base.device->chipset == 0xa0) {
 695       /* VP2 */
 696       screen->base.base.get_video_param = nv84_screen_get_video_param;
 697       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 698    } else {
 699       /* VP3/4 */
 700       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 701       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 702    }
 703
 704    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 705                         NULL, &screen->fence.bo);
 706    if (ret) {
 707       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 708       goto fail;
 709    }
 710
 711    nouveau_bo_map(screen->fence.bo, 0, NULL);
 712    screen->fence.map = screen->fence.bo->map;
 713    screen->base.fence.emit = nv50_screen_fence_emit;
 714    screen->base.fence.update = nv50_screen_fence_update;
 715
 716    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 717                             &(struct nv04_notify){ .length = 32 },
 718                             sizeof(struct nv04_notify), &screen->sync);
 719    if (ret) {
 720       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 721       goto fail;
 722    }
 723
 724    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 725                             NULL, 0, &screen->m2mf);
 726    if (ret) {
 727       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 728       goto fail;
 729    }
 730
 731    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 732                             NULL, 0, &screen->eng2d);
 733    if (ret) {
 734       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 735       goto fail;
 736    }
 737
 738    switch (dev->chipset & 0xf0) {
 739    case 0x50:
 740       tesla_class = NV50_3D_CLASS;
 741       break;
 742    case 0x80:
 743    case 0x90:
 744       tesla_class = NV84_3D_CLASS;
 745       break;
 746    case 0xa0:
 747       switch (dev->chipset) {
 748       case 0xa0:
 749       case 0xaa:
 750       case 0xac:
 751          tesla_class = NVA0_3D_CLASS;
 752          break;
 753       case 0xaf:
 754          tesla_class = NVAF_3D_CLASS;
 755          break;
 756       default:
 757          tesla_class = NVA3_3D_CLASS;
 758          break;
 759       }
 760       break;
 761    default:
 762       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 763       goto fail;
 764    }
 765    screen->base.class_3d = tesla_class;
 766
 767    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 768                             NULL, 0, &screen->tesla);
 769    if (ret) {
 770       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 771       goto fail;
 772    }
 773
 774    /* This over-allocates by a page. The GP, which would execute at the end of
 775     * the last page, would trigger faults. The going theory is that it
 776     * prefetches up to a certain amount.
 777     */
 778    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 779                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 780                         NULL, &screen->code);
 781    if (ret) {
 782       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 783       goto fail;
 784    }
 785
 786    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 787    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 788    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 789
 790    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 791
 792    screen->TPs = util_bitcount(value & 0xffff);
 793    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 794
 795    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 796          STACK_WARPS_ALLOC * 64 * 8;
 797
 798    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 799                         &screen->stack_bo);
 800    if (ret) {
 801       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 802       goto fail;
 803    }
 804
 805    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 806          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 807          ONE_TEMP_SIZE;
 808    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 809    screen->max_tls_space /= 2; /* half of vram */
 810
 811    /* hw can address max 64 KiB */
 812    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 813
 814    uint64_t tls_size;
 815    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 816    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 817    if (ret)
 818       goto fail;
 819
 820    if (nouveau_mesa_debug)
 821       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 822             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 823
 824    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 825                         &screen->uniforms);
 826    if (ret) {
 827       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 828       goto fail;
 829    }
 830
 831    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 832                         &screen->txc);
 833    if (ret) {
 834       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 835       goto fail;
 836    }
 837
 838    screen->tic.entries = CALLOC(4096, sizeof(void *));
 839    screen->tsc.entries = screen->tic.entries + 2048;
 840
 841    if (!nv50_blitter_create(screen))
 842       goto fail;
 843
 844    nv50_screen_init_hwctx(screen);
 845
 846    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 847
 848    return pscreen;
 849
 850 fail:
 851    nv50_screen_destroy(pscreen);
 852    return NULL;
 853 }
 854
 855 int
 856 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 857 {
 858    int i = screen->tic.next;
 859
 860    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 861       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 862
 863    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 864
 865    if (screen->tic.entries[i])
 866       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 867
 868    screen->tic.entries[i] = entry;
 869    return i;
 870 }
 871
 872 int
 873 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 874 {
 875    int i = screen->tsc.next;
 876
 877    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 878       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 879
 880    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 881
 882    if (screen->tsc.entries[i])
 883       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 884
 885    screen->tsc.entries[i] = entry;
 886    return i;
 887 }