src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    /* transfers & shared are always supported */
  71    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  72                  PIPE_BIND_TRANSFER_WRITE |
  73                  PIPE_BIND_SHARED);
  74
  75    return (nv50_format_table[format].usage & bindings) == bindings;
  76 }
  77
  78 static int
  79 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  80 {
  81    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  82    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  83
  84    switch (param) {
  85    /* non-boolean caps */
  86    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  87       return 14;
  88    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  89       return 12;
  90    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  91       return 14;
  92    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  93       return 512;
  94    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  95    case PIPE_CAP_MIN_TEXEL_OFFSET:
  96       return -8;
  97    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  98    case PIPE_CAP_MAX_TEXEL_OFFSET:
  99       return 7;
 100    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 101       return 128 * 1024 * 1024;
 102    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 103       return 330;
 104    case PIPE_CAP_MAX_RENDER_TARGETS:
 105       return 8;
 106    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 107       return 1;
 108    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 109       return 4;
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 111    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 112       return 64;
 113    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 114    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 115       return 1024;
 116    case PIPE_CAP_MAX_VERTEX_STREAMS:
 117       return 1;
 118    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 119       return 2048;
 120    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 121       return 256;
 122    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 123       return 1; /* 256 for binding as RT, but that's not possible in GL */
 124    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 125       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 126    case PIPE_CAP_MAX_VIEWPORTS:
 127       return NV50_MAX_VIEWPORTS;
 128    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 129       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 130    case PIPE_CAP_ENDIANNESS:
 131       return PIPE_ENDIAN_LITTLE;
 132    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 133       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 134
 135    /* supported caps */
 136    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 137    case PIPE_CAP_TEXTURE_SWIZZLE:
 138    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 139    case PIPE_CAP_NPOT_TEXTURES:
 140    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 141    case PIPE_CAP_ANISOTROPIC_FILTER:
 142    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 143    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 144    case PIPE_CAP_TWO_SIDED_STENCIL:
 145    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 146    case PIPE_CAP_POINT_SPRITE:
 147    case PIPE_CAP_SM3:
 148    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 149    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 150    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 151    case PIPE_CAP_QUERY_TIMESTAMP:
 152    case PIPE_CAP_QUERY_TIME_ELAPSED:
 153    case PIPE_CAP_OCCLUSION_QUERY:
 154    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 155    case PIPE_CAP_INDEP_BLEND_ENABLE:
 156    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 157    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 158    case PIPE_CAP_PRIMITIVE_RESTART:
 159    case PIPE_CAP_TGSI_INSTANCEID:
 160    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 161    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 162    case PIPE_CAP_CONDITIONAL_RENDER:
 163    case PIPE_CAP_TEXTURE_BARRIER:
 164    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 165    case PIPE_CAP_START_INSTANCE:
 166    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 167    case PIPE_CAP_USER_INDEX_BUFFERS:
 168    case PIPE_CAP_USER_VERTEX_BUFFERS:
 169    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 170    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 171    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 172    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 173    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 174    case PIPE_CAP_CLIP_HALFZ:
 175    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 176    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 177    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 178    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 179    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 180    case PIPE_CAP_TGSI_TXQS:
 181    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 182    case PIPE_CAP_SHAREABLE_SHADERS:
 183    case PIPE_CAP_CLEAR_TEXTURE:
 184    case PIPE_CAP_COMPUTE:
 185       return 1;
 186    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 187       return 1; /* class_3d >= NVA0_3D_CLASS; */
 188    /* supported on nva0+ */
 189    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 190       return class_3d >= NVA0_3D_CLASS;
 191    /* supported on nva3+ */
 192    case PIPE_CAP_CUBE_MAP_ARRAY:
 193    case PIPE_CAP_INDEP_BLEND_FUNC:
 194    case PIPE_CAP_TEXTURE_QUERY_LOD:
 195    case PIPE_CAP_SAMPLE_SHADING:
 196    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 197       return class_3d >= NVA3_3D_CLASS;
 198
 199    /* unsupported caps */
 200    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 201    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 202    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 203    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 204    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 205    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 206    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 207    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 208    case PIPE_CAP_TGSI_TEXCOORD:
 209    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 210    case PIPE_CAP_TEXTURE_GATHER_SM5:
 211    case PIPE_CAP_FAKE_SW_MSAA:
 212    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 213    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 214    case PIPE_CAP_DRAW_INDIRECT:
 215    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 216    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 217    case PIPE_CAP_VERTEXID_NOBASE:
 218    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 219    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 220    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 221    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 222    case PIPE_CAP_DRAW_PARAMETERS:
 223    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 224       return 0;
 225
 226    case PIPE_CAP_VENDOR_ID:
 227       return 0x10de;
 228    case PIPE_CAP_DEVICE_ID: {
 229       uint64_t device_id;
 230       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 231          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 232          return -1;
 233       }
 234       return device_id;
 235    }
 236    case PIPE_CAP_ACCELERATED:
 237       return 1;
 238    case PIPE_CAP_VIDEO_MEMORY:
 239       return dev->vram_size >> 20;
 240    case PIPE_CAP_UMA:
 241       return 0;
 242    }
 243
 244    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 245    return 0;
 246 }
 247
 248 static int
 249 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 250                              enum pipe_shader_cap param)
 251 {
 252    switch (shader) {
 253    case PIPE_SHADER_VERTEX:
 254    case PIPE_SHADER_GEOMETRY:
 255    case PIPE_SHADER_FRAGMENT:
 256    case PIPE_SHADER_COMPUTE:
 257       break;
 258    default:
 259       return 0;
 260    }
 261
 262    switch (param) {
 263    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 264    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 265    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 266    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 267       return 16384;
 268    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 269       return 4;
 270    case PIPE_SHADER_CAP_MAX_INPUTS:
 271       if (shader == PIPE_SHADER_VERTEX)
 272          return 32;
 273       return 15;
 274    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 275       return 16;
 276    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 277       return 65536;
 278    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 279       return NV50_MAX_PIPE_CONSTBUFS;
 280    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 281    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 282       return shader != PIPE_SHADER_FRAGMENT;
 283    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 284    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 285       return 1;
 286    case PIPE_SHADER_CAP_MAX_PREDS:
 287       return 0;
 288    case PIPE_SHADER_CAP_MAX_TEMPS:
 289       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 290    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 291       return 1;
 292    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 293       return 0;
 294    case PIPE_SHADER_CAP_SUBROUTINES:
 295       return 0; /* please inline, or provide function declarations */
 296    case PIPE_SHADER_CAP_INTEGERS:
 297       return 1;
 298    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 299       /* The chip could handle more sampler views than samplers */
 300    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 301       return MIN2(16, PIPE_MAX_SAMPLERS);
 302    case PIPE_SHADER_CAP_DOUBLES:
 303    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 304    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 305    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 306    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 307       return 0;
 308    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 309       return 32;
 310    default:
 311       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 312       return 0;
 313    }
 314 }
 315
 316 static float
 317 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 318 {
 319    switch (param) {
 320    case PIPE_CAPF_MAX_LINE_WIDTH:
 321    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 322       return 10.0f;
 323    case PIPE_CAPF_MAX_POINT_WIDTH:
 324    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 325       return 64.0f;
 326    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 327       return 16.0f;
 328    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 329       return 4.0f;
 330    case PIPE_CAPF_GUARD_BAND_LEFT:
 331    case PIPE_CAPF_GUARD_BAND_TOP:
 332       return 0.0f;
 333    case PIPE_CAPF_GUARD_BAND_RIGHT:
 334    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 335       return 0.0f; /* that or infinity */
 336    }
 337
 338    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 339    return 0.0f;
 340 }
 341
 342 static int
 343 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 344                               enum pipe_compute_cap param, void *data)
 345 {
 346    struct nv50_screen *screen = nv50_screen(pscreen);
 347
 348 #define RET(x) do {                  \
 349    if (data)                         \
 350       memcpy(data, x, sizeof(x));    \
 351    return sizeof(x);                 \
 352 } while (0)
 353
 354    switch (param) {
 355    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 356       RET((uint64_t []) { 2 });
 357    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 358       RET(((uint64_t []) { 65535, 65535 }));
 359    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 360       RET(((uint64_t []) { 512, 512, 64 }));
 361    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 362       RET((uint64_t []) { 512 });
 363    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 364       RET((uint64_t []) { 1ULL << 32 });
 365    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 366       RET((uint64_t []) { 16 << 10 });
 367    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 368       RET((uint64_t []) { 16 << 10 });
 369    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 370       RET((uint64_t []) { 4096 });
 371    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 372       RET((uint32_t []) { 32 });
 373    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 374       RET((uint64_t []) { 1ULL << 40 });
 375    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 376       RET((uint32_t []) { 0 });
 377    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 378       RET((uint32_t []) { screen->mp_count });
 379    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 380       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 381    default:
 382       return 0;
 383    }
 384
 385 #undef RET
 386 }
 387
 388 static void
 389 nv50_screen_destroy(struct pipe_screen *pscreen)
 390 {
 391    struct nv50_screen *screen = nv50_screen(pscreen);
 392
 393    if (!nouveau_drm_screen_unref(&screen->base))
 394       return;
 395
 396    if (screen->base.fence.current) {
 397       struct nouveau_fence *current = NULL;
 398
 399       /* nouveau_fence_wait will create a new current fence, so wait on the
 400        * _current_ one, and remove both.
 401        */
 402       nouveau_fence_ref(screen->base.fence.current, &current);
 403       nouveau_fence_wait(current, NULL);
 404       nouveau_fence_ref(NULL, &current);
 405       nouveau_fence_ref(NULL, &screen->base.fence.current);
 406    }
 407    if (screen->base.pushbuf)
 408       screen->base.pushbuf->user_priv = NULL;
 409
 410    if (screen->blitter)
 411       nv50_blitter_destroy(screen);
 412    if (screen->pm.prog) {
 413       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 414       nv50_program_destroy(NULL, screen->pm.prog);
 415       FREE(screen->pm.prog);
 416    }
 417
 418    nouveau_bo_ref(NULL, &screen->code);
 419    nouveau_bo_ref(NULL, &screen->tls_bo);
 420    nouveau_bo_ref(NULL, &screen->stack_bo);
 421    nouveau_bo_ref(NULL, &screen->txc);
 422    nouveau_bo_ref(NULL, &screen->uniforms);
 423    nouveau_bo_ref(NULL, &screen->fence.bo);
 424
 425    nouveau_heap_destroy(&screen->vp_code_heap);
 426    nouveau_heap_destroy(&screen->gp_code_heap);
 427    nouveau_heap_destroy(&screen->fp_code_heap);
 428
 429    FREE(screen->tic.entries);
 430
 431    nouveau_object_del(&screen->tesla);
 432    nouveau_object_del(&screen->eng2d);
 433    nouveau_object_del(&screen->m2mf);
 434    nouveau_object_del(&screen->compute);
 435    nouveau_object_del(&screen->sync);
 436
 437    nouveau_screen_fini(&screen->base);
 438
 439    FREE(screen);
 440 }
 441
 442 static void
 443 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 444 {
 445    struct nv50_screen *screen = nv50_screen(pscreen);
 446    struct nouveau_pushbuf *push = screen->base.pushbuf;
 447
 448    /* we need to do it after possible flush in MARK_RING */
 449    *sequence = ++screen->base.fence.sequence;
 450
 451    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 452    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 453    PUSH_DATAh(push, screen->fence.bo->offset);
 454    PUSH_DATA (push, screen->fence.bo->offset);
 455    PUSH_DATA (push, *sequence);
 456    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 457                     NV50_3D_QUERY_GET_UNK4 |
 458                     NV50_3D_QUERY_GET_UNIT_CROP |
 459                     NV50_3D_QUERY_GET_TYPE_QUERY |
 460                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 461                     NV50_3D_QUERY_GET_SHORT);
 462 }
 463
 464 static u32
 465 nv50_screen_fence_update(struct pipe_screen *pscreen)
 466 {
 467    return nv50_screen(pscreen)->fence.map[0];
 468 }
 469
 470 static void
 471 nv50_screen_init_hwctx(struct nv50_screen *screen)
 472 {
 473    struct nouveau_pushbuf *push = screen->base.pushbuf;
 474    struct nv04_fifo *fifo;
 475    unsigned i;
 476
 477    fifo = (struct nv04_fifo *)screen->base.channel->data;
 478
 479    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 480    PUSH_DATA (push, screen->m2mf->handle);
 481    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 482    PUSH_DATA (push, screen->sync->handle);
 483    PUSH_DATA (push, fifo->vram);
 484    PUSH_DATA (push, fifo->vram);
 485
 486    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 487    PUSH_DATA (push, screen->eng2d->handle);
 488    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 489    PUSH_DATA (push, screen->sync->handle);
 490    PUSH_DATA (push, fifo->vram);
 491    PUSH_DATA (push, fifo->vram);
 492    PUSH_DATA (push, fifo->vram);
 493    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 494    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 495    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 496    PUSH_DATA (push, 0);
 497    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 498    PUSH_DATA (push, 0);
 499    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 500    PUSH_DATA (push, 1);
 501    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 502    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 503
 504    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 505    PUSH_DATA (push, screen->tesla->handle);
 506
 507    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 508    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 509
 510    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 511    PUSH_DATA (push, screen->sync->handle);
 512    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 513    for (i = 0; i < 11; ++i)
 514       PUSH_DATA(push, fifo->vram);
 515    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 516    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 517       PUSH_DATA(push, fifo->vram);
 518
 519    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 520    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 521    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 522    PUSH_DATA (push, 0xf);
 523
 524    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 525       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 526       PUSH_DATA (push, 0x18);
 527    }
 528
 529    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 530    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 531
 532    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 533    for (i = 0; i < 8; ++i)
 534       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 535
 536    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 537    PUSH_DATA (push, 1);
 538
 539    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 540    PUSH_DATA (push, 0);
 541    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 542    PUSH_DATA (push, 0);
 543    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 544    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 545    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 546    PUSH_DATA (push, 0);
 547    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 548    PUSH_DATA (push, 1);
 549    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 550    PUSH_DATA (push, 1);
 551
 552    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 553       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 554       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 555    }
 556
 557    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 558    PUSH_DATA (push, 0);
 559    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 560    PUSH_DATA (push, 0);
 561    PUSH_DATA (push, 0);
 562    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 563    PUSH_DATA (push, 0x3f);
 564
 565    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 566    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 567    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 568
 569    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 570    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 571    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 572
 573    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 574    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 575    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 576
 577    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 578    PUSH_DATAh(push, screen->tls_bo->offset);
 579    PUSH_DATA (push, screen->tls_bo->offset);
 580    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 581
 582    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 583    PUSH_DATAh(push, screen->stack_bo->offset);
 584    PUSH_DATA (push, screen->stack_bo->offset);
 585    PUSH_DATA (push, 4);
 586
 587    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 588    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 589    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 590    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 591
 592    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 593    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 594    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 595    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 596
 597    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 598    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 599    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 600    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 601
 602    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 603    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 604    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 605    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 606
 607    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 608    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 609    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 610    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 611
 612    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 613    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 614    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 615    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 616    PUSH_DATAf(push, 0.0f);
 617    PUSH_DATAf(push, 0.0f);
 618    PUSH_DATAf(push, 0.0f);
 619    PUSH_DATAf(push, 0.0f);
 620    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 621    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 622    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 623
 624    nv50_upload_ms_info(push);
 625
 626    /* max TIC (bits 4:8) & TSC bindings, per program type */
 627    for (i = 0; i < 3; ++i) {
 628       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 629       PUSH_DATA (push, 0x54);
 630    }
 631
 632    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 633    PUSH_DATAh(push, screen->txc->offset);
 634    PUSH_DATA (push, screen->txc->offset);
 635    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 636
 637    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 638    PUSH_DATAh(push, screen->txc->offset + 65536);
 639    PUSH_DATA (push, screen->txc->offset + 65536);
 640    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 641
 642    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 643    PUSH_DATA (push, 0);
 644
 645    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 646    PUSH_DATA (push, 0);
 647    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 648    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 649    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 650    for (i = 0; i < 8 * 2; ++i)
 651       PUSH_DATA(push, 0);
 652    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 653    PUSH_DATA (push, 0);
 654
 655    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 656    PUSH_DATA (push, 1);
 657    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 658       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 659       PUSH_DATAf(push, 0.0f);
 660       PUSH_DATAf(push, 1.0f);
 661       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 662       PUSH_DATA (push, 8192 << 16);
 663       PUSH_DATA (push, 8192 << 16);
 664    }
 665
 666    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 667 #ifdef NV50_SCISSORS_CLIPPING
 668    PUSH_DATA (push, 0x0000);
 669 #else
 670    PUSH_DATA (push, 0x1080);
 671 #endif
 672
 673    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 674    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 675
 676    /* We use scissors instead of exact view volume clipping,
 677     * so they're always enabled.
 678     */
 679    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 680       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 681       PUSH_DATA (push, 1);
 682       PUSH_DATA (push, 8192 << 16);
 683       PUSH_DATA (push, 8192 << 16);
 684    }
 685
 686    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 687    PUSH_DATA (push, 1);
 688    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 689    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 690    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 691    PUSH_DATA (push, 0x11111111);
 692    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 693    PUSH_DATA (push, 1);
 694
 695    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 696    PUSH_DATA (push, 0);
 697    if (screen->base.class_3d >= NV84_3D_CLASS) {
 698       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 699       PUSH_DATA (push, 0);
 700    }
 701
 702    PUSH_KICK (push);
 703 }
 704
 705 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 706       uint64_t *tls_size)
 707 {
 708    struct nouveau_device *dev = screen->base.device;
 709    int ret;
 710
 711    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 712          ONE_TEMP_SIZE;
 713    if (nouveau_mesa_debug)
 714       debug_printf("allocating space for %u temps\n",
 715             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 716    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 717          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 718
 719    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 720                         *tls_size, NULL, &screen->tls_bo);
 721    if (ret) {
 722       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 723       return ret;
 724    }
 725
 726    return 0;
 727 }
 728
 729 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 730 {
 731    struct nouveau_pushbuf *push = screen->base.pushbuf;
 732    int ret;
 733    uint64_t tls_size;
 734
 735    if (tls_space < screen->cur_tls_space)
 736       return 0;
 737    if (tls_space > screen->max_tls_space) {
 738       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 739        * LOCAL_WARPS_NO_CLAMP) */
 740       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 741             (unsigned)(tls_space / ONE_TEMP_SIZE),
 742             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 743       return -ENOMEM;
 744    }
 745
 746    nouveau_bo_ref(NULL, &screen->tls_bo);
 747    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 748    if (ret)
 749       return ret;
 750
 751    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 752    PUSH_DATAh(push, screen->tls_bo->offset);
 753    PUSH_DATA (push, screen->tls_bo->offset);
 754    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 755
 756    return 1;
 757 }
 758
 759 struct nouveau_screen *
 760 nv50_screen_create(struct nouveau_device *dev)
 761 {
 762    struct nv50_screen *screen;
 763    struct pipe_screen *pscreen;
 764    struct nouveau_object *chan;
 765    uint64_t value;
 766    uint32_t tesla_class;
 767    unsigned stack_size;
 768    int ret;
 769
 770    screen = CALLOC_STRUCT(nv50_screen);
 771    if (!screen)
 772       return NULL;
 773    pscreen = &screen->base.base;
 774    pscreen->destroy = nv50_screen_destroy;
 775
 776    ret = nouveau_screen_init(&screen->base, dev);
 777    if (ret) {
 778       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 779       goto fail;
 780    }
 781
 782    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 783     *  admit them to VRAM.
 784     */
 785    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 786       PIPE_BIND_VERTEX_BUFFER;
 787    screen->base.sysmem_bindings |=
 788       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 789
 790    screen->base.pushbuf->user_priv = screen;
 791    screen->base.pushbuf->rsvd_kick = 5;
 792
 793    chan = screen->base.channel;
 794
 795    pscreen->context_create = nv50_create;
 796    pscreen->is_format_supported = nv50_screen_is_format_supported;
 797    pscreen->get_param = nv50_screen_get_param;
 798    pscreen->get_shader_param = nv50_screen_get_shader_param;
 799    pscreen->get_paramf = nv50_screen_get_paramf;
 800    pscreen->get_compute_param = nv50_screen_get_compute_param;
 801    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 802    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 803
 804    nv50_screen_init_resource_functions(pscreen);
 805
 806    if (screen->base.device->chipset < 0x84 ||
 807        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 808       /* PMPEG */
 809       nouveau_screen_init_vdec(&screen->base);
 810    } else if (screen->base.device->chipset < 0x98 ||
 811               screen->base.device->chipset == 0xa0) {
 812       /* VP2 */
 813       screen->base.base.get_video_param = nv84_screen_get_video_param;
 814       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 815    } else {
 816       /* VP3/4 */
 817       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 818       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 819    }
 820
 821    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 822                         NULL, &screen->fence.bo);
 823    if (ret) {
 824       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 825       goto fail;
 826    }
 827
 828    nouveau_bo_map(screen->fence.bo, 0, NULL);
 829    screen->fence.map = screen->fence.bo->map;
 830    screen->base.fence.emit = nv50_screen_fence_emit;
 831    screen->base.fence.update = nv50_screen_fence_update;
 832
 833    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 834                             &(struct nv04_notify){ .length = 32 },
 835                             sizeof(struct nv04_notify), &screen->sync);
 836    if (ret) {
 837       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 838       goto fail;
 839    }
 840
 841    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 842                             NULL, 0, &screen->m2mf);
 843    if (ret) {
 844       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 845       goto fail;
 846    }
 847
 848    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 849                             NULL, 0, &screen->eng2d);
 850    if (ret) {
 851       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 852       goto fail;
 853    }
 854
 855    switch (dev->chipset & 0xf0) {
 856    case 0x50:
 857       tesla_class = NV50_3D_CLASS;
 858       break;
 859    case 0x80:
 860    case 0x90:
 861       tesla_class = NV84_3D_CLASS;
 862       break;
 863    case 0xa0:
 864       switch (dev->chipset) {
 865       case 0xa0:
 866       case 0xaa:
 867       case 0xac:
 868          tesla_class = NVA0_3D_CLASS;
 869          break;
 870       case 0xaf:
 871          tesla_class = NVAF_3D_CLASS;
 872          break;
 873       default:
 874          tesla_class = NVA3_3D_CLASS;
 875          break;
 876       }
 877       break;
 878    default:
 879       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 880       goto fail;
 881    }
 882    screen->base.class_3d = tesla_class;
 883
 884    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 885                             NULL, 0, &screen->tesla);
 886    if (ret) {
 887       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 888       goto fail;
 889    }
 890
 891    /* This over-allocates by a page. The GP, which would execute at the end of
 892     * the last page, would trigger faults. The going theory is that it
 893     * prefetches up to a certain amount.
 894     */
 895    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 896                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 897                         NULL, &screen->code);
 898    if (ret) {
 899       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 900       goto fail;
 901    }
 902
 903    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 904    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 905    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 906
 907    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 908
 909    screen->TPs = util_bitcount(value & 0xffff);
 910    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 911
 912    screen->mp_count = screen->TPs * screen->MPsInTP;
 913
 914    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 915          STACK_WARPS_ALLOC * 64 * 8;
 916
 917    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 918                         &screen->stack_bo);
 919    if (ret) {
 920       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 921       goto fail;
 922    }
 923
 924    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 925          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 926          ONE_TEMP_SIZE;
 927    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 928    screen->max_tls_space /= 2; /* half of vram */
 929
 930    /* hw can address max 64 KiB */
 931    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 932
 933    uint64_t tls_size;
 934    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 935    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 936    if (ret)
 937       goto fail;
 938
 939    if (nouveau_mesa_debug)
 940       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 941             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 942
 943    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 944                         &screen->uniforms);
 945    if (ret) {
 946       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 947       goto fail;
 948    }
 949
 950    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 951                         &screen->txc);
 952    if (ret) {
 953       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 954       goto fail;
 955    }
 956
 957    screen->tic.entries = CALLOC(4096, sizeof(void *));
 958    screen->tsc.entries = screen->tic.entries + 2048;
 959
 960    if (!nv50_blitter_create(screen))
 961       goto fail;
 962
 963    nv50_screen_init_hwctx(screen);
 964
 965    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
 966    if (ret) {
 967       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
 968       goto fail;
 969    }
 970
 971    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
 972
 973    return &screen->base;
 974
 975 fail:
 976    screen->base.base.context_create = NULL;
 977    return &screen->base;
 978 }
 979
 980 int
 981 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 982 {
 983    int i = screen->tic.next;
 984
 985    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 986       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 987
 988    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 989
 990    if (screen->tic.entries[i])
 991       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 992
 993    screen->tic.entries[i] = entry;
 994    return i;
 995 }
 996
 997 int
 998 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 999 {
1000    int i = screen->tsc.next;
1001
1002    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1003       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1004
1005    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1006
1007    if (screen->tsc.entries[i])
1008       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1009
1010    screen->tsc.entries[i] = entry;
1011    return i;
1012 }