2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
33 #include "nouveau_vp3_video.h"
35 #include "nv_object.xml.h"
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
42 #define THREADS_IN_WARP 32
45 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
46 enum pipe_format format
,
47 enum pipe_texture_target target
,
48 unsigned sample_count
,
53 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
55 if (sample_count
== 8 && util_format_get_blocksizebits(format
) >= 128)
58 if (!util_format_is_supported(format
, bindings
))
62 case PIPE_FORMAT_Z16_UNORM
:
63 if (nv50_screen(pscreen
)->tesla
->oclass
< NVA0_3D_CLASS
)
70 /* transfers & shared are always supported */
71 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
72 PIPE_BIND_TRANSFER_WRITE
|
75 return (( nv50_format_table
[format
].usage
|
76 nv50_vertex_format
[format
].usage
) & bindings
) == bindings
;
80 nv50_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
82 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
83 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
86 /* non-boolean caps */
87 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
89 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
91 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
93 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
95 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
96 case PIPE_CAP_MIN_TEXEL_OFFSET
:
98 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
99 case PIPE_CAP_MAX_TEXEL_OFFSET
:
101 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
102 return 128 * 1024 * 1024;
103 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
105 case PIPE_CAP_MAX_RENDER_TARGETS
:
107 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
109 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
111 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
112 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
114 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
115 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
117 case PIPE_CAP_MAX_VERTEX_STREAMS
:
119 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
121 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
123 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
124 return 16; /* 256 for binding as RT, but that's not possible in GL */
125 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
126 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
127 case PIPE_CAP_MAX_VIEWPORTS
:
128 return NV50_MAX_VIEWPORTS
;
129 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
130 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50
;
131 case PIPE_CAP_ENDIANNESS
:
132 return PIPE_ENDIAN_LITTLE
;
133 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
134 return (class_3d
>= NVA3_3D_CLASS
) ? 4 : 0;
137 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
138 case PIPE_CAP_TEXTURE_SWIZZLE
:
139 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
140 case PIPE_CAP_NPOT_TEXTURES
:
141 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
142 case PIPE_CAP_ANISOTROPIC_FILTER
:
143 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
144 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
145 case PIPE_CAP_TWO_SIDED_STENCIL
:
146 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
147 case PIPE_CAP_POINT_SPRITE
:
149 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
150 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
151 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
152 case PIPE_CAP_QUERY_TIMESTAMP
:
153 case PIPE_CAP_QUERY_TIME_ELAPSED
:
154 case PIPE_CAP_OCCLUSION_QUERY
:
155 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
156 case PIPE_CAP_INDEP_BLEND_ENABLE
:
157 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
158 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
159 case PIPE_CAP_PRIMITIVE_RESTART
:
160 case PIPE_CAP_TGSI_INSTANCEID
:
161 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
162 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
163 case PIPE_CAP_CONDITIONAL_RENDER
:
164 case PIPE_CAP_TEXTURE_BARRIER
:
165 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
166 case PIPE_CAP_START_INSTANCE
:
167 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
168 case PIPE_CAP_USER_INDEX_BUFFERS
:
169 case PIPE_CAP_USER_VERTEX_BUFFERS
:
170 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
171 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
172 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
173 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
174 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
175 case PIPE_CAP_CLIP_HALFZ
:
176 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
177 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
178 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
179 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
180 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
181 case PIPE_CAP_TGSI_TXQS
:
182 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
183 case PIPE_CAP_SHAREABLE_SHADERS
:
184 case PIPE_CAP_CLEAR_TEXTURE
:
185 case PIPE_CAP_COMPUTE
:
186 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
188 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
189 return 1; /* class_3d >= NVA0_3D_CLASS; */
190 /* supported on nva0+ */
191 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
192 return class_3d
>= NVA0_3D_CLASS
;
193 /* supported on nva3+ */
194 case PIPE_CAP_CUBE_MAP_ARRAY
:
195 case PIPE_CAP_INDEP_BLEND_FUNC
:
196 case PIPE_CAP_TEXTURE_QUERY_LOD
:
197 case PIPE_CAP_SAMPLE_SHADING
:
198 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
199 return class_3d
>= NVA3_3D_CLASS
;
201 /* unsupported caps */
202 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
203 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
204 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
205 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
206 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
207 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
208 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
209 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
210 case PIPE_CAP_TGSI_TEXCOORD
:
211 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
212 case PIPE_CAP_TEXTURE_GATHER_SM5
:
213 case PIPE_CAP_FAKE_SW_MSAA
:
214 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
215 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
216 case PIPE_CAP_DRAW_INDIRECT
:
217 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
218 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
219 case PIPE_CAP_VERTEXID_NOBASE
:
220 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
: /* potentially supported on some hw */
221 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
222 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
223 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
224 case PIPE_CAP_DRAW_PARAMETERS
:
225 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
226 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
227 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
228 case PIPE_CAP_INVALIDATE_BUFFER
:
229 case PIPE_CAP_GENERATE_MIPMAP
:
230 case PIPE_CAP_STRING_MARKER
:
231 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
232 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
233 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
234 case PIPE_CAP_QUERY_MEMORY_INFO
:
235 case PIPE_CAP_PCI_GROUP
:
236 case PIPE_CAP_PCI_BUS
:
237 case PIPE_CAP_PCI_DEVICE
:
238 case PIPE_CAP_PCI_FUNCTION
:
241 case PIPE_CAP_VENDOR_ID
:
243 case PIPE_CAP_DEVICE_ID
: {
245 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
246 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
251 case PIPE_CAP_ACCELERATED
:
253 case PIPE_CAP_VIDEO_MEMORY
:
254 return dev
->vram_size
>> 20;
259 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
264 nv50_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
265 enum pipe_shader_cap param
)
268 case PIPE_SHADER_VERTEX
:
269 case PIPE_SHADER_GEOMETRY
:
270 case PIPE_SHADER_FRAGMENT
:
272 case PIPE_SHADER_COMPUTE
:
278 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
279 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
280 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
281 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
283 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
285 case PIPE_SHADER_CAP_MAX_INPUTS
:
286 if (shader
== PIPE_SHADER_VERTEX
)
289 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
291 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
293 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
294 return NV50_MAX_PIPE_CONSTBUFS
;
295 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
296 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
297 return shader
!= PIPE_SHADER_FRAGMENT
;
298 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
299 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
301 case PIPE_SHADER_CAP_MAX_PREDS
:
303 case PIPE_SHADER_CAP_MAX_TEMPS
:
304 return nv50_screen(pscreen
)->max_tls_space
/ ONE_TEMP_SIZE
;
305 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
307 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
309 case PIPE_SHADER_CAP_SUBROUTINES
:
310 return 0; /* please inline, or provide function declarations */
311 case PIPE_SHADER_CAP_INTEGERS
:
313 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
314 /* The chip could handle more sampler views than samplers */
315 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
316 return MIN2(16, PIPE_MAX_SAMPLERS
);
317 case PIPE_SHADER_CAP_DOUBLES
:
318 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
319 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
320 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
321 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
322 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
323 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
324 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
326 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
329 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
335 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
338 case PIPE_CAPF_MAX_LINE_WIDTH
:
339 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
341 case PIPE_CAPF_MAX_POINT_WIDTH
:
342 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
344 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
346 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
348 case PIPE_CAPF_GUARD_BAND_LEFT
:
349 case PIPE_CAPF_GUARD_BAND_TOP
:
351 case PIPE_CAPF_GUARD_BAND_RIGHT
:
352 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
353 return 0.0f
; /* that or infinity */
356 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param
);
361 nv50_screen_get_compute_param(struct pipe_screen
*pscreen
,
362 enum pipe_compute_cap param
, void *data
)
364 struct nv50_screen
*screen
= nv50_screen(pscreen
);
366 #define RET(x) do { \
368 memcpy(data, x, sizeof(x)); \
373 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
374 RET((uint64_t []) { 2 });
375 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
376 RET(((uint64_t []) { 65535, 65535 }));
377 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
378 RET(((uint64_t []) { 512, 512, 64 }));
379 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
380 RET((uint64_t []) { 512 });
381 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
: /* g0-15[] */
382 RET((uint64_t []) { 1ULL << 32 });
383 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
: /* s[] */
384 RET((uint64_t []) { 16 << 10 });
385 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
: /* l[] */
386 RET((uint64_t []) { 16 << 10 });
387 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
: /* c[], arbitrary limit */
388 RET((uint64_t []) { 4096 });
389 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
390 RET((uint32_t []) { 32 });
391 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
392 RET((uint64_t []) { 1ULL << 40 });
393 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
394 RET((uint32_t []) { 0 });
395 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
396 RET((uint32_t []) { screen
->mp_count
});
397 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
398 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
407 nv50_screen_destroy(struct pipe_screen
*pscreen
)
409 struct nv50_screen
*screen
= nv50_screen(pscreen
);
411 if (!nouveau_drm_screen_unref(&screen
->base
))
414 if (screen
->base
.fence
.current
) {
415 struct nouveau_fence
*current
= NULL
;
417 /* nouveau_fence_wait will create a new current fence, so wait on the
418 * _current_ one, and remove both.
420 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
421 nouveau_fence_wait(current
, NULL
);
422 nouveau_fence_ref(NULL
, ¤t
);
423 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
425 if (screen
->base
.pushbuf
)
426 screen
->base
.pushbuf
->user_priv
= NULL
;
429 nv50_blitter_destroy(screen
);
430 if (screen
->pm
.prog
) {
431 screen
->pm
.prog
->code
= NULL
; /* hardcoded, don't FREE */
432 nv50_program_destroy(NULL
, screen
->pm
.prog
);
433 FREE(screen
->pm
.prog
);
436 nouveau_bo_ref(NULL
, &screen
->code
);
437 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
438 nouveau_bo_ref(NULL
, &screen
->stack_bo
);
439 nouveau_bo_ref(NULL
, &screen
->txc
);
440 nouveau_bo_ref(NULL
, &screen
->uniforms
);
441 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
443 nouveau_heap_destroy(&screen
->vp_code_heap
);
444 nouveau_heap_destroy(&screen
->gp_code_heap
);
445 nouveau_heap_destroy(&screen
->fp_code_heap
);
447 FREE(screen
->tic
.entries
);
449 nouveau_object_del(&screen
->tesla
);
450 nouveau_object_del(&screen
->eng2d
);
451 nouveau_object_del(&screen
->m2mf
);
452 nouveau_object_del(&screen
->compute
);
453 nouveau_object_del(&screen
->sync
);
455 nouveau_screen_fini(&screen
->base
);
461 nv50_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
463 struct nv50_screen
*screen
= nv50_screen(pscreen
);
464 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
466 /* we need to do it after possible flush in MARK_RING */
467 *sequence
= ++screen
->base
.fence
.sequence
;
469 assert(PUSH_AVAIL(push
) + push
->rsvd_kick
>= 5);
470 PUSH_DATA (push
, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH
), 4));
471 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
472 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
473 PUSH_DATA (push
, *sequence
);
474 PUSH_DATA (push
, NV50_3D_QUERY_GET_MODE_WRITE_UNK0
|
475 NV50_3D_QUERY_GET_UNK4
|
476 NV50_3D_QUERY_GET_UNIT_CROP
|
477 NV50_3D_QUERY_GET_TYPE_QUERY
|
478 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO
|
479 NV50_3D_QUERY_GET_SHORT
);
483 nv50_screen_fence_update(struct pipe_screen
*pscreen
)
485 return nv50_screen(pscreen
)->fence
.map
[0];
489 nv50_screen_init_hwctx(struct nv50_screen
*screen
)
491 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
492 struct nv04_fifo
*fifo
;
495 fifo
= (struct nv04_fifo
*)screen
->base
.channel
->data
;
497 BEGIN_NV04(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
498 PUSH_DATA (push
, screen
->m2mf
->handle
);
499 BEGIN_NV04(push
, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY
), 3);
500 PUSH_DATA (push
, screen
->sync
->handle
);
501 PUSH_DATA (push
, fifo
->vram
);
502 PUSH_DATA (push
, fifo
->vram
);
504 BEGIN_NV04(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
505 PUSH_DATA (push
, screen
->eng2d
->handle
);
506 BEGIN_NV04(push
, NV50_2D(DMA_NOTIFY
), 4);
507 PUSH_DATA (push
, screen
->sync
->handle
);
508 PUSH_DATA (push
, fifo
->vram
);
509 PUSH_DATA (push
, fifo
->vram
);
510 PUSH_DATA (push
, fifo
->vram
);
511 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
512 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
513 BEGIN_NV04(push
, NV50_2D(CLIP_ENABLE
), 1);
515 BEGIN_NV04(push
, NV50_2D(COLOR_KEY_ENABLE
), 1);
517 BEGIN_NV04(push
, SUBC_2D(0x0888), 1);
519 BEGIN_NV04(push
, NV50_2D(COND_MODE
), 1);
520 PUSH_DATA (push
, NV50_2D_COND_MODE_ALWAYS
);
522 BEGIN_NV04(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
523 PUSH_DATA (push
, screen
->tesla
->handle
);
525 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
526 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
528 BEGIN_NV04(push
, NV50_3D(DMA_NOTIFY
), 1);
529 PUSH_DATA (push
, screen
->sync
->handle
);
530 BEGIN_NV04(push
, NV50_3D(DMA_ZETA
), 11);
531 for (i
= 0; i
< 11; ++i
)
532 PUSH_DATA(push
, fifo
->vram
);
533 BEGIN_NV04(push
, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN
);
534 for (i
= 0; i
< NV50_3D_DMA_COLOR__LEN
; ++i
)
535 PUSH_DATA(push
, fifo
->vram
);
537 BEGIN_NV04(push
, NV50_3D(REG_MODE
), 1);
538 PUSH_DATA (push
, NV50_3D_REG_MODE_STRIPED
);
539 BEGIN_NV04(push
, NV50_3D(UNK1400_LANES
), 1);
540 PUSH_DATA (push
, 0xf);
542 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
543 BEGIN_NV04(push
, NV50_3D(WATCHDOG_TIMER
), 1);
544 PUSH_DATA (push
, 0x18);
547 BEGIN_NV04(push
, NV50_3D(ZETA_COMP_ENABLE
), 1);
548 PUSH_DATA(push
, screen
->base
.drm
->version
>= 0x01000101);
550 BEGIN_NV04(push
, NV50_3D(RT_COMP_ENABLE(0)), 8);
551 for (i
= 0; i
< 8; ++i
)
552 PUSH_DATA(push
, screen
->base
.drm
->version
>= 0x01000101);
554 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
557 BEGIN_NV04(push
, NV50_3D(CSAA_ENABLE
), 1);
559 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_ENABLE
), 1);
561 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
562 PUSH_DATA (push
, NV50_3D_MULTISAMPLE_MODE_MS1
);
563 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_CTRL
), 1);
565 BEGIN_NV04(push
, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS
), 1);
567 BEGIN_NV04(push
, NV50_3D(BLEND_SEPARATE_ALPHA
), 1);
570 if (screen
->tesla
->oclass
>= NVA0_3D_CLASS
) {
571 BEGIN_NV04(push
, SUBC_3D(NVA0_3D_TEX_MISC
), 1);
575 BEGIN_NV04(push
, NV50_3D(SCREEN_Y_CONTROL
), 1);
577 BEGIN_NV04(push
, NV50_3D(WINDOW_OFFSET_X
), 2);
580 BEGIN_NV04(push
, NV50_3D(ZCULL_REGION
), 1);
581 PUSH_DATA (push
, 0x3f);
583 BEGIN_NV04(push
, NV50_3D(VP_ADDRESS_HIGH
), 2);
584 PUSH_DATAh(push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
585 PUSH_DATA (push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
587 BEGIN_NV04(push
, NV50_3D(FP_ADDRESS_HIGH
), 2);
588 PUSH_DATAh(push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
589 PUSH_DATA (push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
591 BEGIN_NV04(push
, NV50_3D(GP_ADDRESS_HIGH
), 2);
592 PUSH_DATAh(push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
593 PUSH_DATA (push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
595 BEGIN_NV04(push
, NV50_3D(LOCAL_ADDRESS_HIGH
), 3);
596 PUSH_DATAh(push
, screen
->tls_bo
->offset
);
597 PUSH_DATA (push
, screen
->tls_bo
->offset
);
598 PUSH_DATA (push
, util_logbase2(screen
->cur_tls_space
/ 8));
600 BEGIN_NV04(push
, NV50_3D(STACK_ADDRESS_HIGH
), 3);
601 PUSH_DATAh(push
, screen
->stack_bo
->offset
);
602 PUSH_DATA (push
, screen
->stack_bo
->offset
);
605 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
606 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (0 << 16));
607 PUSH_DATA (push
, screen
->uniforms
->offset
+ (0 << 16));
608 PUSH_DATA (push
, (NV50_CB_PVP
<< 16) | 0x0000);
610 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
611 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (1 << 16));
612 PUSH_DATA (push
, screen
->uniforms
->offset
+ (1 << 16));
613 PUSH_DATA (push
, (NV50_CB_PGP
<< 16) | 0x0000);
615 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
616 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (2 << 16));
617 PUSH_DATA (push
, screen
->uniforms
->offset
+ (2 << 16));
618 PUSH_DATA (push
, (NV50_CB_PFP
<< 16) | 0x0000);
620 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
621 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (3 << 16));
622 PUSH_DATA (push
, screen
->uniforms
->offset
+ (3 << 16));
623 PUSH_DATA (push
, (NV50_CB_AUX
<< 16) | (NV50_CB_AUX_SIZE
& 0xffff));
625 BEGIN_NI04(push
, NV50_3D(SET_PROGRAM_CB
), 3);
626 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf01);
627 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf21);
628 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf31);
630 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
631 BEGIN_NV04(push
, NV50_3D(CB_ADDR
), 1);
632 PUSH_DATA (push
, (NV50_CB_AUX_RUNOUT_OFFSET
<< (8 - 2)) | NV50_CB_AUX
);
633 BEGIN_NI04(push
, NV50_3D(CB_DATA(0)), 4);
634 PUSH_DATAf(push
, 0.0f
);
635 PUSH_DATAf(push
, 0.0f
);
636 PUSH_DATAf(push
, 0.0f
);
637 PUSH_DATAf(push
, 0.0f
);
638 BEGIN_NV04(push
, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
639 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET
);
640 PUSH_DATA (push
, screen
->uniforms
->offset
+ (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET
);
642 nv50_upload_ms_info(push
);
644 /* max TIC (bits 4:8) & TSC bindings, per program type */
645 for (i
= 0; i
< 3; ++i
) {
646 BEGIN_NV04(push
, NV50_3D(TEX_LIMITS(i
)), 1);
647 PUSH_DATA (push
, 0x54);
650 BEGIN_NV04(push
, NV50_3D(TIC_ADDRESS_HIGH
), 3);
651 PUSH_DATAh(push
, screen
->txc
->offset
);
652 PUSH_DATA (push
, screen
->txc
->offset
);
653 PUSH_DATA (push
, NV50_TIC_MAX_ENTRIES
- 1);
655 BEGIN_NV04(push
, NV50_3D(TSC_ADDRESS_HIGH
), 3);
656 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
657 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
658 PUSH_DATA (push
, NV50_TSC_MAX_ENTRIES
- 1);
660 BEGIN_NV04(push
, NV50_3D(LINKED_TSC
), 1);
663 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_EN
), 1);
665 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_MODE
), 1);
666 PUSH_DATA (push
, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
667 BEGIN_NV04(push
, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
668 for (i
= 0; i
< 8 * 2; ++i
)
670 BEGIN_NV04(push
, NV50_3D(CLIPID_ENABLE
), 1);
673 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
675 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
676 BEGIN_NV04(push
, NV50_3D(DEPTH_RANGE_NEAR(i
)), 2);
677 PUSH_DATAf(push
, 0.0f
);
678 PUSH_DATAf(push
, 1.0f
);
679 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(i
)), 2);
680 PUSH_DATA (push
, 8192 << 16);
681 PUSH_DATA (push
, 8192 << 16);
684 BEGIN_NV04(push
, NV50_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
685 #ifdef NV50_SCISSORS_CLIPPING
686 PUSH_DATA (push
, 0x0000);
688 PUSH_DATA (push
, 0x1080);
691 BEGIN_NV04(push
, NV50_3D(CLEAR_FLAGS
), 1);
692 PUSH_DATA (push
, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT
);
694 /* We use scissors instead of exact view volume clipping,
695 * so they're always enabled.
697 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
698 BEGIN_NV04(push
, NV50_3D(SCISSOR_ENABLE(i
)), 3);
700 PUSH_DATA (push
, 8192 << 16);
701 PUSH_DATA (push
, 8192 << 16);
704 BEGIN_NV04(push
, NV50_3D(RASTERIZE_ENABLE
), 1);
706 BEGIN_NV04(push
, NV50_3D(POINT_RASTER_RULES
), 1);
707 PUSH_DATA (push
, NV50_3D_POINT_RASTER_RULES_OGL
);
708 BEGIN_NV04(push
, NV50_3D(FRAG_COLOR_CLAMP_EN
), 1);
709 PUSH_DATA (push
, 0x11111111);
710 BEGIN_NV04(push
, NV50_3D(EDGEFLAG
), 1);
713 BEGIN_NV04(push
, NV50_3D(VB_ELEMENT_BASE
), 1);
715 if (screen
->base
.class_3d
>= NV84_3D_CLASS
) {
716 BEGIN_NV04(push
, NV84_3D(VERTEX_ID_BASE
), 1);
723 static int nv50_tls_alloc(struct nv50_screen
*screen
, unsigned tls_space
,
726 struct nouveau_device
*dev
= screen
->base
.device
;
729 screen
->cur_tls_space
= util_next_power_of_two(tls_space
/ ONE_TEMP_SIZE
) *
731 if (nouveau_mesa_debug
)
732 debug_printf("allocating space for %u temps\n",
733 util_next_power_of_two(tls_space
/ ONE_TEMP_SIZE
));
734 *tls_size
= screen
->cur_tls_space
* util_next_power_of_two(screen
->TPs
) *
735 screen
->MPsInTP
* LOCAL_WARPS_ALLOC
* THREADS_IN_WARP
;
737 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
738 *tls_size
, NULL
, &screen
->tls_bo
);
740 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret
);
747 int nv50_tls_realloc(struct nv50_screen
*screen
, unsigned tls_space
)
749 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
753 if (tls_space
< screen
->cur_tls_space
)
755 if (tls_space
> screen
->max_tls_space
) {
756 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
757 * LOCAL_WARPS_NO_CLAMP) */
758 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
759 (unsigned)(tls_space
/ ONE_TEMP_SIZE
),
760 (unsigned)(screen
->max_tls_space
/ ONE_TEMP_SIZE
));
764 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
765 ret
= nv50_tls_alloc(screen
, tls_space
, &tls_size
);
769 BEGIN_NV04(push
, NV50_3D(LOCAL_ADDRESS_HIGH
), 3);
770 PUSH_DATAh(push
, screen
->tls_bo
->offset
);
771 PUSH_DATA (push
, screen
->tls_bo
->offset
);
772 PUSH_DATA (push
, util_logbase2(screen
->cur_tls_space
/ 8));
777 struct nouveau_screen
*
778 nv50_screen_create(struct nouveau_device
*dev
)
780 struct nv50_screen
*screen
;
781 struct pipe_screen
*pscreen
;
782 struct nouveau_object
*chan
;
784 uint32_t tesla_class
;
788 screen
= CALLOC_STRUCT(nv50_screen
);
791 pscreen
= &screen
->base
.base
;
792 pscreen
->destroy
= nv50_screen_destroy
;
794 ret
= nouveau_screen_init(&screen
->base
, dev
);
796 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret
);
800 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
801 * admit them to VRAM.
803 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
804 PIPE_BIND_VERTEX_BUFFER
;
805 screen
->base
.sysmem_bindings
|=
806 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
808 screen
->base
.pushbuf
->user_priv
= screen
;
809 screen
->base
.pushbuf
->rsvd_kick
= 5;
811 chan
= screen
->base
.channel
;
813 pscreen
->context_create
= nv50_create
;
814 pscreen
->is_format_supported
= nv50_screen_is_format_supported
;
815 pscreen
->get_param
= nv50_screen_get_param
;
816 pscreen
->get_shader_param
= nv50_screen_get_shader_param
;
817 pscreen
->get_paramf
= nv50_screen_get_paramf
;
818 pscreen
->get_compute_param
= nv50_screen_get_compute_param
;
819 pscreen
->get_driver_query_info
= nv50_screen_get_driver_query_info
;
820 pscreen
->get_driver_query_group_info
= nv50_screen_get_driver_query_group_info
;
822 nv50_screen_init_resource_functions(pscreen
);
824 if (screen
->base
.device
->chipset
< 0x84 ||
825 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
827 nouveau_screen_init_vdec(&screen
->base
);
828 } else if (screen
->base
.device
->chipset
< 0x98 ||
829 screen
->base
.device
->chipset
== 0xa0) {
831 screen
->base
.base
.get_video_param
= nv84_screen_get_video_param
;
832 screen
->base
.base
.is_video_format_supported
= nv84_screen_video_supported
;
835 screen
->base
.base
.get_video_param
= nouveau_vp3_screen_get_video_param
;
836 screen
->base
.base
.is_video_format_supported
= nouveau_vp3_screen_video_supported
;
839 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096,
840 NULL
, &screen
->fence
.bo
);
842 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret
);
846 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
847 screen
->fence
.map
= screen
->fence
.bo
->map
;
848 screen
->base
.fence
.emit
= nv50_screen_fence_emit
;
849 screen
->base
.fence
.update
= nv50_screen_fence_update
;
851 ret
= nouveau_object_new(chan
, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS
,
852 &(struct nv04_notify
){ .length
= 32 },
853 sizeof(struct nv04_notify
), &screen
->sync
);
855 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret
);
859 ret
= nouveau_object_new(chan
, 0xbeef5039, NV50_M2MF_CLASS
,
860 NULL
, 0, &screen
->m2mf
);
862 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret
);
866 ret
= nouveau_object_new(chan
, 0xbeef502d, NV50_2D_CLASS
,
867 NULL
, 0, &screen
->eng2d
);
869 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret
);
873 switch (dev
->chipset
& 0xf0) {
875 tesla_class
= NV50_3D_CLASS
;
879 tesla_class
= NV84_3D_CLASS
;
882 switch (dev
->chipset
) {
886 tesla_class
= NVA0_3D_CLASS
;
889 tesla_class
= NVAF_3D_CLASS
;
892 tesla_class
= NVA3_3D_CLASS
;
897 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev
->chipset
);
900 screen
->base
.class_3d
= tesla_class
;
902 ret
= nouveau_object_new(chan
, 0xbeef5097, tesla_class
,
903 NULL
, 0, &screen
->tesla
);
905 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret
);
909 /* This over-allocates by a page. The GP, which would execute at the end of
910 * the last page, would trigger faults. The going theory is that it
911 * prefetches up to a certain amount.
913 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
914 (3 << NV50_CODE_BO_SIZE_LOG2
) + 0x1000,
915 NULL
, &screen
->code
);
917 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret
);
921 nouveau_heap_init(&screen
->vp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
922 nouveau_heap_init(&screen
->gp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
923 nouveau_heap_init(&screen
->fp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
925 nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
927 screen
->TPs
= util_bitcount(value
& 0xffff);
928 screen
->MPsInTP
= util_bitcount((value
>> 24) & 0xf);
930 screen
->mp_count
= screen
->TPs
* screen
->MPsInTP
;
932 stack_size
= util_next_power_of_two(screen
->TPs
) * screen
->MPsInTP
*
933 STACK_WARPS_ALLOC
* 64 * 8;
935 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, stack_size
, NULL
,
938 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret
);
942 uint64_t size_of_one_temp
= util_next_power_of_two(screen
->TPs
) *
943 screen
->MPsInTP
* LOCAL_WARPS_ALLOC
* THREADS_IN_WARP
*
945 screen
->max_tls_space
= dev
->vram_size
/ size_of_one_temp
* ONE_TEMP_SIZE
;
946 screen
->max_tls_space
/= 2; /* half of vram */
948 /* hw can address max 64 KiB */
949 screen
->max_tls_space
= MIN2(screen
->max_tls_space
, 64 << 10);
952 unsigned tls_space
= 4/*temps*/ * ONE_TEMP_SIZE
;
953 ret
= nv50_tls_alloc(screen
, tls_space
, &tls_size
);
957 if (nouveau_mesa_debug
)
958 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64
" MiB, tls_size = %"PRIu64
" KiB\n",
959 screen
->TPs
, screen
->MPsInTP
, dev
->vram_size
>> 20, tls_size
>> 10);
961 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 4 << 16, NULL
,
964 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret
);
968 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 3 << 16, NULL
,
971 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret
);
975 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
976 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
978 if (!nv50_blitter_create(screen
))
981 nv50_screen_init_hwctx(screen
);
983 ret
= nv50_screen_compute_setup(screen
, screen
->base
.pushbuf
);
985 NOUVEAU_ERR("Failed to init compute context: %d\n", ret
);
989 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, false);
991 return &screen
->base
;
994 screen
->base
.base
.context_create
= NULL
;
995 return &screen
->base
;
999 nv50_screen_tic_alloc(struct nv50_screen
*screen
, void *entry
)
1001 int i
= screen
->tic
.next
;
1003 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
1004 i
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
1006 screen
->tic
.next
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
1008 if (screen
->tic
.entries
[i
])
1009 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
1011 screen
->tic
.entries
[i
] = entry
;
1016 nv50_screen_tsc_alloc(struct nv50_screen
*screen
, void *entry
)
1018 int i
= screen
->tsc
.next
;
1020 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
1021 i
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
1023 screen
->tsc
.next
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
1025 if (screen
->tsc
.entries
[i
])
1026 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
1028 screen
->tsc
.entries
[i
] = entry
;