src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30 #include "compiler/nir/nir.h"
  31
  32 #include "nv50/nv50_context.h"
  33 #include "nv50/nv50_screen.h"
  34
  35 #include "nouveau_vp3_video.h"
  36
  37 #include "nv_object.xml.h"
  38
  39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  40 #define LOCAL_WARPS_ALLOC 32
  41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  42 #define STACK_WARPS_ALLOC 32
  43
  44 #define THREADS_IN_WARP 32
  45
  46 static boolean
  47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  48                                 enum pipe_format format,
  49                                 enum pipe_texture_target target,
  50                                 unsigned sample_count,
  51                                 unsigned storage_sample_count,
  52                                 unsigned bindings)
  53 {
  54    if (sample_count > 8)
  55       return false;
  56    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  57       return false;
  58    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  59       return false;
  60
  61    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  62       return false;
  63
  64    switch (format) {
  65    case PIPE_FORMAT_Z16_UNORM:
  66       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  67          return false;
  68       break;
  69    default:
  70       break;
  71    }
  72
  73    if (bindings & PIPE_BIND_LINEAR)
  74       if (util_format_is_depth_or_stencil(format) ||
  75           (target != PIPE_TEXTURE_1D &&
  76            target != PIPE_TEXTURE_2D &&
  77            target != PIPE_TEXTURE_RECT) ||
  78           sample_count > 1)
  79          return false;
  80
  81    /* shared is always supported */
  82    bindings &= ~(PIPE_BIND_LINEAR |
  83                  PIPE_BIND_SHARED);
  84
  85    return (( nv50_format_table[format].usage |
  86             nv50_vertex_format[format].usage) & bindings) == bindings;
  87 }
  88
  89 static int
  90 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  91 {
  92    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  93    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  94
  95    switch (param) {
  96    /* non-boolean caps */
  97    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  98       return 14;
  99    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 100       return 12;
 101    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 102       return 14;
 103    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 104       return 512;
 105    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MIN_TEXEL_OFFSET:
 107       return -8;
 108    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 109    case PIPE_CAP_MAX_TEXEL_OFFSET:
 110       return 7;
 111    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 112       return 128 * 1024 * 1024;
 113    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 114       return 330;
 115    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 116       return 330;
 117    case PIPE_CAP_MAX_RENDER_TARGETS:
 118       return 8;
 119    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 120       return 1;
 121    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 122    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 123       return 8;
 124    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 125       return 4;
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 128       return 64;
 129    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 130    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 131       return 1024;
 132    case PIPE_CAP_MAX_VERTEX_STREAMS:
 133       return 1;
 134    case PIPE_CAP_MAX_GS_INVOCATIONS:
 135       return 0;
 136    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 137       return 0;
 138    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 139       return 2048;
 140    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 141       return 2047;
 142    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 143       return 256;
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145       return 16; /* 256 for binding as RT, but that's not possible in GL */
 146    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 147       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 148    case PIPE_CAP_MAX_VIEWPORTS:
 149       return NV50_MAX_VIEWPORTS;
 150    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 151       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 152    case PIPE_CAP_ENDIANNESS:
 153       return PIPE_ENDIAN_LITTLE;
 154    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 155       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 156    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 157       return NV50_MAX_WINDOW_RECTANGLES;
 158    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 159       return 16 * 1024 * 1024;
 160    case PIPE_CAP_MAX_VARYINGS:
 161       return 15;
 162
 163    /* supported caps */
 164    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 165    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 166    case PIPE_CAP_TEXTURE_SWIZZLE:
 167    case PIPE_CAP_NPOT_TEXTURES:
 168    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 169    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 170    case PIPE_CAP_ANISOTROPIC_FILTER:
 171    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 172    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 173    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 174    case PIPE_CAP_POINT_SPRITE:
 175    case PIPE_CAP_SM3:
 176    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 177    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 178    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 179    case PIPE_CAP_QUERY_TIMESTAMP:
 180    case PIPE_CAP_QUERY_TIME_ELAPSED:
 181    case PIPE_CAP_OCCLUSION_QUERY:
 182    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 183    case PIPE_CAP_INDEP_BLEND_ENABLE:
 184    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 185    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 186    case PIPE_CAP_PRIMITIVE_RESTART:
 187    case PIPE_CAP_TGSI_INSTANCEID:
 188    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 189    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 190    case PIPE_CAP_CONDITIONAL_RENDER:
 191    case PIPE_CAP_TEXTURE_BARRIER:
 192    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 193    case PIPE_CAP_START_INSTANCE:
 194    case PIPE_CAP_USER_VERTEX_BUFFERS:
 195    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 196    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 197    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 198    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 199    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 200    case PIPE_CAP_CLIP_HALFZ:
 201    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 202    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 203    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 204    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 205    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 206    case PIPE_CAP_TGSI_TXQS:
 207    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 208    case PIPE_CAP_SHAREABLE_SHADERS:
 209    case PIPE_CAP_CLEAR_TEXTURE:
 210    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 211    case PIPE_CAP_INVALIDATE_BUFFER:
 212    case PIPE_CAP_STRING_MARKER:
 213    case PIPE_CAP_CULL_DISTANCE:
 214    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 215    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 216    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 217    case PIPE_CAP_TGSI_CLOCK:
 218    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 219    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 220    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 221       return 1;
 222    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 223       return 1; /* class_3d >= NVA0_3D_CLASS; */
 224    /* supported on nva0+ */
 225    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 226       return class_3d >= NVA0_3D_CLASS;
 227    /* supported on nva3+ */
 228    case PIPE_CAP_CUBE_MAP_ARRAY:
 229    case PIPE_CAP_INDEP_BLEND_FUNC:
 230    case PIPE_CAP_TEXTURE_QUERY_LOD:
 231    case PIPE_CAP_SAMPLE_SHADING:
 232    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 233       return class_3d >= NVA3_3D_CLASS;
 234
 235    /* unsupported caps */
 236    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 237    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 238    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 239    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 240    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 241    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 242    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 243    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 244    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 245    case PIPE_CAP_TGSI_TEXCOORD:
 246    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 247    case PIPE_CAP_TEXTURE_GATHER_SM5:
 248    case PIPE_CAP_FAKE_SW_MSAA:
 249    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 250    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 251    case PIPE_CAP_DRAW_INDIRECT:
 252    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 253    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 254    case PIPE_CAP_VERTEXID_NOBASE:
 255    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 256    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 257    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 258    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 259    case PIPE_CAP_DRAW_PARAMETERS:
 260    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 261    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 262    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 263    case PIPE_CAP_GENERATE_MIPMAP:
 264    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 265    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 266    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 267    case PIPE_CAP_QUERY_MEMORY_INFO:
 268    case PIPE_CAP_PCI_GROUP:
 269    case PIPE_CAP_PCI_BUS:
 270    case PIPE_CAP_PCI_DEVICE:
 271    case PIPE_CAP_PCI_FUNCTION:
 272    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 273    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 274    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 275    case PIPE_CAP_TGSI_VOTE:
 276    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 277    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 278    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 279    case PIPE_CAP_NATIVE_FENCE_FD:
 280    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 281    case PIPE_CAP_TGSI_FS_FBFETCH:
 282    case PIPE_CAP_DOUBLES:
 283    case PIPE_CAP_INT64:
 284    case PIPE_CAP_INT64_DIVMOD:
 285    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 286    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 287    case PIPE_CAP_TGSI_BALLOT:
 288    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 289    case PIPE_CAP_POST_DEPTH_COVERAGE:
 290    case PIPE_CAP_BINDLESS_TEXTURE:
 291    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 292    case PIPE_CAP_QUERY_SO_OVERFLOW:
 293    case PIPE_CAP_MEMOBJ:
 294    case PIPE_CAP_LOAD_CONSTBUF:
 295    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 296    case PIPE_CAP_TILE_RASTER_ORDER:
 297    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 298    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 299    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 300    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 301    case PIPE_CAP_FENCE_SIGNAL:
 302    case PIPE_CAP_CONSTBUF0_FLAGS:
 303    case PIPE_CAP_PACKED_UNIFORMS:
 304    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 305    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 306    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 307    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 308    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 309    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 310    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 311    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 312    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 313    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 314    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 315    case PIPE_CAP_TGSI_ATOMFADD:
 316    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 317    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 318    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 319    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 320    case PIPE_CAP_COMPUTE:
 321    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 322       return 0;
 323
 324    case PIPE_CAP_MAX_FRAMES_IN_FLIGHT:
 325       return 2;
 326
 327    case PIPE_CAP_VENDOR_ID:
 328       return 0x10de;
 329    case PIPE_CAP_DEVICE_ID: {
 330       uint64_t device_id;
 331       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 332          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 333          return -1;
 334       }
 335       return device_id;
 336    }
 337    case PIPE_CAP_ACCELERATED:
 338       return 1;
 339    case PIPE_CAP_VIDEO_MEMORY:
 340       return dev->vram_size >> 20;
 341    case PIPE_CAP_UMA:
 342       return 0;
 343    default:
 344       debug_printf("%s: unhandled cap %d\n", __func__, param);
 345       return u_pipe_screen_get_param_defaults(pscreen, param);
 346    }
 347 }
 348
 349 static int
 350 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 351                              enum pipe_shader_type shader,
 352                              enum pipe_shader_cap param)
 353 {
 354    const struct nouveau_screen *screen = nouveau_screen(pscreen);
 355
 356    switch (shader) {
 357    case PIPE_SHADER_VERTEX:
 358    case PIPE_SHADER_GEOMETRY:
 359    case PIPE_SHADER_FRAGMENT:
 360       break;
 361    case PIPE_SHADER_COMPUTE:
 362    default:
 363       return 0;
 364    }
 365
 366    switch (param) {
 367    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 368    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 369    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 370    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 371       return 16384;
 372    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 373       return 4;
 374    case PIPE_SHADER_CAP_MAX_INPUTS:
 375       if (shader == PIPE_SHADER_VERTEX)
 376          return 32;
 377       return 15;
 378    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 379       return 16;
 380    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 381       return 65536;
 382    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 383       return NV50_MAX_PIPE_CONSTBUFS;
 384    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 385       return shader != PIPE_SHADER_FRAGMENT;
 386    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 387    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 388    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 389       return 1;
 390    case PIPE_SHADER_CAP_MAX_TEMPS:
 391       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 392    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 393       return 1;
 394    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 395       return 1;
 396    case PIPE_SHADER_CAP_INT64_ATOMICS:
 397    case PIPE_SHADER_CAP_FP16:
 398    case PIPE_SHADER_CAP_SUBROUTINES:
 399       return 0; /* please inline, or provide function declarations */
 400    case PIPE_SHADER_CAP_INTEGERS:
 401       return 1;
 402    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 403       return 1;
 404    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 405       /* The chip could handle more sampler views than samplers */
 406    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 407       return MIN2(16, PIPE_MAX_SAMPLERS);
 408    case PIPE_SHADER_CAP_PREFERRED_IR:
 409       return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
 410    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 411       return 32;
 412    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 413    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 414    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 415    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 416    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 417    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 418    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 419    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 420    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 421    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 422    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 423       return 0;
 424    case PIPE_SHADER_CAP_SCALAR_ISA:
 425       return 1;
 426    default:
 427       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 428       return 0;
 429    }
 430 }
 431
 432 static float
 433 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 434 {
 435    switch (param) {
 436    case PIPE_CAPF_MAX_LINE_WIDTH:
 437    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 438       return 10.0f;
 439    case PIPE_CAPF_MAX_POINT_WIDTH:
 440    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 441       return 64.0f;
 442    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 443       return 16.0f;
 444    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 445       return 4.0f;
 446    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 447    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 448    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 449       return 0.0f;
 450    }
 451
 452    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 453    return 0.0f;
 454 }
 455
 456 static int
 457 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 458                               enum pipe_shader_ir ir_type,
 459                               enum pipe_compute_cap param, void *data)
 460 {
 461    struct nv50_screen *screen = nv50_screen(pscreen);
 462
 463 #define RET(x) do {                  \
 464    if (data)                         \
 465       memcpy(data, x, sizeof(x));    \
 466    return sizeof(x);                 \
 467 } while (0)
 468
 469    switch (param) {
 470    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 471       RET((uint64_t []) { 2 });
 472    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 473       RET(((uint64_t []) { 65535, 65535 }));
 474    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 475       RET(((uint64_t []) { 512, 512, 64 }));
 476    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 477       RET((uint64_t []) { 512 });
 478    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 479       RET((uint64_t []) { 1ULL << 32 });
 480    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 481       RET((uint64_t []) { 16 << 10 });
 482    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 483       RET((uint64_t []) { 16 << 10 });
 484    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 485       RET((uint64_t []) { 4096 });
 486    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 487       RET((uint32_t []) { 32 });
 488    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 489       RET((uint64_t []) { 1ULL << 40 });
 490    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 491       RET((uint32_t []) { 0 });
 492    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 493       RET((uint32_t []) { screen->mp_count });
 494    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 495       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 496    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 497       RET((uint32_t []) { 32 });
 498    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 499       RET((uint64_t []) { 0 });
 500    default:
 501       return 0;
 502    }
 503
 504 #undef RET
 505 }
 506
 507 static void
 508 nv50_screen_destroy(struct pipe_screen *pscreen)
 509 {
 510    struct nv50_screen *screen = nv50_screen(pscreen);
 511
 512    if (!nouveau_drm_screen_unref(&screen->base))
 513       return;
 514
 515    if (screen->base.fence.current) {
 516       struct nouveau_fence *current = NULL;
 517
 518       /* nouveau_fence_wait will create a new current fence, so wait on the
 519        * _current_ one, and remove both.
 520        */
 521       nouveau_fence_ref(screen->base.fence.current, &current);
 522       nouveau_fence_wait(current, NULL);
 523       nouveau_fence_ref(NULL, &current);
 524       nouveau_fence_ref(NULL, &screen->base.fence.current);
 525    }
 526    if (screen->base.pushbuf)
 527       screen->base.pushbuf->user_priv = NULL;
 528
 529    if (screen->blitter)
 530       nv50_blitter_destroy(screen);
 531    if (screen->pm.prog) {
 532       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 533       nv50_program_destroy(NULL, screen->pm.prog);
 534       FREE(screen->pm.prog);
 535    }
 536
 537    nouveau_bo_ref(NULL, &screen->code);
 538    nouveau_bo_ref(NULL, &screen->tls_bo);
 539    nouveau_bo_ref(NULL, &screen->stack_bo);
 540    nouveau_bo_ref(NULL, &screen->txc);
 541    nouveau_bo_ref(NULL, &screen->uniforms);
 542    nouveau_bo_ref(NULL, &screen->fence.bo);
 543
 544    nouveau_heap_destroy(&screen->vp_code_heap);
 545    nouveau_heap_destroy(&screen->gp_code_heap);
 546    nouveau_heap_destroy(&screen->fp_code_heap);
 547
 548    FREE(screen->tic.entries);
 549
 550    nouveau_object_del(&screen->tesla);
 551    nouveau_object_del(&screen->eng2d);
 552    nouveau_object_del(&screen->m2mf);
 553    nouveau_object_del(&screen->compute);
 554    nouveau_object_del(&screen->sync);
 555
 556    nouveau_screen_fini(&screen->base);
 557
 558    FREE(screen);
 559 }
 560
 561 static void
 562 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 563 {
 564    struct nv50_screen *screen = nv50_screen(pscreen);
 565    struct nouveau_pushbuf *push = screen->base.pushbuf;
 566
 567    /* we need to do it after possible flush in MARK_RING */
 568    *sequence = ++screen->base.fence.sequence;
 569
 570    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 571    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 572    PUSH_DATAh(push, screen->fence.bo->offset);
 573    PUSH_DATA (push, screen->fence.bo->offset);
 574    PUSH_DATA (push, *sequence);
 575    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 576                     NV50_3D_QUERY_GET_UNK4 |
 577                     NV50_3D_QUERY_GET_UNIT_CROP |
 578                     NV50_3D_QUERY_GET_TYPE_QUERY |
 579                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 580                     NV50_3D_QUERY_GET_SHORT);
 581 }
 582
 583 static u32
 584 nv50_screen_fence_update(struct pipe_screen *pscreen)
 585 {
 586    return nv50_screen(pscreen)->fence.map[0];
 587 }
 588
 589 static void
 590 nv50_screen_init_hwctx(struct nv50_screen *screen)
 591 {
 592    struct nouveau_pushbuf *push = screen->base.pushbuf;
 593    struct nv04_fifo *fifo;
 594    unsigned i;
 595
 596    fifo = (struct nv04_fifo *)screen->base.channel->data;
 597
 598    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 599    PUSH_DATA (push, screen->m2mf->handle);
 600    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 601    PUSH_DATA (push, screen->sync->handle);
 602    PUSH_DATA (push, fifo->vram);
 603    PUSH_DATA (push, fifo->vram);
 604
 605    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 606    PUSH_DATA (push, screen->eng2d->handle);
 607    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 608    PUSH_DATA (push, screen->sync->handle);
 609    PUSH_DATA (push, fifo->vram);
 610    PUSH_DATA (push, fifo->vram);
 611    PUSH_DATA (push, fifo->vram);
 612    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 613    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 614    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 615    PUSH_DATA (push, 0);
 616    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 617    PUSH_DATA (push, 0);
 618    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 619    PUSH_DATA (push, 1);
 620    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 621    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 622
 623    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 624    PUSH_DATA (push, screen->tesla->handle);
 625
 626    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 627    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 628
 629    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 630    PUSH_DATA (push, screen->sync->handle);
 631    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 632    for (i = 0; i < 11; ++i)
 633       PUSH_DATA(push, fifo->vram);
 634    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 635    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 636       PUSH_DATA(push, fifo->vram);
 637
 638    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 639    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 640    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 641    PUSH_DATA (push, 0xf);
 642
 643    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 644       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 645       PUSH_DATA (push, 0x18);
 646    }
 647
 648    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 649    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 650
 651    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 652    for (i = 0; i < 8; ++i)
 653       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 654
 655    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 656    PUSH_DATA (push, 1);
 657
 658    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 659    PUSH_DATA (push, 0);
 660    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 661    PUSH_DATA (push, 0);
 662    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 663    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 664    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 665    PUSH_DATA (push, 0);
 666    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 667    PUSH_DATA (push, 1);
 668    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 669    PUSH_DATA (push, 1);
 670
 671    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 672       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 673       PUSH_DATA (push, 0);
 674    }
 675
 676    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 677    PUSH_DATA (push, 0);
 678    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 679    PUSH_DATA (push, 0);
 680    PUSH_DATA (push, 0);
 681    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 682    PUSH_DATA (push, 0x3f);
 683
 684    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 685    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 686    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 687
 688    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 689    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 690    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 691
 692    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 693    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 694    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 695
 696    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 697    PUSH_DATAh(push, screen->tls_bo->offset);
 698    PUSH_DATA (push, screen->tls_bo->offset);
 699    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 700
 701    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 702    PUSH_DATAh(push, screen->stack_bo->offset);
 703    PUSH_DATA (push, screen->stack_bo->offset);
 704    PUSH_DATA (push, 4);
 705
 706    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 707    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 708    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 709    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 710
 711    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 712    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 713    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 714    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 715
 716    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 717    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 718    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 719    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 720
 721    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 722    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 723    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 724    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 725
 726    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 727    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 728    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 729    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 730
 731    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 732    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 733    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 734    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 735    PUSH_DATAf(push, 0.0f);
 736    PUSH_DATAf(push, 0.0f);
 737    PUSH_DATAf(push, 0.0f);
 738    PUSH_DATAf(push, 0.0f);
 739    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 740    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 741    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 742
 743    nv50_upload_ms_info(push);
 744
 745    /* max TIC (bits 4:8) & TSC bindings, per program type */
 746    for (i = 0; i < 3; ++i) {
 747       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 748       PUSH_DATA (push, 0x54);
 749    }
 750
 751    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 752    PUSH_DATAh(push, screen->txc->offset);
 753    PUSH_DATA (push, screen->txc->offset);
 754    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 755
 756    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 757    PUSH_DATAh(push, screen->txc->offset + 65536);
 758    PUSH_DATA (push, screen->txc->offset + 65536);
 759    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 760
 761    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 762    PUSH_DATA (push, 0);
 763
 764    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 765    PUSH_DATA (push, 0);
 766    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 767    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 768    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 769    for (i = 0; i < 8 * 2; ++i)
 770       PUSH_DATA(push, 0);
 771    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 772    PUSH_DATA (push, 0);
 773
 774    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 775    PUSH_DATA (push, 1);
 776    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 777       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 778       PUSH_DATAf(push, 0.0f);
 779       PUSH_DATAf(push, 1.0f);
 780       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 781       PUSH_DATA (push, 8192 << 16);
 782       PUSH_DATA (push, 8192 << 16);
 783    }
 784
 785    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 786 #ifdef NV50_SCISSORS_CLIPPING
 787    PUSH_DATA (push, 0x0000);
 788 #else
 789    PUSH_DATA (push, 0x1080);
 790 #endif
 791
 792    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 793    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 794
 795    /* We use scissors instead of exact view volume clipping,
 796     * so they're always enabled.
 797     */
 798    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 799       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 800       PUSH_DATA (push, 1);
 801       PUSH_DATA (push, 8192 << 16);
 802       PUSH_DATA (push, 8192 << 16);
 803    }
 804
 805    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 806    PUSH_DATA (push, 1);
 807    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 808    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 809    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 810    PUSH_DATA (push, 0x11111111);
 811    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 812    PUSH_DATA (push, 1);
 813
 814    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 815    PUSH_DATA (push, 0);
 816    if (screen->base.class_3d >= NV84_3D_CLASS) {
 817       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 818       PUSH_DATA (push, 0);
 819    }
 820
 821    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 822    PUSH_DATA (push, 1);
 823    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 824    PUSH_DATA (push, 1);
 825
 826    PUSH_KICK (push);
 827 }
 828
 829 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 830       uint64_t *tls_size)
 831 {
 832    struct nouveau_device *dev = screen->base.device;
 833    int ret;
 834
 835    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 836          ONE_TEMP_SIZE;
 837    if (nouveau_mesa_debug)
 838       debug_printf("allocating space for %u temps\n",
 839             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 840    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 841          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 842
 843    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 844                         *tls_size, NULL, &screen->tls_bo);
 845    if (ret) {
 846       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 847       return ret;
 848    }
 849
 850    return 0;
 851 }
 852
 853 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 854 {
 855    struct nouveau_pushbuf *push = screen->base.pushbuf;
 856    int ret;
 857    uint64_t tls_size;
 858
 859    if (tls_space < screen->cur_tls_space)
 860       return 0;
 861    if (tls_space > screen->max_tls_space) {
 862       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 863        * LOCAL_WARPS_NO_CLAMP) */
 864       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 865             (unsigned)(tls_space / ONE_TEMP_SIZE),
 866             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 867       return -ENOMEM;
 868    }
 869
 870    nouveau_bo_ref(NULL, &screen->tls_bo);
 871    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 872    if (ret)
 873       return ret;
 874
 875    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 876    PUSH_DATAh(push, screen->tls_bo->offset);
 877    PUSH_DATA (push, screen->tls_bo->offset);
 878    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 879
 880    return 1;
 881 }
 882
 883 static const nir_shader_compiler_options nir_options = {
 884    .fuse_ffma = false, /* nir doesn't track mad vs fma */
 885    .lower_flrp32 = true,
 886    .lower_flrp64 = true,
 887    .lower_fpow = false,
 888    .lower_fmod64 = true,
 889    .lower_uadd_carry = true,
 890    .lower_usub_borrow = true,
 891    .lower_ffract = true,
 892    .lower_pack_half_2x16 = true,
 893    .lower_pack_unorm_2x16 = true,
 894    .lower_pack_snorm_2x16 = true,
 895    .lower_pack_unorm_4x8 = true,
 896    .lower_pack_snorm_4x8 = true,
 897    .lower_unpack_half_2x16 = true,
 898    .lower_unpack_unorm_2x16 = true,
 899    .lower_unpack_snorm_2x16 = true,
 900    .lower_unpack_unorm_4x8 = true,
 901    .lower_unpack_snorm_4x8 = true,
 902    .lower_extract_byte = true,
 903    .lower_extract_word = true,
 904    .lower_all_io_to_temps = false,
 905    .native_integers = true,
 906    .lower_cs_local_index_from_id = true,
 907    .use_interpolated_input_intrinsics = true,
 908    .max_unroll_iterations = 32,
 909 };
 910
 911 static const void *
 912 nv50_screen_get_compiler_options(struct pipe_screen *pscreen,
 913                                  enum pipe_shader_ir ir,
 914                                  enum pipe_shader_type shader)
 915 {
 916    if (ir == PIPE_SHADER_IR_NIR)
 917       return &nir_options;
 918    return NULL;
 919 }
 920
 921 struct nouveau_screen *
 922 nv50_screen_create(struct nouveau_device *dev)
 923 {
 924    struct nv50_screen *screen;
 925    struct pipe_screen *pscreen;
 926    struct nouveau_object *chan;
 927    uint64_t value;
 928    uint32_t tesla_class;
 929    unsigned stack_size;
 930    int ret;
 931
 932    screen = CALLOC_STRUCT(nv50_screen);
 933    if (!screen)
 934       return NULL;
 935    pscreen = &screen->base.base;
 936    pscreen->destroy = nv50_screen_destroy;
 937
 938    ret = nouveau_screen_init(&screen->base, dev);
 939    if (ret) {
 940       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 941       goto fail;
 942    }
 943
 944    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 945     *  admit them to VRAM.
 946     */
 947    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 948       PIPE_BIND_VERTEX_BUFFER;
 949    screen->base.sysmem_bindings |=
 950       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 951
 952    screen->base.pushbuf->user_priv = screen;
 953    screen->base.pushbuf->rsvd_kick = 5;
 954
 955    chan = screen->base.channel;
 956
 957    pscreen->context_create = nv50_create;
 958    pscreen->is_format_supported = nv50_screen_is_format_supported;
 959    pscreen->get_param = nv50_screen_get_param;
 960    pscreen->get_shader_param = nv50_screen_get_shader_param;
 961    pscreen->get_paramf = nv50_screen_get_paramf;
 962    pscreen->get_compute_param = nv50_screen_get_compute_param;
 963    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 964    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 965
 966    /* nir stuff */
 967    pscreen->get_compiler_options = nv50_screen_get_compiler_options;
 968
 969    nv50_screen_init_resource_functions(pscreen);
 970
 971    if (screen->base.device->chipset < 0x84 ||
 972        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 973       /* PMPEG */
 974       nouveau_screen_init_vdec(&screen->base);
 975    } else if (screen->base.device->chipset < 0x98 ||
 976               screen->base.device->chipset == 0xa0) {
 977       /* VP2 */
 978       screen->base.base.get_video_param = nv84_screen_get_video_param;
 979       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 980    } else {
 981       /* VP3/4 */
 982       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 983       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 984    }
 985
 986    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 987                         NULL, &screen->fence.bo);
 988    if (ret) {
 989       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 990       goto fail;
 991    }
 992
 993    nouveau_bo_map(screen->fence.bo, 0, NULL);
 994    screen->fence.map = screen->fence.bo->map;
 995    screen->base.fence.emit = nv50_screen_fence_emit;
 996    screen->base.fence.update = nv50_screen_fence_update;
 997
 998    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 999                             &(struct nv04_notify){ .length = 32 },
1000                             sizeof(struct nv04_notify), &screen->sync);
1001    if (ret) {
1002       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
1003       goto fail;
1004    }
1005
1006    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
1007                             NULL, 0, &screen->m2mf);
1008    if (ret) {
1009       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
1010       goto fail;
1011    }
1012
1013    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
1014                             NULL, 0, &screen->eng2d);
1015    if (ret) {
1016       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
1017       goto fail;
1018    }
1019
1020    switch (dev->chipset & 0xf0) {
1021    case 0x50:
1022       tesla_class = NV50_3D_CLASS;
1023       break;
1024    case 0x80:
1025    case 0x90:
1026       tesla_class = NV84_3D_CLASS;
1027       break;
1028    case 0xa0:
1029       switch (dev->chipset) {
1030       case 0xa0:
1031       case 0xaa:
1032       case 0xac:
1033          tesla_class = NVA0_3D_CLASS;
1034          break;
1035       case 0xaf:
1036          tesla_class = NVAF_3D_CLASS;
1037          break;
1038       default:
1039          tesla_class = NVA3_3D_CLASS;
1040          break;
1041       }
1042       break;
1043    default:
1044       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
1045       goto fail;
1046    }
1047    screen->base.class_3d = tesla_class;
1048
1049    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
1050                             NULL, 0, &screen->tesla);
1051    if (ret) {
1052       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
1053       goto fail;
1054    }
1055
1056    /* This over-allocates by a page. The GP, which would execute at the end of
1057     * the last page, would trigger faults. The going theory is that it
1058     * prefetches up to a certain amount.
1059     */
1060    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
1061                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
1062                         NULL, &screen->code);
1063    if (ret) {
1064       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
1065       goto fail;
1066    }
1067
1068    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1069    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1070    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1071
1072    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1073
1074    screen->TPs = util_bitcount(value & 0xffff);
1075    screen->MPsInTP = util_bitcount(value & 0x0f000000);
1076
1077    screen->mp_count = screen->TPs * screen->MPsInTP;
1078
1079    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1080          STACK_WARPS_ALLOC * 64 * 8;
1081
1082    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1083                         &screen->stack_bo);
1084    if (ret) {
1085       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1086       goto fail;
1087    }
1088
1089    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1090          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1091          ONE_TEMP_SIZE;
1092    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1093    screen->max_tls_space /= 2; /* half of vram */
1094
1095    /* hw can address max 64 KiB */
1096    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1097
1098    uint64_t tls_size;
1099    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1100    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1101    if (ret)
1102       goto fail;
1103
1104    if (nouveau_mesa_debug)
1105       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1106             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1107
1108    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1109                         &screen->uniforms);
1110    if (ret) {
1111       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1112       goto fail;
1113    }
1114
1115    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1116                         &screen->txc);
1117    if (ret) {
1118       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1119       goto fail;
1120    }
1121
1122    screen->tic.entries = CALLOC(4096, sizeof(void *));
1123    screen->tsc.entries = screen->tic.entries + 2048;
1124
1125    if (!nv50_blitter_create(screen))
1126       goto fail;
1127
1128    nv50_screen_init_hwctx(screen);
1129
1130    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1131    if (ret) {
1132       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1133       goto fail;
1134    }
1135
1136    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1137
1138    return &screen->base;
1139
1140 fail:
1141    screen->base.base.context_create = NULL;
1142    return &screen->base;
1143 }
1144
1145 int
1146 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1147 {
1148    int i = screen->tic.next;
1149
1150    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1151       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1152
1153    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1154
1155    if (screen->tic.entries[i])
1156       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1157
1158    screen->tic.entries[i] = entry;
1159    return i;
1160 }
1161
1162 int
1163 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1164 {
1165    int i = screen->tsc.next;
1166
1167    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1168       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1169
1170    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1171
1172    if (screen->tsc.entries[i])
1173       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1174
1175    screen->tsc.entries[i] = entry;
1176    return i;
1177 }