2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <nouveau_drm.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
30 #include "nv50/nv50_context.h"
31 #include "nv50/nv50_screen.h"
33 #include "nouveau_vp3_video.h"
35 #include "nv_object.xml.h"
37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
38 #define LOCAL_WARPS_ALLOC 32
39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
40 #define STACK_WARPS_ALLOC 32
42 #define THREADS_IN_WARP 32
44 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
47 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
48 enum pipe_format format
,
49 enum pipe_texture_target target
,
50 unsigned sample_count
,
55 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
57 if (sample_count
== 8 && util_format_get_blocksizebits(format
) >= 128)
60 if (!util_format_is_supported(format
, bindings
))
64 case PIPE_FORMAT_Z16_UNORM
:
65 if (nv50_screen(pscreen
)->tesla
->oclass
< NVA0_3D_CLASS
)
72 /* transfers & shared are always supported */
73 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
74 PIPE_BIND_TRANSFER_WRITE
|
77 return (nv50_format_table
[format
].usage
& bindings
) == bindings
;
81 nv50_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
83 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
84 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
87 /* non-boolean caps */
88 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
90 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
92 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
94 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
96 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
97 case PIPE_CAP_MIN_TEXEL_OFFSET
:
99 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
100 case PIPE_CAP_MAX_TEXEL_OFFSET
:
102 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
103 return 128 * 1024 * 1024;
104 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
106 case PIPE_CAP_MAX_RENDER_TARGETS
:
108 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
110 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
112 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
113 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
115 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
116 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
118 case PIPE_CAP_MAX_VERTEX_STREAMS
:
120 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
122 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
124 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
125 return 1; /* 256 for binding as RT, but that's not possible in GL */
126 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
127 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
128 case PIPE_CAP_MAX_VIEWPORTS
:
129 return NV50_MAX_VIEWPORTS
;
130 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
131 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50
;
132 case PIPE_CAP_ENDIANNESS
:
133 return PIPE_ENDIAN_LITTLE
;
134 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
135 return (class_3d
>= NVA3_3D_CLASS
) ? 4 : 0;
138 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
139 case PIPE_CAP_TEXTURE_SWIZZLE
:
140 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
141 case PIPE_CAP_NPOT_TEXTURES
:
142 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
143 case PIPE_CAP_ANISOTROPIC_FILTER
:
144 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
145 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
146 case PIPE_CAP_TWO_SIDED_STENCIL
:
147 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
148 case PIPE_CAP_POINT_SPRITE
:
150 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
151 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
152 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
153 case PIPE_CAP_QUERY_TIMESTAMP
:
154 case PIPE_CAP_QUERY_TIME_ELAPSED
:
155 case PIPE_CAP_OCCLUSION_QUERY
:
156 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
157 case PIPE_CAP_INDEP_BLEND_ENABLE
:
158 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
159 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
160 case PIPE_CAP_PRIMITIVE_RESTART
:
161 case PIPE_CAP_TGSI_INSTANCEID
:
162 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
163 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
164 case PIPE_CAP_CONDITIONAL_RENDER
:
165 case PIPE_CAP_TEXTURE_BARRIER
:
166 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
167 case PIPE_CAP_START_INSTANCE
:
168 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
169 case PIPE_CAP_USER_INDEX_BUFFERS
:
170 case PIPE_CAP_USER_VERTEX_BUFFERS
:
171 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
172 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
173 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
174 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
175 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
176 case PIPE_CAP_CLIP_HALFZ
:
177 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
178 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
179 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
180 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
181 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
182 case PIPE_CAP_TGSI_TXQS
:
183 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
185 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
186 return 1; /* class_3d >= NVA0_3D_CLASS; */
187 /* supported on nva0+ */
188 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
189 return class_3d
>= NVA0_3D_CLASS
;
190 /* supported on nva3+ */
191 case PIPE_CAP_CUBE_MAP_ARRAY
:
192 case PIPE_CAP_INDEP_BLEND_FUNC
:
193 case PIPE_CAP_TEXTURE_QUERY_LOD
:
194 case PIPE_CAP_SAMPLE_SHADING
:
195 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
196 return class_3d
>= NVA3_3D_CLASS
;
198 /* unsupported caps */
199 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
200 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
201 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
202 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
203 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
204 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
205 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
206 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
207 case PIPE_CAP_TGSI_TEXCOORD
:
208 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
209 case PIPE_CAP_TEXTURE_GATHER_SM5
:
210 case PIPE_CAP_FAKE_SW_MSAA
:
211 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
212 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
213 case PIPE_CAP_COMPUTE
:
214 case PIPE_CAP_DRAW_INDIRECT
:
215 case PIPE_CAP_VERTEXID_NOBASE
:
216 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
: /* potentially supported on some hw */
217 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
218 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
219 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
220 case PIPE_CAP_SHAREABLE_SHADERS
:
223 case PIPE_CAP_VENDOR_ID
:
225 case PIPE_CAP_DEVICE_ID
: {
227 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
228 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
233 case PIPE_CAP_ACCELERATED
:
235 case PIPE_CAP_VIDEO_MEMORY
:
236 return dev
->vram_size
>> 20;
241 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
246 nv50_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
247 enum pipe_shader_cap param
)
250 case PIPE_SHADER_VERTEX
:
251 case PIPE_SHADER_GEOMETRY
:
252 case PIPE_SHADER_FRAGMENT
:
259 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
260 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
261 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
262 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
264 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
266 case PIPE_SHADER_CAP_MAX_INPUTS
:
267 if (shader
== PIPE_SHADER_VERTEX
)
270 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
272 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
274 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
275 return NV50_MAX_PIPE_CONSTBUFS
;
276 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
277 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
278 return shader
!= PIPE_SHADER_FRAGMENT
;
279 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
280 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
282 case PIPE_SHADER_CAP_MAX_PREDS
:
284 case PIPE_SHADER_CAP_MAX_TEMPS
:
285 return nv50_screen(pscreen
)->max_tls_space
/ ONE_TEMP_SIZE
;
286 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
288 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
290 case PIPE_SHADER_CAP_SUBROUTINES
:
291 return 0; /* please inline, or provide function declarations */
292 case PIPE_SHADER_CAP_INTEGERS
:
294 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
295 /* The chip could handle more sampler views than samplers */
296 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
297 return MIN2(16, PIPE_MAX_SAMPLERS
);
298 case PIPE_SHADER_CAP_DOUBLES
:
299 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
300 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
301 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
302 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
304 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
307 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
313 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
316 case PIPE_CAPF_MAX_LINE_WIDTH
:
317 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
319 case PIPE_CAPF_MAX_POINT_WIDTH
:
320 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
322 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
324 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
326 case PIPE_CAPF_GUARD_BAND_LEFT
:
327 case PIPE_CAPF_GUARD_BAND_TOP
:
329 case PIPE_CAPF_GUARD_BAND_RIGHT
:
330 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
331 return 0.0f
; /* that or infinity */
334 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param
);
339 nv50_screen_destroy(struct pipe_screen
*pscreen
)
341 struct nv50_screen
*screen
= nv50_screen(pscreen
);
343 if (!nouveau_drm_screen_unref(&screen
->base
))
346 if (screen
->base
.fence
.current
) {
347 struct nouveau_fence
*current
= NULL
;
349 /* nouveau_fence_wait will create a new current fence, so wait on the
350 * _current_ one, and remove both.
352 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
353 nouveau_fence_wait(current
);
354 nouveau_fence_ref(NULL
, ¤t
);
355 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
357 if (screen
->base
.pushbuf
)
358 screen
->base
.pushbuf
->user_priv
= NULL
;
361 nv50_blitter_destroy(screen
);
363 nouveau_bo_ref(NULL
, &screen
->code
);
364 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
365 nouveau_bo_ref(NULL
, &screen
->stack_bo
);
366 nouveau_bo_ref(NULL
, &screen
->txc
);
367 nouveau_bo_ref(NULL
, &screen
->uniforms
);
368 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
370 nouveau_heap_destroy(&screen
->vp_code_heap
);
371 nouveau_heap_destroy(&screen
->gp_code_heap
);
372 nouveau_heap_destroy(&screen
->fp_code_heap
);
374 FREE(screen
->tic
.entries
);
376 nouveau_object_del(&screen
->tesla
);
377 nouveau_object_del(&screen
->eng2d
);
378 nouveau_object_del(&screen
->m2mf
);
379 nouveau_object_del(&screen
->sync
);
381 nouveau_screen_fini(&screen
->base
);
387 nv50_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
389 struct nv50_screen
*screen
= nv50_screen(pscreen
);
390 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
392 /* we need to do it after possible flush in MARK_RING */
393 *sequence
= ++screen
->base
.fence
.sequence
;
395 assert(PUSH_AVAIL(push
) >= 5);
396 PUSH_DATA (push
, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH
), 4));
397 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
398 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
399 PUSH_DATA (push
, *sequence
);
400 PUSH_DATA (push
, NV50_3D_QUERY_GET_MODE_WRITE_UNK0
|
401 NV50_3D_QUERY_GET_UNK4
|
402 NV50_3D_QUERY_GET_UNIT_CROP
|
403 NV50_3D_QUERY_GET_TYPE_QUERY
|
404 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO
|
405 NV50_3D_QUERY_GET_SHORT
);
409 nv50_screen_fence_update(struct pipe_screen
*pscreen
)
411 return nv50_screen(pscreen
)->fence
.map
[0];
415 nv50_screen_init_hwctx(struct nv50_screen
*screen
)
417 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
418 struct nv04_fifo
*fifo
;
421 fifo
= (struct nv04_fifo
*)screen
->base
.channel
->data
;
423 BEGIN_NV04(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
424 PUSH_DATA (push
, screen
->m2mf
->handle
);
425 BEGIN_NV04(push
, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY
), 3);
426 PUSH_DATA (push
, screen
->sync
->handle
);
427 PUSH_DATA (push
, fifo
->vram
);
428 PUSH_DATA (push
, fifo
->vram
);
430 BEGIN_NV04(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
431 PUSH_DATA (push
, screen
->eng2d
->handle
);
432 BEGIN_NV04(push
, NV50_2D(DMA_NOTIFY
), 4);
433 PUSH_DATA (push
, screen
->sync
->handle
);
434 PUSH_DATA (push
, fifo
->vram
);
435 PUSH_DATA (push
, fifo
->vram
);
436 PUSH_DATA (push
, fifo
->vram
);
437 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
438 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
439 BEGIN_NV04(push
, NV50_2D(CLIP_ENABLE
), 1);
441 BEGIN_NV04(push
, NV50_2D(COLOR_KEY_ENABLE
), 1);
443 BEGIN_NV04(push
, SUBC_2D(0x0888), 1);
445 BEGIN_NV04(push
, NV50_2D(COND_MODE
), 1);
446 PUSH_DATA (push
, NV50_2D_COND_MODE_ALWAYS
);
448 BEGIN_NV04(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
449 PUSH_DATA (push
, screen
->tesla
->handle
);
451 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
452 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
454 BEGIN_NV04(push
, NV50_3D(DMA_NOTIFY
), 1);
455 PUSH_DATA (push
, screen
->sync
->handle
);
456 BEGIN_NV04(push
, NV50_3D(DMA_ZETA
), 11);
457 for (i
= 0; i
< 11; ++i
)
458 PUSH_DATA(push
, fifo
->vram
);
459 BEGIN_NV04(push
, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN
);
460 for (i
= 0; i
< NV50_3D_DMA_COLOR__LEN
; ++i
)
461 PUSH_DATA(push
, fifo
->vram
);
463 BEGIN_NV04(push
, NV50_3D(REG_MODE
), 1);
464 PUSH_DATA (push
, NV50_3D_REG_MODE_STRIPED
);
465 BEGIN_NV04(push
, NV50_3D(UNK1400_LANES
), 1);
466 PUSH_DATA (push
, 0xf);
468 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
469 BEGIN_NV04(push
, NV50_3D(WATCHDOG_TIMER
), 1);
470 PUSH_DATA (push
, 0x18);
473 BEGIN_NV04(push
, NV50_3D(ZETA_COMP_ENABLE
), 1);
474 PUSH_DATA(push
, screen
->base
.device
->drm_version
>= 0x01000101);
476 BEGIN_NV04(push
, NV50_3D(RT_COMP_ENABLE(0)), 8);
477 for (i
= 0; i
< 8; ++i
)
478 PUSH_DATA(push
, screen
->base
.device
->drm_version
>= 0x01000101);
480 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
483 BEGIN_NV04(push
, NV50_3D(CSAA_ENABLE
), 1);
485 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_ENABLE
), 1);
487 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
488 PUSH_DATA (push
, NV50_3D_MULTISAMPLE_MODE_MS1
);
489 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_CTRL
), 1);
491 BEGIN_NV04(push
, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS
), 1);
493 BEGIN_NV04(push
, NV50_3D(BLEND_SEPARATE_ALPHA
), 1);
496 if (screen
->tesla
->oclass
>= NVA0_3D_CLASS
) {
497 BEGIN_NV04(push
, SUBC_3D(NVA0_3D_TEX_MISC
), 1);
498 PUSH_DATA (push
, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP
);
501 BEGIN_NV04(push
, NV50_3D(SCREEN_Y_CONTROL
), 1);
503 BEGIN_NV04(push
, NV50_3D(WINDOW_OFFSET_X
), 2);
506 BEGIN_NV04(push
, NV50_3D(ZCULL_REGION
), 1);
507 PUSH_DATA (push
, 0x3f);
509 BEGIN_NV04(push
, NV50_3D(VP_ADDRESS_HIGH
), 2);
510 PUSH_DATAh(push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
511 PUSH_DATA (push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
513 BEGIN_NV04(push
, NV50_3D(FP_ADDRESS_HIGH
), 2);
514 PUSH_DATAh(push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
515 PUSH_DATA (push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
517 BEGIN_NV04(push
, NV50_3D(GP_ADDRESS_HIGH
), 2);
518 PUSH_DATAh(push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
519 PUSH_DATA (push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
521 BEGIN_NV04(push
, NV50_3D(LOCAL_ADDRESS_HIGH
), 3);
522 PUSH_DATAh(push
, screen
->tls_bo
->offset
);
523 PUSH_DATA (push
, screen
->tls_bo
->offset
);
524 PUSH_DATA (push
, util_logbase2(screen
->cur_tls_space
/ 8));
526 BEGIN_NV04(push
, NV50_3D(STACK_ADDRESS_HIGH
), 3);
527 PUSH_DATAh(push
, screen
->stack_bo
->offset
);
528 PUSH_DATA (push
, screen
->stack_bo
->offset
);
531 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
532 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (0 << 16));
533 PUSH_DATA (push
, screen
->uniforms
->offset
+ (0 << 16));
534 PUSH_DATA (push
, (NV50_CB_PVP
<< 16) | 0x0000);
536 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
537 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (1 << 16));
538 PUSH_DATA (push
, screen
->uniforms
->offset
+ (1 << 16));
539 PUSH_DATA (push
, (NV50_CB_PGP
<< 16) | 0x0000);
541 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
542 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (2 << 16));
543 PUSH_DATA (push
, screen
->uniforms
->offset
+ (2 << 16));
544 PUSH_DATA (push
, (NV50_CB_PFP
<< 16) | 0x0000);
546 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
547 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (3 << 16));
548 PUSH_DATA (push
, screen
->uniforms
->offset
+ (3 << 16));
549 PUSH_DATA (push
, (NV50_CB_AUX
<< 16) | (NV50_CB_AUX_SIZE
& 0xffff));
551 BEGIN_NI04(push
, NV50_3D(SET_PROGRAM_CB
), 3);
552 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf01);
553 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf21);
554 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf31);
556 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
557 BEGIN_NV04(push
, NV50_3D(CB_ADDR
), 1);
558 PUSH_DATA (push
, (NV50_CB_AUX_RUNOUT_OFFSET
<< (8 - 2)) | NV50_CB_AUX
);
559 BEGIN_NI04(push
, NV50_3D(CB_DATA(0)), 4);
560 PUSH_DATAf(push
, 0.0f
);
561 PUSH_DATAf(push
, 0.0f
);
562 PUSH_DATAf(push
, 0.0f
);
563 PUSH_DATAf(push
, 0.0f
);
564 BEGIN_NV04(push
, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
565 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET
);
566 PUSH_DATA (push
, screen
->uniforms
->offset
+ (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET
);
568 nv50_upload_ms_info(push
);
570 /* max TIC (bits 4:8) & TSC bindings, per program type */
571 for (i
= 0; i
< 3; ++i
) {
572 BEGIN_NV04(push
, NV50_3D(TEX_LIMITS(i
)), 1);
573 PUSH_DATA (push
, 0x54);
576 BEGIN_NV04(push
, NV50_3D(TIC_ADDRESS_HIGH
), 3);
577 PUSH_DATAh(push
, screen
->txc
->offset
);
578 PUSH_DATA (push
, screen
->txc
->offset
);
579 PUSH_DATA (push
, NV50_TIC_MAX_ENTRIES
- 1);
581 BEGIN_NV04(push
, NV50_3D(TSC_ADDRESS_HIGH
), 3);
582 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
583 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
584 PUSH_DATA (push
, NV50_TSC_MAX_ENTRIES
- 1);
586 BEGIN_NV04(push
, NV50_3D(LINKED_TSC
), 1);
589 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_EN
), 1);
591 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_MODE
), 1);
592 PUSH_DATA (push
, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
593 BEGIN_NV04(push
, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
594 for (i
= 0; i
< 8 * 2; ++i
)
596 BEGIN_NV04(push
, NV50_3D(CLIPID_ENABLE
), 1);
599 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
601 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
602 BEGIN_NV04(push
, NV50_3D(DEPTH_RANGE_NEAR(i
)), 2);
603 PUSH_DATAf(push
, 0.0f
);
604 PUSH_DATAf(push
, 1.0f
);
605 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(i
)), 2);
606 PUSH_DATA (push
, 8192 << 16);
607 PUSH_DATA (push
, 8192 << 16);
610 BEGIN_NV04(push
, NV50_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
611 #ifdef NV50_SCISSORS_CLIPPING
612 PUSH_DATA (push
, 0x0000);
614 PUSH_DATA (push
, 0x1080);
617 BEGIN_NV04(push
, NV50_3D(CLEAR_FLAGS
), 1);
618 PUSH_DATA (push
, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT
);
620 /* We use scissors instead of exact view volume clipping,
621 * so they're always enabled.
623 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
624 BEGIN_NV04(push
, NV50_3D(SCISSOR_ENABLE(i
)), 3);
626 PUSH_DATA (push
, 8192 << 16);
627 PUSH_DATA (push
, 8192 << 16);
630 BEGIN_NV04(push
, NV50_3D(RASTERIZE_ENABLE
), 1);
632 BEGIN_NV04(push
, NV50_3D(POINT_RASTER_RULES
), 1);
633 PUSH_DATA (push
, NV50_3D_POINT_RASTER_RULES_OGL
);
634 BEGIN_NV04(push
, NV50_3D(FRAG_COLOR_CLAMP_EN
), 1);
635 PUSH_DATA (push
, 0x11111111);
636 BEGIN_NV04(push
, NV50_3D(EDGEFLAG
), 1);
639 BEGIN_NV04(push
, NV50_3D(VB_ELEMENT_BASE
), 1);
641 if (screen
->base
.class_3d
>= NV84_3D_CLASS
) {
642 BEGIN_NV04(push
, SUBC_3D(NV84_3D_VERTEX_ID_BASE
), 1);
649 static int nv50_tls_alloc(struct nv50_screen
*screen
, unsigned tls_space
,
652 struct nouveau_device
*dev
= screen
->base
.device
;
655 screen
->cur_tls_space
= util_next_power_of_two(tls_space
/ ONE_TEMP_SIZE
) *
657 if (nouveau_mesa_debug
)
658 debug_printf("allocating space for %u temps\n",
659 util_next_power_of_two(tls_space
/ ONE_TEMP_SIZE
));
660 *tls_size
= screen
->cur_tls_space
* util_next_power_of_two(screen
->TPs
) *
661 screen
->MPsInTP
* LOCAL_WARPS_ALLOC
* THREADS_IN_WARP
;
663 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
664 *tls_size
, NULL
, &screen
->tls_bo
);
666 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret
);
673 int nv50_tls_realloc(struct nv50_screen
*screen
, unsigned tls_space
)
675 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
679 if (tls_space
< screen
->cur_tls_space
)
681 if (tls_space
> screen
->max_tls_space
) {
682 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
683 * LOCAL_WARPS_NO_CLAMP) */
684 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
685 (unsigned)(tls_space
/ ONE_TEMP_SIZE
),
686 (unsigned)(screen
->max_tls_space
/ ONE_TEMP_SIZE
));
690 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
691 ret
= nv50_tls_alloc(screen
, tls_space
, &tls_size
);
695 BEGIN_NV04(push
, NV50_3D(LOCAL_ADDRESS_HIGH
), 3);
696 PUSH_DATAh(push
, screen
->tls_bo
->offset
);
697 PUSH_DATA (push
, screen
->tls_bo
->offset
);
698 PUSH_DATA (push
, util_logbase2(screen
->cur_tls_space
/ 8));
704 nv50_screen_create(struct nouveau_device
*dev
)
706 struct nv50_screen
*screen
;
707 struct pipe_screen
*pscreen
;
708 struct nouveau_object
*chan
;
710 uint32_t tesla_class
;
714 screen
= CALLOC_STRUCT(nv50_screen
);
717 pscreen
= &screen
->base
.base
;
719 ret
= nouveau_screen_init(&screen
->base
, dev
);
721 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret
);
725 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
726 * admit them to VRAM.
728 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
729 PIPE_BIND_VERTEX_BUFFER
;
730 screen
->base
.sysmem_bindings
|=
731 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
733 screen
->base
.pushbuf
->user_priv
= screen
;
734 screen
->base
.pushbuf
->rsvd_kick
= 5;
736 chan
= screen
->base
.channel
;
738 pscreen
->destroy
= nv50_screen_destroy
;
739 pscreen
->context_create
= nv50_create
;
740 pscreen
->is_format_supported
= nv50_screen_is_format_supported
;
741 pscreen
->get_param
= nv50_screen_get_param
;
742 pscreen
->get_shader_param
= nv50_screen_get_shader_param
;
743 pscreen
->get_paramf
= nv50_screen_get_paramf
;
745 nv50_screen_init_resource_functions(pscreen
);
747 if (screen
->base
.device
->chipset
< 0x84 ||
748 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
750 nouveau_screen_init_vdec(&screen
->base
);
751 } else if (screen
->base
.device
->chipset
< 0x98 ||
752 screen
->base
.device
->chipset
== 0xa0) {
754 screen
->base
.base
.get_video_param
= nv84_screen_get_video_param
;
755 screen
->base
.base
.is_video_format_supported
= nv84_screen_video_supported
;
758 screen
->base
.base
.get_video_param
= nouveau_vp3_screen_get_video_param
;
759 screen
->base
.base
.is_video_format_supported
= nouveau_vp3_screen_video_supported
;
762 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096,
763 NULL
, &screen
->fence
.bo
);
765 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret
);
769 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
770 screen
->fence
.map
= screen
->fence
.bo
->map
;
771 screen
->base
.fence
.emit
= nv50_screen_fence_emit
;
772 screen
->base
.fence
.update
= nv50_screen_fence_update
;
774 ret
= nouveau_object_new(chan
, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS
,
775 &(struct nv04_notify
){ .length
= 32 },
776 sizeof(struct nv04_notify
), &screen
->sync
);
778 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret
);
782 ret
= nouveau_object_new(chan
, 0xbeef5039, NV50_M2MF_CLASS
,
783 NULL
, 0, &screen
->m2mf
);
785 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret
);
789 ret
= nouveau_object_new(chan
, 0xbeef502d, NV50_2D_CLASS
,
790 NULL
, 0, &screen
->eng2d
);
792 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret
);
796 switch (dev
->chipset
& 0xf0) {
798 tesla_class
= NV50_3D_CLASS
;
802 tesla_class
= NV84_3D_CLASS
;
805 switch (dev
->chipset
) {
809 tesla_class
= NVA0_3D_CLASS
;
812 tesla_class
= NVAF_3D_CLASS
;
815 tesla_class
= NVA3_3D_CLASS
;
820 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev
->chipset
);
823 screen
->base
.class_3d
= tesla_class
;
825 ret
= nouveau_object_new(chan
, 0xbeef5097, tesla_class
,
826 NULL
, 0, &screen
->tesla
);
828 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret
);
832 /* This over-allocates by a page. The GP, which would execute at the end of
833 * the last page, would trigger faults. The going theory is that it
834 * prefetches up to a certain amount.
836 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
837 (3 << NV50_CODE_BO_SIZE_LOG2
) + 0x1000,
838 NULL
, &screen
->code
);
840 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret
);
844 nouveau_heap_init(&screen
->vp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
845 nouveau_heap_init(&screen
->gp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
846 nouveau_heap_init(&screen
->fp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
848 nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
850 screen
->TPs
= util_bitcount(value
& 0xffff);
851 screen
->MPsInTP
= util_bitcount((value
>> 24) & 0xf);
853 stack_size
= util_next_power_of_two(screen
->TPs
) * screen
->MPsInTP
*
854 STACK_WARPS_ALLOC
* 64 * 8;
856 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, stack_size
, NULL
,
859 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret
);
863 uint64_t size_of_one_temp
= util_next_power_of_two(screen
->TPs
) *
864 screen
->MPsInTP
* LOCAL_WARPS_ALLOC
* THREADS_IN_WARP
*
866 screen
->max_tls_space
= dev
->vram_size
/ size_of_one_temp
* ONE_TEMP_SIZE
;
867 screen
->max_tls_space
/= 2; /* half of vram */
869 /* hw can address max 64 KiB */
870 screen
->max_tls_space
= MIN2(screen
->max_tls_space
, 64 << 10);
873 unsigned tls_space
= 4/*temps*/ * ONE_TEMP_SIZE
;
874 ret
= nv50_tls_alloc(screen
, tls_space
, &tls_size
);
878 if (nouveau_mesa_debug
)
879 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64
" MiB, tls_size = %"PRIu64
" KiB\n",
880 screen
->TPs
, screen
->MPsInTP
, dev
->vram_size
>> 20, tls_size
>> 10);
882 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 4 << 16, NULL
,
885 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret
);
889 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 3 << 16, NULL
,
892 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret
);
896 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
897 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
899 if (!nv50_blitter_create(screen
))
902 nv50_screen_init_hwctx(screen
);
904 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, false);
909 nv50_screen_destroy(pscreen
);
914 nv50_screen_tic_alloc(struct nv50_screen
*screen
, void *entry
)
916 int i
= screen
->tic
.next
;
918 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
919 i
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
921 screen
->tic
.next
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
923 if (screen
->tic
.entries
[i
])
924 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
926 screen
->tic
.entries
[i
] = entry
;
931 nv50_screen_tsc_alloc(struct nv50_screen
*screen
, void *entry
)
933 int i
= screen
->tsc
.next
;
935 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
936 i
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
938 screen
->tsc
.next
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
940 if (screen
->tsc
.entries
[i
])
941 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
943 screen
->tsc
.entries
[i
] = entry
;